DETAILED ACTION
This Office Action is in response to the Remarks and Amendments filed on 23 May 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Herner (US 11,004,895 B1; hereinafter Herner), in view of Yeon et al. (US 2017/0250316 A1; hereinafter Yeon), in view of Gomes et al. (US 12,170,273 B2 hereinafter Gomes).
In regards to claim 1, Herner teaches a light-emitting diode package (fig. 3), comprising:
a redistribution layer (the layers below (270) containing (40));
a light-emitting diode (20) disposed on the redistribution layer and electrically connected to the redistribution layer, wherein the light-emitting diode comprises a first light-emitting diode (rightmost LED in fig. 3), a second light-emitting diode (middle LED in fig. 3), a third light-emitting diode (leftmost LED in fig. 3), and electrodes (230);
a first dielectric layer ((240) in fig. 7B) disposed on the redistribution layer and covering the light-emitting diode;
a plurality of wavelength conversion structures (80a, 80b) disposed on the second light- emitting diode and the third light-emitting; and
a transparent encapsulant ((600); fig. 10F) disposed on the first dielectric layer and covering the plurality of wavelength conversion structures,
wherein the electrodes of the light-emitting diode are not disposed on a surface of the light-emitting diode facing the plurality of wavelength conversion structures (fig. 3 shows the electrodes 230 on a surface of the LEDs not facing the wavelength conversion structures);
a circuit board ((540); fig. 10D; backboard (540) may comprise a printed circuit board (PCB)) (col. 20/ln. 2)) having a first surface (bottom of (540)) and a second surface (top of (540)) opposite to the first surface, and the redistribution layer is disposed on the second surface of the circuit board;
a conductive terminal (60) disposed on the second surface of the circuit board and connected to the circuit board and the redistribution layer; and
an electronic element (data lines (60), select lines (70), and power lines (72) (col. 19/ln. 67, col. 20/ln. 1) disposed on the first surface of the circuit board (540) and electrically connected to the light-emitting diode (22).
Herner appears to be silent as to, but does not preclude, the limitations of the wavelength structures are respectively in contact with the second light-emitting diode and the third light-emitting diode. Yeon teaches, e.g. in figs. 1-3, that it was known and predictably effective to use wavelength structures ([0049]: (128), (130), (132)) that contact light emitters ([0050]: (110)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to substitute the Yeon contacting configuration of an LED package for the analogous Herner configuration as a substitution of one known element for another that yields predictable results to one of ordinary skill in the art would have been obvious. MPEP §2143 I (B).
The combination of Herner and Yeon appears to be silent as to, but does not preclude the limitations wherein the electronic element and the redistribution layer are located on opposite sides of the circuit board. Gomes teaches the limitations wherein the electronic element (112) (col. 7/lns. 16-21) and the redistribution layer (140) (col. 6/lns. 50-55) are located on opposite sides of the circuit board (110) (col. 7/lns. 14-16). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the device taught by the combination of Herner and Yeon with the aforementioned limitations taught by Gomes to have the layout taught by Gomes to have optimized IC dies with smaller package sizes (Gomes col. 1/lns. 30-35).
In regards to claim 2, the combination of Herner, Yeon, and Gomes teaches the limitations discussed above in addressing claim 1. Herner further teaches the limitations wherein the light-emitting diode package does not have a native epitaxy substrate (col. 10/lns 29-31: “LED fabrication will occur on an LED substrate, although the LED substrate will be removed in a subsequent step”).
In regards to claim 3, the combination of Herner, Yeon, and Gomes teaches the limitations discussed above in addressing claim 1. Herner further teaches the limitations further comprising: a first conductive through hole (the hole containing (270)) penetrating a surface of the first dielectric layer (240) facing the redistribution layer and connected to the redistribution layer and the light-emitting diode (22).
In regards to claim 6, the combination of Herner, Yeon, and Gomes teaches the limitations discussed above in addressing claim 1. Herner further teaches the limitations wherein the circuit board comprises a core layer, a first build-up circuit structure, a second build-up circuit structure, and a second conductive through hole (col. 20/lns. 17-22: “backboard interconnects may be fabricated as multiple layers separated by dielectric layers and connected by vertical interconnects (not shown)…backboard 540 may comprise a printed circuit board (PCB) with the backboard substrate 550 comprising FR-4 material and backboard interconnects comprising copper”), the first build-up line structure and the second build-up line structure are respectively disposed at two opposite sides of the core layer, the second conductive through hole penetrates the core layer, and the second conductive through hole is electrically connected to the first build-up circuit structure and the second build-up circuit structure (col. 20/lns. 17-22: “backboard interconnects may be fabricated as multiple layers separated by dielectric layers and connected by vertical interconnects (not shown)…backboard 540 may comprise a printed circuit board (PCB) with the backboard substrate 550 comprising FR-4 material and backboard interconnects comprising copper”).
In regards to claim 7, the combination of Herner, Yeon, and Gomes teaches the limitations discussed above in addressing claim 1. Herner further teaches the limitations wherein the redistribution layer comprises at least one conductive layer, at least one second dielectric layer, and at least one conductive hole (col. 20/lns. 17-22: “backboard interconnects may be fabricated as multiple layers separated by dielectric layers and connected by vertical interconnects (not shown)…backboard 540 may comprise a printed circuit board (PCB) with the backboard substrate 550 comprising FR-4 material and backboard interconnects comprising copper”), the at least one conductive layer and the at least one second dielectric layer are sequentially stacked on the first dielectric layer, the at least one conductive hole penetrates the second dielectric layer, and the at least one conductive hole is electrically connected to the at least one conductive layer (col. 20/lns. 17-22: “backboard interconnects may be fabricated as multiple layers separated by dielectric layers and connected by vertical interconnects (not shown)…backboard 540 may comprise a printed circuit board (PCB) with the backboard substrate 550 comprising FR-4 material and backboard interconnects comprising copper”).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 6, and 7 have been considered but are moot because the new ground of rejection does not rely on the references as applied in the prior rejection of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812