Prosecution Insights
Last updated: April 19, 2026
Application No. 17/573,461

LOW VIA RESISTANCE INTERCONNECT STRUCTURE

Final Rejection §103
Filed
Jan 11, 2022
Examiner
PARKER, JOHN M
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
5 (Final)
92%
Grant Probability
Favorable
6-7
OA Rounds
2y 4m
To Grant
93%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
763 granted / 831 resolved
+23.8% vs TC avg
Minimal +1% lift
Without
With
+0.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
24 currently pending
Career history
855
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
43.5%
+3.5% vs TC avg
§102
37.3%
-2.7% vs TC avg
§112
14.1%
-25.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 831 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-5, 8-10, 24, 26 and 27is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeoh et al. (US Pat. Pub. 2021/0066475) in view of Chen et al. (US Pat. Pub. 2017/009589). Regarding claim 1, Yeoh teaches an interconnect structure of a semiconductor device, the interconnect structure comprising: a via structure, the via structure comprising a barrier layer on sidewalls and at bottom of the via structure [fig. 59a and c, via structure 4906, barrier 5916, fig. 59c does not label the barrier specifically, however, it is shown in fig. 59a]; a first metal layer [fig.59c, 5954]; a cap layer on the first metal layer [fig. 59c, 5956]; and a second metal layer between and in direct contact with the first metal layer and the barrier layer at the bottom of the via structure and the first metal layer, wherein the first metal layer and the second metal layer comprise different materials [fig. 59c, second metal 5914 between 5954 and 5916, paragraph [0604] teaches 5914 is ruthenium, paragraphs [0605 and 0606] teach conductive fill material is copper, 5954 is conductive fill material], wherein the barrier layer comprises Tantalum Nitride (TaN) [paragraph [0604]]. Yeoh fails to teach the TaN at the bottom of the via structure is thicker than the TaN on the sidewalls of the via structure. However, Chen teaches forming an interconnect structure in which a barrier layer comprising TaN and Co is formed to be thicker at the bottom of the via structure than the sidewalls [fig. 12, barrier layer considered to be both 904a and 902, the barrier is thicker at the bottom than on the sidewalls, paragraph [0047] teaches TaN for 902]. It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Chen into the method of Yeoh by forming the barrier layer to be thicker at the bottom of the via structure than on sidewalls, the barrier comprising TaN. The ordinary artisan would have been motivated to modify Yeoh in the manner set forth above for at least the purpose of utilizing processes that avoid back diffusion of metal into the cooper interconnect [Chen, paragraph [0030]]. Regarding claim 2, Yeoh in view of Chen teaches the interconnect structure of claim 1, wherein the barrier layer further comprises Cobalt (Co) [Chen, paragraph [0027] teaches Co for the metal 904a] Regarding claim 3, Yeoh in view of Chen teaches the interconnect structure of claim 1, wherein the first metal comprises copper (Cu) [Yeoh, paragraphs [0605 and 0606] teach conductive fill material is copper, 5954 is conductive fill material]. Regarding claim 4, Yeoh in view of Chen discloses the interconnect structure of claim 1, wherein the second metal layer comprises a metallic material having a coefficient of thermal expansion less than 7x10-6/K [Applicants own specification teaches Ru as having the correct coefficient of thermal expansion, paragraph [0604] teaches 5914 is ruthenium]. Regarding claim 5, Yeoh in view of Chen teaches the interconnect structure of claim 4, wherein the metallic material comprises at least one of W, Mo, Cr, and Ru [Yeoh, paragraph [0604] teaches 5914 is ruthenium]. Regarding claim 8, Yeoh in view of Chen discloses the interconnect structure of claim 7, wherein the cap layer comprises Co [Yeoh, paragraph [0608] teaches 5956 is cobalt]. Regarding claim 9, Yeoh in view of Chen teaches the interconnect structure of claim 7 further comprising an etch stop layer on the cap layer [Yeoh, fig. 59c, 5958] Regarding claim 10, Yeoh in view of Chen disclose the interconnect structure of claim 9, wherein a top surface of the second metal layer is coplanar with or below a top surface of the etch stop layer [Yeoh, fig. 59c, 5914 is coplanar with 5958]. Regarding claim 24, Yeoh in view of Chen teaches the interconnect structure of claim 1, wherein the second metal layer is disposed through the cap [Yeoh, fig. 59c, 5914 extends through 5956]. Regarding claim 26, Yeoh in view of Chen teaches the interconnect structure of claim 1, wherein the cap layer is in direct contact with the first metal layer [Yeoh, fig. 59c, 5954 is in direct contact with 5956]. Regarding claim 27, Yeoh in view of Chen discloses the interconnect structure of claim 1, wherein the cap layer is disposed below the barrier layer at the bottom of the via structure [Yeoh, fig. 59c, 5956 is below 5916 at the bottom of the via structure]. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeoh in view of Chen as applied to claims 1-5, 8-10, 24, 26 and 27 above, and further in view of the following arguments. Regarding claim 6, Yeoh in view of Chen teaches semiconductor devices formed at the 10 nanometer node or smaller [abstract], and a variety of layers in the 0.5-2 nanometer thickness range [paragraphs [0153, 0154, 0159]. They fail to specifically teach the thickness of the second metal layer is less than 5 nanometers. However, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization to achieve desired transistor performance. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(IV)(B). Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeoh in view of Chen as applied to claims 1-5, 8-10, 24, 26 and 27 above, and further in view of Kunimune et al. (US Pat. Pub. 2004/0130030). Regarding claim 11, while Yeoh in view of Chen teaches an etch stop layer they fail to specifically teach SiCN or AlN with ODC as the etch stop material. However, Kunimune teaches a semiconductor interconnect structure with multiple metal levels [fig. 6, 209. 233], a cap layer [fig. 6, 250] and an etch stop layer on the cap layer [fig. 6, 222] the etch stop layer being SiCN [paragraph [0086]]. It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Kunimune into the method of Yeoh in view of Chen by forming an etch stop layer out of SiCN. The ordinary artisan would have been motivated to modify Yeoh in view of Chen in the manner set forth above for at least the purpose of utilizing a layer which prevents diffusion of metals to elsewhere in the device [Kunimune, paragraph [0086]] while also functioning to protect layers below [Obvious advantage of an etch stop material]. Claim(s) 21-23, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeoh in view of Chen as applied to claims 1-5, 8-10, 24, 26 and 27 above, and further in view of Hsueh et al. (US Pat. Pub. 2021/0287994). Regarding claim 21, Yeoh in view of Chen fails to teach a third metal layer in direct contact with a top portion of the via structure. However, Hsueh teaches a metal structure with a cap thereon and a via structure on the cap, with a third metal layer in direct contact with a top portion of the via structure [fig. 6, metal structure 626, via structure 114/116 in layer 618b, third metal layer in direct contact 114/116 in layer 618c]. It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Hsueh into the method of Yeoh in view of Chen by having a third metal layer in direct contact with a top portion of the via structure. The ordinary artisan would have been motivated to modify Yeoh in view of Chen in the manner set forth above for at least the purpose of successfully contacting devices located in the substrate while decreasing RC delay [Hsueh, paragraphs [0050 and 0051]]. Regarding claim 22, while Hsueh shows a third metal layer they fail to specifically show a barrier extending to sidewalls and bottom of the third metal layer. However, additional embodiments of Hsueh show the second metal layer extending below the top surfaces of a barrier layer, the barrier layer extending to sidewalls and bottom of the second layer [fig. 4a, second layer 112, barrier 108]. It would be well known to one of ordinary skill in the art to utilize this embodiment in the structure shown in fig. 6, allowing the third metal layer to have the barrier layer extending to its sidewalls and bottom. It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of what is well known into the method of Hsueh by having the barrier extend to sidewalls and bottom of the third metal layer. The ordinary artisan would have been motivated to modify Hsueh in the manner set forth above for at least the purpose of having a reduced contact resistance and RC delay [paragraph [0051]]. Regarding claim 23, while Hsueh shows a third metal layer [fig. 6, 112 in layer 618b] they fail to specifically show a barrier extending to sidewalls and bottom of the third metal layer. However, additional embodiments of Hsueh show the second metal layer extending below the top surfaces of a barrier layer, the barrier layer extending to sidewalls and bottom of the second layer [fig. 4a, second layer 112, barrier 108]. It would be well known to one of ordinary skill in the art to utilize this embodiment in the structure shown in fig. 6, allowing the third metal layer to have the barrier layer extending to its sidewalls and bottom. It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of what is well known into the method of Hsueh by having the barrier extend to sidewalls and bottom of the third metal layer. The ordinary artisan would have been motivated to modify Hsueh in the manner set forth above for at least the purpose of having a reduced contact resistance and RC delay [paragraph [0051]]. Regarding claim 25, Yeoh in view of Chen fails to teach a portion of the second metal layer extends into the first metal layer. However, Hsueh teaches a first metal layer with a second metal layer thereon and a via structure above the first metal layer, the second metal layer extends into the first metal layer [fig. 4b, first metal layer 110, second metal layer 112, via structure 120, 112 extends into 110]. It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Hsueh into the method of Yeoh in view of Chen by having a the second metal layer extend into the first metal layer. The ordinary artisan would have been motivated to modify Yeoh in view of Chen in the manner set forth above for at least the purpose of decreasing RC delay in interconnect structures [Hsueh, paragraphs [0015 and 0016]]. Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot in view of the new grounds of rejection applied above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOHN M PARKER/Examiner, Art Unit 2899
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Prosecution Timeline

Jan 11, 2022
Application Filed
Oct 26, 2024
Non-Final Rejection — §103
Jan 30, 2025
Response Filed
May 02, 2025
Final Rejection — §103
Jul 08, 2025
Response after Non-Final Action
Aug 07, 2025
Request for Continued Examination
Aug 08, 2025
Response after Non-Final Action
Aug 09, 2025
Non-Final Rejection — §103
Nov 13, 2025
Response Filed
Nov 29, 2025
Non-Final Rejection — §103
Mar 03, 2026
Response Filed
Mar 14, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

6-7
Expected OA Rounds
92%
Grant Probability
93%
With Interview (+0.9%)
2y 4m
Median Time to Grant
High
PTA Risk
Based on 831 resolved cases by this examiner. Grant probability derived from career allow rate.

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