DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on March 5, 2026. Claims 1-2 have been amended. No new claims have been added or canceled. Currently, claims 1-3 are pending.
Applicant’s amendments to claim 1 and 2 successfully overcomes the 112(b) rejection of claims 1 and 2 and dependent claims set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments filed March 5, 2026, with respect to claim 1 have been fully considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2018/0069127) in view of Matsukizono et al. (US 8975637), Kim (US 20160211285), and Young (US 20050176226).
Regarding claim 1, Yang teaches a method of fabricating a thin-film transistor (TFT) photodetector, the method comprising:
forming a diffusion layer ([0017]) on a glass substrate or a transparent flexible substrate (see Fig. 1; [0017]; glass substrate 110), wherein the diffusion layer includes a P-type diffusion layer of P-type polycrystalline or amorphous silicon ([0017], P-type amorphous silicon), for use as an active layer ([0017]) (see Fig. 5);
forming an insulating oxide layer (GI and 140) (see Figs. 3-4; [0019]) on the formed diffusion layer;
forming a gate material layer on the insulating oxide layer ([0019]);
forming a gate (G) to be used as the light receiving part by photo-patterning the gate material layer (see Fig. 3; [0018]-[0019]);
removing a remaining area of the P-type diffusion layer (130) except for areas to be used as a source and a drain by etching (see Fig. 2; [0018]); and
generating electrodes (S and D) by depositing a metal [0020] in etched parts (140H) of the insulating oxide layer in the source and the drain (see Fig. 5).
Yang does not explicitly teach that the insulating oxide layer is configured to control tunneling of optically excited charges between the active layer and a light receiving part; forming a plurality of diffusion layers, that the diffusion layers include P+-type diffusion layers of amorphous or polycrystalline silicon at both sides of the P-type diffusion layer, that the gate material layer is an N-type diffusion layer of polycrystalline or amorphous silicon; that the light receiving part and the active layer are formed of amorphous silicon or polycrystalline silicon, thereby forming a wavelength extension layer having a plurality of localized energy levels between a conduction band and a valence band; etching the insulating oxide layer except for only a necessary part in a photoresist (PR) patterning process, and that when light is incident on the light receiving part, electrons migrate by tunneling through the insulating oxide layer between the light receiving part and the active layer which have been excited with the insulating oxide layer in between, the amount of charge in the light receiving part is changed by the migration of the electrons, causing a threshold voltage modulation effect equivalent to application of a negative power source to the light receiving part to induce photocurrent flow, and enabling detection of light having a longer wavelength than a maximum detectable wavelength of single crystalline silicon by exploiting the plurality of localized energy levels naturally formed in the light receiving part and the active layer.
In a similar field of endeavor, Matsukizono teaches forming diffusion layers (233 and 234; Fig. 3; col. 8, lines 5-20), that the diffusion layers include P+-type diffusion layers of amorphous or polycrystalline silicon (234; Fig. 3; col. 8, lines 5-20) at both sides of the P-type diffusion layer (233), and etching the generated insulating oxide layer (122) except for only a necessary part (241 and 242) in a photoresist (PR) patterning process (see Figs. 7a-7b), in order to have “an advantage of being able to curtail the production process and the production cost” (col. 11, lines 20-30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yang with the diffusion layers and oxide layer formation methods of Matsukizono, in order to reduce the production cost.
Yang, as modified by Matsukizono, does not explicitly teach that the insulating oxide layer is configured to control tunneling of optically excited charges between the active layer and a light receiving part;
that the gate material layer is an N-type diffusion layer of polycrystalline or amorphous silicon;
that the light receiving part and the active layer are formed of amorphous silicon or polycrystalline silicon, thereby forming a wavelength extension layer having a plurality of localized energy levels between a conduction band and a valence band; and
that when light is incident on the light receiving part, electrons migrate by tunneling through the insulating oxide layer between the light receiving part and the active layer which have been excited with the insulating oxide layer in between, the amount of charge in the light receiving part is changed by the migration of the electrons, causing a threshold voltage modulation effect equivalent to application of a negative power source to the light receiving part to induce photocurrent flow.
In a similar field of endeavor, Kim teaches, in Fig. 2, that the insulating oxide layer (140, [0038]) is configured to control tunneling of optically excited charges between the active layer (160, [0041]) and a light receiving part (150, [0037]) ([0038]);
that the gate material layer (150) is an N-type diffusion layer of polycrystalline or amorphous silicon ([0037], polycrystalline silicon);
that the light receiving part (150) and the active layer (160) are formed of silicon ([0035], [0037], [0048], 150 is formed of polycrystalline silicon, while active layer 160 is formed of silicon), thereby forming a wavelength extension layer having a plurality of localized energy levels between a conduction band and a valence band ([0042]-[0043]); and
that when light is incident on the light receiving part (150), electrons migrate by tunneling through the insulating oxide layer (140) between the light receiving part (150) and the active layer (160) which have been excited with the insulating oxide layer (140) in between, the amount of charge in the light receiving part (150) is changed by the migration of the electrons, causing a threshold voltage modulation effect equivalent to application of a negative power source to the light receiving part (150) to induce photocurrent flow ([0041], lowering the threshold voltage is equivalent to when a negative power source is applied to the gate of a PMOS),
in order to fabricate a photodetector that “shows not only a very high sensitivity to detect even a single photon but also performance to drive a very large current flow by means of a slight amount of light” ([0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Yang in view of Matsukizono with the tunneling structure, light receiving part, active layer, and threshold voltage modulation of Kim, in order to fabricate a photodetector that shows not only a very high sensitivity to detect even a single photon but also performance to drive a very large current flow by means of a slight amount of light” ([0043]).
Yang in view of Matsukizono and Kim does not explicitly teach that both the light receiving part and the active layer are formed of amorphous silicon or polycrystalline silicon, and that detection of light having a longer wavelength than a maximum detectable wavelength of single crystalline silicon is enabled by exploiting the plurality of localized energy levels naturally formed in the light receiving part and the active layer.
In a similar field of endeavor, Young teaches that the light receiving part (26) and the active layer (28) are formed of amorphous silicon or polycrystalline silicon ([0040], 26 is amorphous silicon and active layer 28 is polycrystalline silicon), and that detection of light having a longer wavelength than a maximum detectable wavelength of single crystalline silicon is enabled by exploiting the plurality of localized energy levels naturally formed in the light receiving part and the active layer (this feature is inherent in the Poly-Si channel/a-Si gate architecture that modifies the device of Yang in view of Matsukizono and Kim), in order to have “an improved bottom-gate TFT having a low threshold voltage” ([0015]) that can be applied to “other kinds of active matrix array devices such as sensor array devices” ([0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Yang in view of Matsukizono and Kim with the light receiving part and active layer materials of Young, in order to have an improved TFT having a low threshold voltage that can be applied to sensor array devices ([0015], [0053]).
Regarding claim 3, Yang, as modified by Matsukizono, Kim, and Young, teaches the limitations of claim 1. Young further teaches, in Fig. 5, that the N-type diffusion layer (26 and 26’, [0046]) is formed by depositing amorphous silicon (26, [0046]) and then crystallizing the deposited amorphous silicon by thermal treatment ([0046], to form 26’).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2018/0069127) in view of Matsukizono et al. (US 8975637), Kim (US 20160211285), and Young (US 20050176226), and further in view of Bouthinon (US 20210233975).
Regarding claim 2, Yang, as modified by Matsukizono, Kim, and Young teaches the limitations of claim 1. Yang, as modified by Matsukizono, Kim, and Young does not explicitly teach wherein the insulating oxide layer is formed by sputtering or plasma enhanced chemical vapor deposition (PECVD).
In a similar field of endeavor, Bouthinon teaches wherein the insulating oxide layer (52) is formed by sputtering or plasma enhanced chemical vapor deposition (PECVD) ([0132], sputtering), in order to “improve the production of such a device integrating an image sensor and a display screen” ([0006]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yang, as modified by Matsukizono, Kim, and Young, with the insulating oxide layer being formed by sputtering of Bouthinon, in order to improve the production of a device integrating an image sensor and a display screen.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is (703)756-4644. The examiner can normally be reached Monday - Friday 11:30-8:30 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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