Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Amendment and Request for Reconsideration filed December 2, 2025. Claim 1 has been amended. Claims 1-22 are pending, with claims 11-22 currently withdrawn from consideration.
Response to Amendment
The amendments to the claims filed December 2, 2025 have been entered. Applicant’s amendments to the claims have failed to overcome each and every rejection set forth in the previous Office Action filed September 2, 2025.
Response to Arguments
Applicant's arguments filed December 2, 2025 have been fully considered but they are not persuasive.
Applicant argues on pages 9-10 that the cited prior art references fail to teach that bottom surfaces of the gate plugs are higher than top surfaces of the gate structures in the gate spaced regions and not in contact with the gate structures in the gate spaced regions, as recited in amended claim 1.
This argument is not persuasive because, as explained in the previous Office Action and again in the rejections of the claims below, Examiner’s interpretation of Cheng2123 differs from the interpretation presented by Applicant. Specifically, Applicant states on page 10 that the Examiner contemplated the CB contacts 50 in Cheng2123 as the gate plugs in claim 1, the sacrificial spacers 34 in Cheng2123 as the gate structures in the gate spaced regions in claim 1. This is incorrect. In the previous Office Action, and again in the rejections of the claims below, the “gate spaced region” is not mapped to the sacrificial spacers 34, but is mapped to the region above sacrificial spacers 34, shown in FIG. 13 of Cheng2123. The gate contact region is shown in FIG. 13 of Cheng2123 as the region including the interface between the materials of HKMG 22 [the gate structure] and CB contact 50 [the gate plug]. Note the shape of CB contact 50 [the gate plug], shown having a stepped bottom surface, a portion of which is level with the top surface of HKMG 22 in the center [in the gate contact region], and a lower portion of the bottom surface of CB contact 5o [the gate plug] is shown level with the top of sacrificial spacers 34 around the periphery [in the gate spaced region]. Accordingly, in the region above sacrificial spacers 34 [in the gate spaced region], the bottom surfaces of CB contact 50 [the gate plug] are higher than, and not in contact with HKMG 22 [the gate structure]. See annotated FIG. 13 of Cheng2123:
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In response to Applicant’s argument on page 10 that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from the independent claim 1, as amended, see the rejections of the claims below.
Claim Objections
Applicant has amended claim 1. Therefore, the objection to claim 1 set forth in the Office Action filed September 2, 2025 is withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
In the Office Action filed September 2, 2025, claim 1 and claims 2-10 dependent therefrom were rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Applicant has amended claim 1, therefore the 35 U.S.C. 112(b) rejections of claims 1-10 have been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al., US 2019/0378909 A1 (hereinafter Cheng) and further in view of Cheng, US 2019/0312123 A1 (hereinafter Cheng2123).
Regarding claim 1, as amended, Cheng teaches: a semiconductor structure, comprising: a base (Cheng, FIG. 18, fin 10); a plurality of gate structures arranged discretely on the base (Cheng, FIG. 18, functional gate structures 26, [0067]), wherein the gate structures comprise gate contact regions (Cheng, FIG. 18, region of functional gate structures 26 below contact caps 28, [0048]) configured to contact with gate plugs (Cheng, FIG. 18, upper surface of functional gate structures 26 [the gate structures] shown in contact with contact caps 28 [the gate plugs] in the gate contact regions) and gate spaced regions (Cheng, FIG. 18, elements other than contact caps 28, including dielectric 66 and regions horizontally adjacent to contact caps 28, [0082]); source/drain doped regions (Cheng, FIG. 18, source / drain regions 12, 14, [0040]), located in the base on two sides of the gate structures (Cheng, see FIG. 18), wherein the source/drain doped regions comprise source/drain contact regions (Cheng, FIG. 18, upper surfaces of source / drain regions 12, 14) configured to contact with source/drain plugs (Cheng, FIG. 18 shows upper surfaces of source / drain regions 12, 14 in contact with metal fill 58, i.e., source/drain plugs, [0075]), (Cheng, FIG. 18, dielectric liner 62 and dielectric 66, [0079-0080]), located on the base on sides of the gate structures and covering the source/drain doped regions (Cheng, see FIG. 18, dielectric liner 62 and dielectric 66, i.e., dielectric structure layers, shown on upper surfaces of source / drain regions 12, 14, i.e., covering the source/drain doped regions), wherein the dielectric structure layers further cover tops of the gate structures (Cheng, see FIG. 18); source/drain contact structures, in contact with the source/drain doped regions (Cheng, FIG. 18, metal fill 58, [0075]), wherein the source/drain contact structures are an integrated structure (for purposes of examination, absent additional structural limitations, “an integrated structure” is broad enough to encompass any grouping of claimed structural elements), and comprise source/drain plugs penetrating dielectric structure layers of the source/drain contact regions (Cheng, FIG. 18 shows metal fill 58, i.e., source/drain plugs, penetrating the region of dielectric liner 62 at the upper surfaces of source / drain regions 12, 14, i.e., the source/drain contact regions) .
Cheng does not explicitly teach: where remaining regions of the source/drain doped regions are configured for use as source/drain connection regions … source/drain contact layers located in dielectric structures of the source/drain connection regions, top surfaces of the source/drain contact layers are lower than top surfaces of the source/drain plugs, and the source/drain contact structures and the dielectric structure layers enclose spaced openings; spaced dielectric layers, filling the spaced openings; and gate plugs, located on tops of the gate structures in the gate contact regions and in contact with the gate structures in the gate contact regions, bottom surfaces of the gate plugs are leveled with top surfaces of the gate structures in the gate contact regions, higher than top surfaces of the gate structures in the gate spaced regions, and not in contact with the gate structures in the gate spaced regions.
However, Cheng2123, in the same field of endeavor, teaches: where remaining regions of the source/drain doped regions (Cheng2123, FIGs. 13-16 show remaining regions of the source/drain doped regions as the regions of second dielectric 40 not covered by CA contacts 52, [0069]) are configured for use as source/drain connection regions (Cheng2123, see [0069]). Cheng2123 also teaches: source/drain contact layers (Cheng2123, FIGs. 13-16, TS contacts 38) located in dielectric structures of the source/drain connection regions (Cheng2123, FIGs. 13-16, sacrificial spacers 34, [0109]), top surfaces of the source/drain contact layers are lower than top surfaces of the source/drain plugs (Cheng2123, FIG. 15 shows top surfaces of CA contacts 52, i.e., top surfaces of the source/drain plugs, higher than top surfaces of TS contacts 38, i.e., the source/drain contact layers), and the source/drain contact structures and the dielectric structure layers enclose spaced openings (Cheng2123, FIGs. 9-10, openings 44, [0068]); spaced dielectric layers, filling the spaced openings (Cheng2123, FIGs. 13-16, second dielectric 40, [0065-0066]); and gate plugs (Cheng2123, FIGs. 13-18, CB contacts 50, [0069]; analogous to the gate contact caps 28 of Cheng), located on tops of the gate structures in the gate contact regions and in contact with the gate structures in the gate contact regions (Cheng2123, FIGs. 13-18, CB contacts 50 [the gate plugs] shown on tops of and in contact with HKMG 22 [the gate structures] in the region where bottom surface of CB contacts 50 contact top surfaces of HKMG 22 [the gate contact region]), bottom surfaces of the gate plugs are leveled with top surfaces of the gate structures in the gate contact regions (Cheng2123, FIGs. 13 and 18, bottom surface of CB contacts 50 [the gate plugs] shown leveled with top surfaces of HKMG 22 [the gate structures], [0069; 0077]), higher than top surfaces of the gate structures in the gate spaced regions (Cheng2123, FIGs. 13 and 18, in the region above sacrificial spacers 34 [in the gate spaced regions], analogous to the dielectric 66 and regions adjacent to contact caps 28 of Cheng, bottom surface of CB contacts 50 [the gate plugs] are shown higher than top surfaces of HKMG 22 [the gate structures], [0069; 0077]), and not in contact with the gate structures in the gate spaced regions (Cheng2123, FIGs. 13 and 18, bottom surface of CB contacts 50 [the gate plugs] in the regions directly above sacrificial spacers 34 [in the gate spaced regions] are shown not in contact with HKMG 22 [the gate structures], [0069; 0077]).
A person having ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the structures taught by Cheng and Cheng2123 are analogous, with the structure taught by Cheng2123 teaching additional details. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng with the teachings of Cheng2123 to arrive at Applicant’s claimed invention with a high likelihood of success and without undue experimentation. The motivation for combining these known elements would be, as expressly recognized by Cheng2123, to improve device performance by improving capacitance reduction and increasing transistor density by placing the gate contact directly on top of the active area.
Regarding claim 2, Cheng in view of Cheng2123 teaches: the semiconductor structure according to claim 1, wherein the dielectric structure layers comprise: bottom dielectric layers (Cheng, see FIG. 18, dielectric liner 62), located on the base on the sides of the gate structures and covering the source/drain doped regions (Cheng, see FIG. 18, dielectric liner 62, i.e., dielectric structure layers, shown on fin 10, i.e., on the base, on sides of functional gate structures 26, i.e., on the sides of the gate structure, and covering a portion of upper surfaces of source / drain regions 12, 14, i.e., covering the source/drain doped regions); and top dielectric layers (Cheng, FIG. 18, dielectric 66), located on the bottom dielectric layers (Cheng, see FIG. 18).
Regarding claim 3, Cheng in view of Cheng2123 teaches: the semiconductor structure according to claim 2, wherein the top surfaces of the source/drain contact layers (Cheng, FIG. 18, upper surfaces of source / drain regions 12, 14) are lower than top surfaces of the bottom dielectric layers (Cheng, see FIG. 18, dielectric liner 62 is shown above the upper surfaces of source / drain regions 12, 14).
Regarding claim 4, Cheng teaches: the semiconductor structure according to claim 1, wherein the semiconductor structure further comprises: gate cap layers (Cheng, FIG. 18, contact caps 28, [0048]), located between tops of the gate structures (Cheng, FIG. 18, functional gate structures 26, [0067]) in the gate spaced regions and the dielectric structure layers (Cheng, FIG. 18, contact caps 28, i.e., gate cap layers, shown between tops of functional gate structures 26 and dielectric liner 62 and dielectric 66, i.e., the dielectric structure layers, [0079-0080]);
Cheng is silent regarding: top surfaces of the gate structures in the gate contact regions are higher than top surfaces of the gate structures in the gate spaced regions. However, Cheng2123 teaches: top surfaces of the gate structures in the gate contact regions (Cheng2123, FIGs. 13 and 14, top surface of CB contacts 50, [0069]) are higher than top surfaces of the gate structures in the gate spaced regions (Cheng2123, FIGs. 13 and 14, top surface of HKMG 22, [0077]).
Regarding claim 5, Cheng in view of Cheng2123 teaches: the semiconductor structure according to claim 4, wherein the top surfaces of the source/drain contact layers (Cheng, FIG. 18, upper surfaces of source / drain regions 12, 14) are lower than the top surfaces of the gate structures in the gate spaced regions (Cheng, FIG. 18, top surface of functional gate structures 26, [0067]).
Regarding claim 6, Cheng in view of Cheng2123 teaches: the semiconductor structure according to claim 4, wherein: the semiconductor structure further comprises: etch stop structures (Cheng2123, FIG. 11, sacrificial spacers 34 remain substantially intact due to high etch selectivity, [0073]), located on the tops of the gate structures in the gate contact regions (Cheng2123, FIG. 11 shows sacrificial spacers 34 arranged vertically along the upper portion of HKMG 22 and dielectric 36, i.e., on the tops of the gate structures in the gate contact regions); (Cheng2123, FIG. 13 shows gate plugs 50 extending downward through an opening in sacrificial spacers 34, i.e., penetrating the etch stop structures, [0077]).
Cheng and Cheng2123 are silent regarding: the dielectric structure layers cover sidewalls of the etch stop structures. However, Cheng2123 teaches a dielectric 62 that surrounds and covers metal fill 52 as well as the first and second dielectrics 36, 40, to reduce parasitic capacitance between the metal gates and the TS contacts (Chen2123, FIG. 23, [0039, 0097]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Cheng in view of Cheng2123 insofar as the dielectric structure layers cover sidewalls of the etch stop structures, because such technique was known in the art and would have yielded predictable results with a high likelihood of success and without undue experimentation.
Regarding claim 7, Cheng in view of Cheng2123 teaches nearly every element of claim 7 but is silent regarding: wherein a material of the etch stop structures comprises at least one of AIN, A1203, SiCN, SiON, SiOC, AION, Si, Ge, C, or SiO2.
However, Cheng2123 teaches that silicon dioxide (SiO2) can be used as an etch stop layer (see [0043]), so the use of SiO2 as a material for an etch stop structure would have been known to a person having ordinary skill in the art. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Cheng with the teachings of Cheng2123, insofar as selecting SiO2 as a material of the etch stop structures, because doing so would yield predictable results with a high likelihood of success and without undue experimentation.
Regarding claim 8, Cheng in view of Cheng2123 teaches: the semiconductor structure according to claim 6, wherein thicknesses of the etch stop structures (Cheng2123, FIG. 11, due to the manufacturing process, thickness of sacrificial spacers 34 is the same as the thickness of spacers 16, within the range of about 2-10 nm, [0048]) are 50% to 150% of thicknesses of the gate cap layers (Cheng, FIGs. 2-3, due to the manufacturing process, contact caps 28 are the same thickness as sacrificial gate cap layer 18, a thickness from about 10 nm to about 200 nm, [0037], this is within Applicant’s claimed range). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Cheng2123 to the teachings of Cheng, insofar as selecting a thickness of the etch stop structures are 50% to 150% of thicknesses of the gate cap layers, because, as expressly recognized by Cheng2123, the technique was known in the art, and doing so enables gate contact over active with improved process margins and increases transistor density on a chip because the gate contact is placed directly on top of the active area.
Regarding claim 9, Cheng in view of Cheng2123 teaches: the semiconductor structure according to claim 1, wherein: the gate structures (Cheng2123, FIGS. 13-14, HKMG 22 and dielectric 36, [0067]) and the source/drain contact structures (Cheng2123, FIGs. 15-16, TS contacts 38 and second dielectric 36) extend both in a longitudinal direction (Cheng2123, FIGs. 14 and 16 show longitudinal direction as up and down), and a direction perpendicular to the longitudinal direction is a transverse direction (Cheng2123, FIGs. 14 and 16 show the transverse direction as left and right); and the semiconductor structure further comprises: interconnect dielectric layers (Cheng2123, ILD 42, FIGs. 12-16, [0068]), located on the dielectric structure layers and covering the spaced dielectric layers and the top surfaces of the source/drain plugs (Cheng2123, see FIGs. 12-16); and metal interconnect lines (Chen2123, local interconnect lines formed in ohmic contact with device-level plugs, [0069]), penetrating the interconnect dielectric layers (Cheng2123, see FIGs. 12-16), wherein the metal interconnect lines extend in the transverse direction (Cheng2123, FIGs. 14 and 16 show the transverse direction as left and right) and are spaced in the longitudinal direction (Cheng2123, FIGs. 14 and 16 show longitudinal direction as up and down; local interconnect lines are not shown but from the structure shown it would be clear to a person having ordinary skill in the art that in order for local interconnect lines to function as described they extend from left to right, i.e., in the transverse direction, and be spaced apart in the longitudinal direction), and the metal interconnect lines are correspondingly in contact with the gate plugs (Chen2123, FIGs. 13-16, CB contacts, [0069]) and the source/drain plugs (Chen2123, FIGs. 13-16, TS contacts, [0069]) respectively.
Regarding claim 10, Cheng in view of Cheng2123 teaches: the semiconductor structure according to claim 9, wherein the metal interconnect lines and the gate plugs are an integrated structure (Cheng2123, FIGs. 11-14 show CB contacts 50, i.e., the metal interconnect lines, formed as an integrated structure including the gate plug within opening 48, [0069]). For purposes of examination, absent additional structural limitations, “an integrated structure” is broad enough to encompass any group of claimed structural elements.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. The cited prior art discloses similar materials, devices, and methods.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899