DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/03/2025 has been entered.
Response to Amendment
The response filed 12/03/2025 is accepted, in which, claims 1 and 9 are amended. Claims 1, 3-18, and 20-21 await an action on the merits as follows.
The rejection of claim 9 under USC 112b is withdrawn in view of the amended claim.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-18, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Pak (US 2022/0173160 A1), in view of Im (US 2019/0326348 A1), in view of Kim (US 2020/0066699 A1), and further in view of Chai (US 20200258938 A1).
Regarding claim 1, Pak teaches a display device (display device, not shown, [0006]) comprising:
a substrate (101, Fig 1);
a transistor (100) on and over (shown on and over) the substrate (101) and disposed (shown in) in a pixel (Fig 1; Fig 1 is a subpixel, [0053]);
a connection electrode (top of DH/LH) electrically connected (shown connected) to the transistor (100);
first electrodes (142/144) electrically separated (shown separated) from the connection electrode (top of DH/LH)
light emitting elements (130) disposed between (shown between) the first electrodes (142/144); and
second electrodes (150/160) disposed on (shown on) the first electrodes (142/144) and the light emitting elements (130),
wherein at least one of the second electrodes (150/160) electrically connect (shown electrically connecting) the connection electrode (top of DH/LH) and one of the light emitting elements (130) to each other.
Pak fails to explicitly teach first electrodes electrically separated from the connection electrode and disposed on and over the transistor, and a bridge electrode on the transistor and electrically separated from the first electrodes, wherein the first electrodes are electrically separated from the light emitting elements, wherein the connection electrode is electrically connected to the transistor through the bridge electrode, and wherein the light emitting elements do not overlap the bridge electrode in a plan view.
However, Im teaches first electrodes electrically separated from the connection electrode and disposed on and over (alignment electrodes 341 shown on and over the transistor 321, Fig 11) the transistor, and
the first electrodes are electrically separated (shown electrically separated) from the light emitting elements.
Kim teaches a bridge electrode (CNE, Fig 5) on (shown on) the transistor.
When combined with Pak and Im, Kim’s bridge electrode (CNE) would be between the connection electrode and the drain of the transistor. Therefore, the combination discloses a bridge electrode on the transistor and electrically separated from the first electrodes and the connection electrode is electrically connected to the transistor through the bridge electrode.
Chai teaches wherein the light emitting elements do not overlap (bridge electrode ETP shown not overlapping in plan view, Fig 5) the bridge electrode in a plan view.
Pak, Im, Kim, and Chai are considered analogous to the claimed invention because all are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Pak with the features of Im, Kim, and Chai to create first electrodes electrically separated from the connection electrode and disposed on and over the transistor, and a bridge electrode on the transistor and electrically separated from the first electrodes, wherein the first electrodes are electrically separated from the light emitting elements, wherein the connection electrode is electrically connected to the transistor through the bridge electrode, and wherein the light emitting elements do not overlap the bridge electrode in a plan view which provides a display device is capable of improving the degree of alignment of light emitting elements (Im, [0007]) and provide a display device with improved reliability and manufacturing yield (Kim, [0005]) having excellent performance in terms of lifespan and luminance (Chai, [0003]) and manufactured by a relatively simple process that omits a separation process of lines for aligning a light emitting device and improves reliability by reducing or minimizing a defect that may occur during the separation process (Chai, [0005]).
Regarding claim 3, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 1. Pak goes on to teach the connection electrode (Top of DH/LH, Fig 1) is disposed between (shown between) the transistor (100) and the at least one of the second electrodes (150/160) in a cross sectional view (Fig 1).
Regarding claim 4, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 3. Pak goes on to teach the second electrodes (150/160) are electrically separated (shown separated) from the first electrodes (142/144), and
at least one pair (one pair shown, Fig 1) of the second electrodes (150/160) and the first electrodes (142/144) overlap (shown overlapping) each other and receive different signals (different signals; 142/144 receive alignment signals, [0077]; 150/160 receive driving signals, [0132]).
Regarding claim 5, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 4. Pak goes on to teach an insulating layer (116, Fig 1) disposed on (shown on) the first electrodes (142/144),
wherein the at least one (150) of the second electrodes (150/160) is electrically connected (shown electrically connected) to the connection electrode (top of DH/LH) through a contact hole (122a) passing through the insulating layer (116).
Regarding claim 6, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 5. Pak goes on to teach the at least one of the second electrodes (150, Fig 1) is electrically connected (shown electrically connected) to the transistor (100) through the connection electrode (top of DH/LH).
Regarding claim 7, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 6. Pak goes on to teach the at least one of the second electrodes (150, Fig 1) is in electrical contact (shown electrically connecting) with the connection electrode (top of DH/LH).
Regarding claim 8, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 7. Pak goes on to teach the connection electrode (top of DH/LH; comprised of same material as drain electrode 108, Mo, [0068]) and the at least one of the second electrodes (150; comprised of Mo, [0071]) are formed of a same material (Mo).
Regarding claim 9, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 8. Pak goes on to teach the connection electrode (top of DH/LH, Fig 1) does not overlap (shown not overlapping) the first electrodes (142/144) in a plan view.
Regarding claim 10, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 9. Pak goes on to teach an emission area (200, Fig 1);
a first non-emission area (area from 122a to 200 on left of Fig 1, and area from 200 to 122b on right of Fig 1) surrounding (shown surrounding) the emission area (200); and
a second non-emission area (from 122a to left side of Fig 1) adjacent (shown adjacent) to the first non-emission area (area from 122a to 200 on left of Fig 1, and area from 200 to 122b on right of Fig 1) and spaced apart (shown spaced apart) from the emission area (200).
Regarding claim 11, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 10. Pak goes on to teach a bank (118, Fig 1) disposed in (shown in) the first non-emission area (area from 122a to 200 on left of Fig 1, and area from 200 to 122b on right of Fig 1).
Regarding claim 12, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 11. Pak teaches the second non-emission area (from 122a to left side of Fig 1), and goes on to teach the bank (118, Fig 1) includes:
a first opening (opening for 200) overlapping the emission area (200).
Kim goes on to teach a second opening (opening trench on left side of Fig 5 above via in E1) overlapping (shown overlapping non-emission area under BM of Fig 5) the second non-emission area.
Regarding claim 13, the combination of Pak, Im, Kim, and Chai disclose the display device of claim 12. Pak goes on to teach the connection electrode (top of DH/LH, Fig 1) is disposed in (shown in) at least one of the first non-emission area (area from 122a to 200 on left of Fig 1, and area from 200 to 122b on right of Fig 1) or the second non-emission area (from 122a to left side of Fig 1).
Regarding claim 14, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 13. Pak goes on to teach the connection electrode (top of DH/LH, Fig 1) at least partially overlaps (shown overlapping) the bank (118).
Regarding claim 15, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 14. Pak goes on to teach the connection electrode (top of DH/LH, Fig 1) is electrically connected (shown electrically connected) to the transistor (100) through a first contact hole (DH) disposed in (shown in) the first non-emission area (area from 122a to 200 on left of Fig 1, and area from 200 to 122b on right of Fig 1).
Regarding claim 16, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 15. Pak teaches the second electrode (150, Fig 1), the connection electrode (top of DH/LH), and the second non-emission area (from 122a to left side of Fig 1).
Kim goes on to teach the second electrode is electrically connected (second electrode CNE1 is electrically connected to RFE1 through contact hole CPE1) to the connection electrode through a second contact hole (CPE1) disposed in (shown in) the second non-emission area.
Therefore, the combination discloses the second electrode is electrically connected to the connection electrode through a second contact hole disposed in the second non-emission area.
Regarding claim 17, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 16. Pak goes on to teach the at least one of the second electrodes (150, Fig 1) extends (shown extending past 122a into second non-emission area) from the emission area (200) to the second non-emission area (from 122a to left side of Fig 1) through the first non-emission area (area from 122a to 200 on left of Fig 1, and area from 200 to 122b on right of Fig 1).
Regarding claim 18, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 17. Pak goes on to teach the transistor (100, Fig 1) includes at least one of a source electrode (106) or a drain electrode (108), and the connection electrode (top of DH/LH) is electrically connected (shown connected through DH to 108) to the source electrode (106) or the drain electrode (108).
Regarding claim 20, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 1. Pak teaches the connection electrode (top of DH/LH, Fig 1).
Kim goes on to teach an insulating layer (L4, Fig 5) disposed on (shown on) the bridge electrode (CNE), wherein the connection electrode is in electrical contact (shown electrically connecting) with the bridge electrode (CNE) through a contact hole passing through the insulating layer (contact hole through L4 shown in Fig 5).
Therefore, the combination discloses an insulating layer disposed on the bridge electrode, wherein the connection electrode is in electrical contact with the bridge electrode through a contact hole passing through the insulating layer.
Regarding claim 21, the combination of Pak, Im, Kim, and Chai discloses the display device of claim 1. Pak teaches the transistor (100, Fig 1) and the first electrodes (142/144).
Im goes on to teach a protection layer (305, Fig 4) on and over (shown on and over) the transistor, the protection layer (305) also disposed below (shown below) the first electrodes.
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tsao (US 2022/0050334 A1) - Pixel structure with alignment electrodes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897