Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to Amendments filed 2/26/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 2 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the second region of the gate insulating layer" in the penultimate line. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 depends from claim 1 and is, therefore, also rejected.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takebuchi et al. (US 2011/0175173 A1; hereinafter Takebuchi) in view of Yamazaki et al. (US 2013/0320334 A1; hereinafter Yamazaki).
Regarding claim 1, Takebuchi discloses a method of manufacturing a semiconductor device (¶ 0002 of Takebuchi) comprising:
forming a semiconductor layer (“a semiconductor layer 10” in Fig. 3A; ¶ 0036);
forming a gate insulating layer (“gate oxide film 12” in Fig. 3A; ¶ 0037) including a silicon oxide film (“The material of the gate oxide film 12 is e.g. silicon oxide”, ¶ 0037) in contact1 with the semiconductor layer and covering the semiconductor layer (“a gate oxide film 12 is formed above the semiconductor layer 10”, ¶ 0037);
forming a gate electrode (“gate electrode 21” in Fig. 3A; ¶ 0038) on the gate insulating layer so as to overlap the semiconductor layer (“a columnar gate electrode 21 is selectively formed above the gate oxide film 12 in the region 20”, ¶ 0038; “the surface of the semiconductor layer 10 where the gate electrode 21 [is] formed”, ¶ 0039); and
injecting boron through the gate electrode and the gate insulating layer after forming the gate electrode (“by ion implantation, as a second impurity, a group III element such as boron (B) is implanted through the gate electrode 21 and the sidewall protective film 23 into the well region 24”2, ¶ 0042), and terminating with boron instead of hydrogen (“boron (B)”, ¶ 0042) wherein
a boron concentration included in a region of the gate insulating layer overlapping the gate electrode is in a range of 1E + 16 [atoms/cm3] or more (Fig. 9A of Takebuchi shows the impurity concentration in the depth direction immediately below the gate electrode (¶ 0069). The interface between the gate insulating layer and the gate electrode3 is at a depth of 0 below the gate electrode which, as shown in Fig. 9A, corresponds to a concentration within Applicant’s claimed range4),
an applied voltage at injecting the boron is 10 keV or more (¶ 0042). Since the range 10 keV or more overlaps the claimed range of 30 keV or more and 40 keV or less, a prima facie case of obviousness exists (MPEP § 2144.05(I)),5 and
the boron concentration in a region of the gate insulating layer adjacent to the gate electrode (region not under resist 40 in Fig. 4A) is more than ten times higher than the boron concentration in a region of the gate insulating layer adjacent to the semiconductor layer (region under resist 40; because the region under resist 40 receives no boron from the implant by virtue of being covered during the implantation process).
With regards to the boron repairing defects in the aforementioned overlapping region, Takebuchi does not explicitly disclose that such a repair occurs. However, Applicant has submitted that boron injection repairs defects in silicon oxide films (Page 16, Lines 8-13 of the Specification as originally filed). As such, the preponderance of evidence of the record indicates that the method of Takebuchi will also repair defects in an overlapping region of the gate insulating layer overlapping the gate electrode as Takebuchi discloses terminating with boron into a silicon oxide film, as discussed above.
Takebuchi discloses that the “semiconductor layer [is] primarily composes of silicon” (¶ 0036). Takebuchi, therefore, does not disclose an oxide semiconductor layer as claimed.
Yamazaki, in the same field of endeavor, discloses that as an alternative to “silicon-based semiconductor material[s] . . . . an oxide semiconductor” such as “zinc oxide or an In-Ga-Zn-based oxide semidonductor” may be used (¶¶ 0003-0004 of Yamazaki).
Because
(1) the prior art of Takebuchi, as discussed above, discloses a method which differs from the claimed method by the substitution of a silicon based semiconductor layer for the claimed oxide semiconductor layer;
(2) Yamazaki, as discussed above, discloses that oxide semiconductor layers and their function as a semiconductor layer within transistors was known in the art; and
(3) one of ordinary skill in the art before the effective filing date of the Application could have substituted an oxide semiconductor layer for the silicon based semiconductor layer (e.g., by forming a layer of oxide semiconductor material as the starting material and then proceeding with the remaining steps disclosed by Takebuchi), and the results of the substitution would have been predictable (as changing the specific composition of the semiconductor material does not alter the principle of operation of the device formed by the method),
it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to use an oxide semiconductor layer as required by claim 1 as it is a simple substitution of one known element for another to obtain predictable results. (MPEP 2143(I)(B)).
Takebuchi does not disclose the thickness of the gate insulating layer to determine if it falls within the claimed range.
However, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to perform routine experimentation to discover the workable range for the thickness of the gate insulating layer. As such, forming the gate insulating layer to be within the claimed range would have been obvious. In the resulting configuration, some portion of gate insulating layer would, accordingly, be 100 nanometers deep from the gate electrode.
Takebuchi does not disclose the thickness of the gate electrode to determine if it falls within the claimed range.
However, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to perform routine experimentation to discover the workable range for the thickness of the gate electrode. As such, forming the gate electrode to be within the claimed range would have been obvious.
Regarding claim 2, Takebuchi discloses that the gate insulating layer is a silicon oxide film (“The material of the gate oxide film 12 is e.g. silicon oxide”, ¶ 0037).
Response to Arguments
Applicant's arguments filed 2/26/2026 have been fully considered but they are not persuasive.
Regarding the rejections under 35 U.S.C. 112, Applicant argues that “Amended Claim 1 recites proper antecedents for all terms.” This argument is not persuasive as there is no antecedent basis for the limitation "the second region of the gate insulating layer" in the penultimate line of claim 1.
Regarding the rejections under 35 U.S.C. 103, Applicant argues that Takebuchi injects boron for the purpose of giving p-type conductivity type to the silicon layer and not for the purpose used by Applicant which is to repair defects. This argument is not persuasive as even though Takebuchi discloses a purpose for the boron injection that is different from the purpose disclosed by Applicant, Takebuchi still discloses the boron injection step and the preponderance of evidence of the record indicates that the benefit of repairing defects in the gate insulating will also occur, as discussed in the rejection of claim 1 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A CULBERT/ Examiner, Art Unit 2815
1 The Examiner is interpreting “contact” to be direct contact without an intervening component in light of Lines 8-17 on Page 5 of Applicant’s Specification as originally filed.
2 Although not explicitly stated, the Examiner notes that because the gate insulating layer 12 covers the entirety of the well region 24 of Takebuchi (see Fig. 4A), in order to be implanted “into the well region 24”, the boron must also go through the gate insulating layer.
3 The Examiner notes that the interface between the gate insulating layer and the gate electrode is “a region of the gate insulating layer overlapping the gate electrode”.
4 Since the indicated value of the impurity concentration falls within the claimed range of 1E + 16 [atoms/cm3] or more, the range is anticipated (MPEP § 2131.03).
5 The Examiner notes that the range in claim 3 has not been shown to be critical or have unexpected results as Applicant’s Specification states that the range of 30 keV or more and 40 keV or less is merely “preferabl[e]” when “the gate electrode . . . is a molybdenum film having a film thickness of 100 nm” (Lines 9-13 on Page 24 of Applicant’s Specification as originally filed) which has not yet been claimed. See MPEP 716.02(d) for a discussion of unexpected results needing to be commensurate in scope with the claimed invention.
Prosecution Insights