DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114 was filed in this application after appeal to the Patent Trial and Appeal Board, but prior to a decision on the appeal. Since this application is eligible for continued examination under 37 CFR 1.114 and the fee set forth in 37 CFR 1.17(e) has been timely paid, the appeal has been withdrawn pursuant to 37 CFR 1.114 and prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant’s submission filed on 14 August 2025 has been entered.
Response to Amendment
The Office acknowledges receipt on 14 August 2025 of Applicant’s amendments in which claims 1, 12, 19, 25-27, and 31 are amended, claim 28 is cancelled, and claim 32 is newly added. The Office withdraws the drawing objections, the claim objection, and the section 112(a) rejections identified in the Office Communication dated 16 April 2025 in view of the amendments.
Response to Arguments
Applicant’s arguments with respect to independent claim(s) 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues in the first paragraph of page 17 and with respect to amended independent claim 25 that Fujishima fails to disclose or suggest a second side of the portion of insulating film (25) directly under the second field plate (FP2) terminating between the first side of the gate electrode and the second side of the gate electrode, as required by amended claim 25. Claim 25 is rejected over the combined teachings of Fujishima and Shin and recites, in relevant part, “a first side of the dielectric layer terminates between a first boundary of the source region and a second boundary of the source region; and a second side of the dielectric layer terminates between the first side of the gate electrode and the second side of the gate electrode.”
Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Fujishima teaches in Fig. 18 a first side of the dielectric layer (portion of 25 directly beneath FP2) terminates between a first boundary of the source region (3) and a second boundary of the source region (3) {see Annotated Copy of Fujishima’s Fig. 18 below}; and a second side of the dielectric layer (portion of 25 directly beneath FP2) terminates between the first side of the gate electrode (9) and the second side of the gate electrode (9) {see Annotated Copy of Fujishima’s Fig. 18 below}.
PNG
media_image1.png
611
835
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 9, 12, 19, and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujishima et al. (US20020145172A1) in view of Ward et al. (US20170243937A1) and Ohno et al. (US20220093747A1).
Regarding claim 1, Fujishima teaches in Fig. 18 a microelectronic device comprising:
a substrate (1) {¶0197};
a source region (3) and a drain region (6) {¶0197};
a gate dielectric (7) {¶0197};
a gate electrode (9) on the gate dielectric (7), the gate electrode (9) having a first side facing toward the drain region (6) {¶0197};
a dielectric layer (10, 25, 14) extending over the gate electrode (9), the source region, and the drain region {¶0197}; and
a field plate (FP1) disposed on the dielectric layer (10, 25, 14), the field plate (FP1) including a second side facing toward the drain region (6), wherein the field plate (FP1) is electrically connected to the gate electrode (9) {¶0216, Fig. 18}.
Fujishima does not teach:
the substrate including silicon;
the source region and a drain region in the silicon
the gate dielectric on the silicon;
the first side of the gate electrode being nearer the drain region than the second side of the field plate;
the field plate extends at least partially over the source region.
In an analogous art, Ward teaches in Fig. 3 and paragraph [0103] a substrate (1000) including silicon. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device based on the teachings of Ward – such that Fujishima’s substrate includes silicon – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, all the claimed elements (e.g., substrate, silicon) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ward) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Consequences of this modification are that Fujishima’s: (1) source region and drain region are disposed in the silicon and (2) gate dielectric is disposed on the silicon.
In an analogous art, Ohno teaches in Fig. 1 and paragraph [0017] a first side of a gate electrode (6) being nearer a drain region (7) than a second side of a field plate (8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device as modified by Ward based on the teachings of Ohno – such that the first side of Fujishima’s gate electrode is nearer the drain region than the second side of Fujishima’s field plate – to reduce[] electric field concentration of the gate electrode … in a lateral direction. Ohno ¶0032. Moreover, all the claimed elements (e.g., gate electrode, drain region, field plate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ohno) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Ward further teaches in Fig. 3 and paragraphs [0098]-[0099] a field plate (185) extends at least partially over a source region (150) {Ward ¶0098, [t]he extended source contact 185 is generally termed as a field plate}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device as modified by Ward and Ohno based on the further teachings of Ward – such that the field plate extends at least partially over the source region – to reduce the peak electric field at the surface of the device. Ward ¶0110. Moreover, all the claimed elements (e.g., field plate, source region) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ward) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 2, Fujishima as modified by Ward and Ohno teaches the microelectronic device of claim 1, and Fujishima further teaches wherein the field plate (FP1) is part of a transistor (3, 6, 9) corresponding to a drain extended metal oxide transistor (DMOS), a metal oxide semiconductor (MOS transistor), a laterally diffused metal oxide semiconductor (LDMOS) transistor, an insulated gate bipolar transistor (IGBT), double diffused MOS (DDMOS), a double-diffused drain MOS (DDDMOS) a junction field effect transistor (JFET), a complementary metal oxide transistor (CMOS), or a gated bipolar transistor {¶0189, 0002, a high withstand voltage lateral MISFET device (RESURF LDMOS); Additionally, Fig. 18 illustrates a metal (9), oxide (8) semiconductor (5) (MOS) structure of a transistor having a source 3, a gate 9, and a drain 6}.
Regarding claim 9, Fujishima as modified by Ward and Ohno teaches the microelectronic device of claim 1, and Fujishima further teaches wherein the side field plate (FP1) includes aluminum {¶0210}.
Regarding claim 23, Fujishima as modified by Ward and Ohno teaches the microelectronic device of claim 1, but Fujishima does not teach wherein the field plate extends over the source region by a distance more than a quarter of a width of the source region.
Ward teaches in Fig. 3 a field plate (185) extends over a source region (150) by a distance more than a quarter of a width of the source region (150) {see Annotated Copy of Exploded View of Ward’s Fig. 3, below}. The motivation for this modification is identified with respect to base claim 1.
Examiner’s Note: “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
PNG
media_image2.png
378
482
media_image2.png
Greyscale
Regarding claim 24, Fujishima as modified by Ward and Ohno teaches the microelectronic device of claim 1, and Fujishima further teaches wherein the field plate (FP1) is electrically connected to the gate electrode (9) through a first conductive contact (h) of a contact layer (FP1, h, 11, 12) that includes second conductive contacts (11, 12) to the source region (3) and to the drain region (6), respectively {¶0216; FP1, h, 11, and 12 all have same hatching and are disposed in same layer}.
Regarding claim 12, Fujishima teaches in Fig. 18 a method comprising:
forming a well (2) in a substrate (1), {¶0197};
forming a source region (3) and a drain region (6) {¶0197};forming a gate dielectric (7) {¶0197};
forming a gate electrode (9) on the gate dielectric (7), the gate electrode (9) including a first side facing toward the drain region (6) {¶0197};
forming a source region (3) and a drain region (6) in the silicon (i.e., substrate (1)) {¶0197};
forming a dielectric layer (10, 15, 14) extending on the gate electrode (7), the source region (3), and the drain region (6) {¶0197}; and
forming a field plate (FP1) disposed on the dielectric layer (10, 15, 14), the field plate (FP1) including a second side facing toward the drain region (6), wherein the field plate (FP1) is electrically connected to the gate electrode (9) {¶0210}.
Fujishima does not teach:
the substrate including silicon;
the source region and the drain region in the silicon;
the gate dielectric on the silicon;
the first side of the gate electrode being nearer the drain region than the second side of the field plate;
the field plate extends at least partially over the source region.
Ward teaches in Fig. 3 and paragraph [0103] a substrate (1000) including silicon. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s method based on the teachings of Ward – such that Fujishima’s substrate includes silicon – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, all the claimed elements (e.g., substrate, silicon) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ward) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Consequences of this modification are that Fujishima’s: (1) source region and drain region are disposed in the silicon and (2) gate dielectric is disposed on the silicon.
Ohno teaches in Fig. 1 and paragraph [0017] a first side of a gate electrode (6) being nearer a drain region (7) than a second side of a field plate (8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s method as modified by Ward based on the teachings of Ohno – such that the first side of Fujishima’s gate electrode is nearer the drain region than the second side of Fujishima’s field plate – to reduce[] electric field concentration of the gate electrode … in a lateral direction. Ohno ¶0032. Moreover, all the claimed elements (e.g., gate electrode, drain region, field plate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ohno) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Ward further teaches in Fig. 3 and paragraphs [0098]-[0099] a field plate (185) extends at least partially over a source region (150). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s method as modified by Ward and Ohno based on the further teachings of Ward – such that the field plate extends at least partially over the source region – to reduce the peak electric field at the surface of the device. Ward ¶0110. Moreover, all the claimed elements (e.g., field plate, source region) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ward) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 19, Fujishima as modified by Ward and Ohno teaches the method of claim 12, and Fujishima further teaches wherein the field plate (FP1) includes aluminum {¶0210}.
Regarding claim 21, Fujishima as modified by Ward and Ohno teaches the method of claim 12, but Fujishima does not teach the field plate extends over the source region by a distance more than a quarter of a width of the source region.
Ward teaches in Fig. 3 a field plate (185) extends over a source region (150) by a distance more than a quarter of a width of the source region (150) {see Annotated Copy of Exploded View of Ward’s Fig. 3, below}. The motivation for this modification is identified with respect to base claim 12.
Examiner’s Note: “The Examiner is authorized to make a finding of relative dimensions that are, as here, clearly depicted in a drawing.” Ex parte Wright, 091818 USPTAB, 2017-001093 (Patent Trial and Appeal Board Decisions, 2018).
PNG
media_image2.png
378
482
media_image2.png
Greyscale
Regarding claim 22, Fujishima as modified by Ward and Ohno teaches the method of claim 12, and Fujishima further teaches wherein the field plate (FP1) is electrically connected to the gate electrode (9) through a first conductive contact (h) of a contact layer (FP1, h, 11, 12) including second conductive contacts (11, 12) to the source region (3) and to the drain region (6), respectively {¶0216; FP1, h, 11, and 12 all have same hatching and are disposed in same layer}.
Claim(s) 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujishima in view of Ward and Ohno as applied to claim 1 and claim 12 respectively above, and further in view of Strasser et al. (US20140312417A1).
Regarding claim 3, Fujishima as modified by Ward and Ohno teaches the microelectronic device of claim 1, and Fujishima further teaches further comprising a field oxide (8) {¶0197} disposed between the source region (3) and the drain region (6).
Fujishima does not teach the field oxide including a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure.
In an analogous art, Strasser teaches the field oxide layer (199) is a local oxidation of silicon (LOCOS) structure {¶0036}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device as modified by Ward and Ohno based on the teachings of Strasser – such that the field oxide includes a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure – for the purposes of: (1) forming a lateral isolation layer … to laterally insulate adjacent components of the semiconductor device {Strasser ¶0006} and (2) growing a silicon oxide layer … on the uncovered portions of the silicon surface, which can be accomplished by exposing the silicon surface to an oxidizing atmosphere such as an oxygen-rich atmosphere at elevated temperatures {Strasser ¶0036, 0046}.
Regarding claim 13, Fujishima as modified by Ward and Ohno teaches the method of claim 12, and Fujishima further teaches further comprising forming a field oxide structure (8).
Fujishima does not teach the field oxide structure including a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure.
Strasser teaches forming a field oxide structure (199) from a local oxidation of silicon (LOCOS) structure {¶0036}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s method as modified by Ward and Ohno based on the teachings of Strasser – such that the field oxide structure includes a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure – for the purposes of: (1) forming a lateral isolation layer … to laterally insulate adjacent components of the semiconductor device {Strasser ¶0006} and (2) growing a silicon oxide layer … on the uncovered portions of the silicon surface, which can be accomplished by exposing the silicon surface to an oxidizing atmosphere such as an oxygen-rich atmosphere at elevated temperatures {Strasser ¶0036, 0046}.
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujishima in view of Ward and Ohno as applied to claim 1 and claim 12 respectively above, and further in view of Shin et al. (US20170294505A1) and Snyder et al. (US20210367073A1).
Regarding claim 6, Fujishima as modified by Ward and Ohno teaches the microelectronic device of claim 1, but Fujishima does not teach further comprising:
a first drift region under the source region; and
a second drift region under the drain region.
However, Fujishima teaches a single drift region (5) disposed below and between the source region (4) and the drain region (6).
In an analogous art, Shin teaches in Fig. 4 and paragraph [0062] a first drift region (240) under the source region (260) and a second drift region (230) under the drain region (250). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device as modified by Ward and Ohno based on the teachings of Shin – such that a first drift region is disposed under the source region; and a second drift region is disposed under the drain region – so the doping profile of each of the two drift regions may be individually tailored. Snyder ¶0036.
Regarding claim 16, Fujishima as modified by Ward and Ohno teaches the method of claim 12, but Fujishima does not teach further comprising:
forming a first drift region under the source region; and
forming a second drift region under the drain region.
However, Fujishima teaches a single drift region (5) disposed below and between the source region (4) and the drain region (6).
Shin teaches in Fig. 4 and paragraph [0062] forming a first drift region (240) under the source region (260) and forming a second drift region (230) under the drain region (250). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s method as modified by Ward and Ohno based on the teachings of Shin – for forming a first drift region under the source region and forming a second drift region under the drain region – so the doping profile of each of the two drift regions may be individually tailored. Snyder ¶0036.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujishima in view of Ward and Ohno as applied to claim 1 and claim 12 respectively above, and further in view of Lee et al. (US20130168766A1).
Regarding claim 7, Fujishima as modified by Ward and Ohno teaches the microelectronic device of claim 1, but Fujishima does not teach further comprising:
a backgate region in silicon, the backgate region being separated from the source region by an isolation structure.
In an analogous art, Lee teaches in Fig. 4F and paragraph [00033] a backgate region (212) in silicon (204), the backgate region (212) being separated from the source region (214) by an isolation structure (210). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device as modified by Ward and Ohno based on the teachings of Lee – such that a backgate region is disposed in silicon, the backgate region being separated from the source region by an isolation structure – for the purposes of: (1) providing an insulating region between the voltage potentials applied to the back gate 212 and the source 214 and (2) providing a potential to the back gate, which is connected to an n-well 208, so as to prevent or minimize the n-well from floating. Lee ¶0004.
Regarding claim 17, Fujishima as modified by Ward and Ohno teaches the method of claim 12, but Fujishima does not teach further comprising:
forming a backgate region in the silicon, the backgate region being separated from the source region by an isolation structure.
Lee teaches in Fig. 4F and paragraph [00033] forming a backgate region (212) in silicon (204), the backgate region (212) being separated from a source region (214) by an isolation structure (210). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s method as modified by Ward and Ohno based on the teachings of Lee – for forming a backgate region in the silicon, the backgate region being separated from the source region by an isolation structure – for the purpose of: (1) providing an insulating region between the voltage potentials applied to the back gate 212 and the source 214 and (2) providing a potential to the back gate, which is connected to an n-well 208, so as to prevent or minimize the n-well from floating. Lee ¶0004.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujishima in view of Ward, Ohno, and Lee as applied to claim 7 above, and further in view of Shin.
Regarding claim 8, Fujishima as modified by Ward, Ohno, and Lee teaches the microelectronic device of claim 7, but Fujishima does not teach wherein:
the backgate region is a first conductivity type and coupled to a well of the first conductivity type in the silicon; and
the source and drain regions are a second conductivity type opposite the first conductivity type, the source and drain regions disposed in the well.
Lee teaches in Fig. 4F and paragraph [00033] the backgate region (212) is a first conductivity type (n-type) and coupled to a well (208) of the first conductivity type (n-type) in the silicon (204); and the source (214) and drain regions (216) are a second conductivity type (p-type) opposite the first conductivity type (n-type). The motivation for this modification is identified with respect to intermediate claim 7.
Shin teaches in Fig. 4 and paragraph [0061] the source (260) and drain regions (250) disposed in the well (204). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device as modified by Ward, Ohno, and Lee based on the teachings of Shin – such that the source and drain regions disposed in the well – because all the claimed elements (e.g., source, drain, well) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (as taught by Shin) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujishima in view of Ward and Ohno as applied to claim 1 above, and further in view of Ho et al. (US20190334032A1).
Regarding claim 10, Fujishima as modified by Ward and Ohno teaches the microelectronic device of claim 1, but Fujishima does not teach wherein the field plate includes copper.
However, Fujishima teaches the source side field plate (FP1) is made of aluminum or the like {¶0210}.
In an analogous art, Ho teaches in Fig. 3 a substrate (102), a field oxide layer (302), a gate dielectric (110), a gate electrode (108), a source region (104), a drain region (106), a metal dielectric (124), and a field plate (214) {¶0037, 0042, 0043}. Ho further teaches the field plate includes copper {0041}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device as modified by Ward and Ohno based on the teachings of Ho – such that the source side field plate includes copper – because copper has greater conductivity than Fujishima’s disclosed aluminum. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 25, 26, 30, and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujishima in view of Shin.
Regarding claim 25, Fujishima teaches in Fig. 18 a microelectronic device, comprising:
a substrate (1) {¶0197};
a gate electrode (9) disposed over the substrate (1) {¶0197};
a first spacer (portion of 10 to left of ‘h’) on a first side (left side) of the gate electrode (9) {¶0197};
a second spacer (portion of 10 to right of ‘h’) on a second side (right side) of the gate electrode (9), the second side (right side) opposite the first side (left side) {¶0197};
a source region (3) in the substrate (1), the source region (3) being adjacent to the first spacer (portion of 10 to left of ‘h’) {¶0197};
a field oxide structure (8) in or on the substrate (1), the second side (right side) of the gate electrode (9) terminating over the field oxide structure (8), wherein the second spacer (portion of 10 to right of ‘h’) is on the field oxide structure (8) {¶0197};
a drain region (6) in the substrate (1), the drain region (6) being adjacent to the field oxide structure (8);
a dielectric layer (portion of 25 directly beneath FP2) disposed on a portion of the gate electrode (9), the first spacer (portion of 10 to left of ‘h’), and at least a portion of the source region (3) {¶0197; “on” broadly interpreted to have its most common meaning of “[p]osition above”}; wherein
a first side of the dielectric layer (portion of 25 directly beneath FP2) terminates between a first boundary of the source region (3) and a second boundary of the source region (3) {see Annotated Copy of Fujishima’s Fig. 18 below}; and
a second side of the dielectric layer (portion of 25 directly beneath FP2) terminates between the first side of the gate electrode (9) and the second side of the gate electrode (9) {see Annotated Copy of Fujishima’s Fig. 18 below}; and
a field plate (FP2) of a conductive material (aluminum) disposed directly on the dielectric layer (25), the field plate (FP2) being electrically connected to the gate electrode (9), wherein the dielectric layer (portion of 25 directly beneath FP2) and the field plate (FP2) have a substantially same footprint {¶0216}.
Fujishima does not teach: the first and second spacers are symmetrical.
Shin teaches in Fig. 4 and paragraph [0069] the first and second spacers (220) are symmetrical. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device based on the teachings of Shin – such that the first and second spacers are symmetrical – because all the claimed elements (e.g., spacers, symmetric) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (as taught by Shin) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
PNG
media_image1.png
611
835
media_image1.png
Greyscale
Regarding claim 26, Fujishima as modified by Shin teaches the microelectronic device of claim 25, and Fujishima further teaches further comprising: a second dielectric layer (14) disposed on the field plate (FP2), wherein the second dielectric layer (14) has a planarized surface and has varying thicknesses over the substrate (1) {¶0003}.
Regarding claim 30, Fujishima as modified by Shin teaches the microelectronic device of claim 25, and Fujishima further teaches wherein the field plate (FP2) includes metal (aluminum) {¶0216}.
Regarding claim 31, Fujishima as modified by Shin teaches the microelectronic device of claim 25, and Fujishima further teaches wherein the dielectric layer (portion of 25 directly beneath FP2) is conformal to a surface (surface of 8) underneath and has a substantially uniform thickness (in the portion of 25 extending laterally from rightmost portion of FP1 to rightmost portion of FP2).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujishima in view of Shin as applied to claim 26 above, and further in view of Kuo et al. (US20170352731A1) and Ho.
Regarding claim 27, Fujishima as modified by Shin teaches the microelectronic device of claim 26, but Fujishima does not teach further comprising:
a first conductive contact extending from the field plate to a metal layer through the second dielectric layer; and
a second conductive contact extending from the gate electrode to the metal layer through the second dielectric layer such that the field plate is electrically connected to the gate electrode.
In an analogous art, Kuo teaches in Fig. 1 and paragraph [0015] a first conductive contact (122) extending from a field plate (131) to a metal layer (128) through the dielectric layer (118) and a second conductive contact (120) extending from a gate electrode (108) to another metal layer (128) through the dielectric layer (118). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device as modified by Shin based on the teachings of Kuo – such that a first conductive contact extends from the field plate to a metal layer through the dielectric layer and a second conductive contact extends from the gate electrode to the other metal layer through the dielectric layer – for the purpose of providing an electrical signal to each of the gate electrode and the field plate from an external location.
Ho teaches in Fig. 6 and paragraph [0056] a field plate (214) is electrically connected to a gate electrode (108) through the same metal layer (604). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device as modified by Shin and Kuo based on the teachings of Ho – such that the field plate is electrically connected to the gate electrode through the same metal layer – so the field plate … is biased by the gate voltage [to] … provide[ the] high voltage LDMOS device 600 with a low Rds(on) vs. breakdown voltage. Ho ¶0056.
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujishima in view of Shin as applied to claim 25 above, and further in view of Hshieh et al. (US5578851A).
Regarding claim 29, Fujishima as modified by Shin teaches the microelectronic device of claim 25, but Fujishima does not teach wherein the field plate includes polysilicon.
In an analogous art, Hshieh teaches in Fig. 1k and lines 14-17 of column 4 a field plate (132b) includes polysilicon. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device as modified by Shin based on the teachings of Hshieh – such that the field plate includes polysilicon – for improv[ing] breakdown voltage in the termination region by smoothing the electric field distribution. Hshieh col. 4, ll. 14-17.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujishima in view of Shin as applied to claim 25 above, and further in view of Yadav et al. (US20170179280A1).
Regarding claim 32, Fujishima as modified by Shin teaches the microelectronic device of claim 25, but Fujishima does not teach wherein the dielectric layer includes silicon nitride.
In an analogous art, Yadav teaches in paragraph [0026] and [0028] a dielectric layer (51/52) includes silicon nitride. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fujishima’s microelectronic device as modified by Shin based on the teachings of Yadav – such that the dielectric layer includes silicon nitride – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al. (US20240136413A1) teaches a semiconductor device includes: a substrate; a body region having a first conductivity type and formed in the substrate; a drift region, having a second conductivity type, formed in the substrate and adjacent to the body region; a field plate structure, formed on the drift region, a lower surface of an end of the field plate structure close to the body region being flush with the upper surface of the substrate, and the end of the field plate structure close to the body region also having an upwardly extending inclined surface; and a drain region, having a second conductivity type, formed in an upper layer of the drift region, and in contact with the end of the field plate structure away from the body region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891