DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-14 and 17-22 are pending.
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/27/2026 has been entered.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 04/27/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Response to Arguments
5. Applicant’s arguments with respect to the amended independent claims have been considered but are moot in view of the new ground(s) of rejection in which the Examiner has cited previously presented prior art, Steely, Jr. et al. (US Patent No. 10,691,182 B2 hereinafter “Steely”), as necessitated by the amended independent claim, disclosing the VC portals 517, 527 acting as the first and second routers allowing data to be transferred between the compute layer and the memory layer via the network layer.
Claim Objections
6. Claim 1 is objected to because of the following informalities: Line 7 states “the plurality of routers is” and should be replaced with “the plurality of routers are”. Appropriate correction is required.
7. Claim 21 is objected to because of the following informalities: Lines 1-2 state “the plurality of routers is” and should be replaced with “the plurality of routers are”. Appropriate correction is required.
8. Claim 22 is objected to because of the following informalities: Lines 1-2 state “the plurality of routers is” and should be replaced with “the plurality of routers are”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
10. Claims 1-8, 11, 12, 14, 17, 18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Steely, Jr. et al. (US Patent No. 10,691,182 B2 hereinafter “Steely”).
Referring to claim 1, Steely discloses a system on chip (SoC) (Steely – Fig. 1(a) & col. 6, lines 26-28 disclose the computing system 100 includes the computing IC 110, which is included in a semiconductor package 103.) comprising:
a first layer including at least one component having a first network interface (Steely – Fig. 4(a) shows a computing tile 414 in a computing layer 405. Fig. 4(b) shows network VC ports 446. Fig. 4(a) & col. 11, line 39 disclose a computing tile 414 in a computing layer 405. Fig. 4(b) & col. 12, lines 8-10 disclose there may be other computing elements, e.g., a processor core, or an application specific integrated circuit (ASIC) in the computing tile 414.);
a second layer having a second network interface (Steely – Fig. 4(a) shows a memory tile 418 in a memory layer 409. Col. 13, line 45 disclose address ports of a D-bank 452 of the memory layer 409.); and
a network layer (Steely – Figs. 5(a)-5(b) shows a network layer 507.) including a plurality of routers connected to the first network interface and the second network interface (Steely – Figs. 5(a)-5(b) & Col. 13, line 53 to col. 14, line 11 disclose the dataflow to/from a computing tile 514 of the computing layer 505 using VC portal 527 and VC portal 517 (in the network tiles 510, 520 of the network layer 507) with memory tile 518 of the memory layer 509. The VC portals 517, 527 are viewed routers since they are components used to route data from the compute layer to the memory layer via the network layer.),
wherein the network layer is positioned between the first layer and the second layer (Steely – Fig. 2 shows a network layer 207 is positioned between the computing layer 205 and the memory layer 209.), and
wherein the plurality of routers is configured to route data between the first layer and the second layer through at least two routers of the plurality of routers comprising a first router and a second router of the network layer, the first router being configured to direct data from the first network interface of the first layer to the second router and the second router being configured to direct the data to the second network interface of the second layer (Steely – Figs. 5(a)-5(b) & Col. 13, line 53 to col. 14, line 11 disclose the dataflow to/from a computing tile 514 of the computing layer 505 using VC portal 527 and VC portal 517 (in the network tiles 510, 520 of the network layer 507) with memory tile 518 of the memory layer 509. The VC portals 517, 527 are viewed routers since they are components used to route data from the compute layer to the memory layer via the network layer.).
Referring to claim 2, Steely discloses the system of claim 1, wherein the first layer is an application specific integrated circuit (ASIC) layer bonded to the network layer (Steely – Fig. 2 & col. 9, lines 49-56 disclose additionally and alternatively, the network layer 207, the computing layer 205, or the memory layer 209 may be bonded together by direct bonding, where one or more contact points 212 of a first tile in a first layer is in direct contact with one or more contact points of a second tile of a second layer, the first layer or the second layer may be selected from the network layer 207, the computing layer 205, or the memory layer 209. Fig. 4(a) & col. 11, line 39 disclose a computing tile 414 in a computing layer 405. Fig. 4(b) & col. 12, lines 8-10 disclose there may be other computing elements, e.g., a processor core, or an application specific integrated circuit (ASIC) in the computing tile 414.).
Referring to claim 3, Steely discloses the system of claim 2, wherein the first network interface connects the at least one component to the one or more routers (Steely – Col. 13, lines 33-45 disclose the network tile 416 having a VC portal 461 coupled to a multiplexer 465 to be selectively coupled to a compute element in the computing layer 405 or to the address ports of a D-bank 452 of the memory layer 409.).
Referring to claim 4, Steely discloses the system of claim 3, wherein each of the at least one component is connected to at least one of the one or more routers via one or more conductive structures (Steely – Fig. 2 & col. 9, lines 47-56 disclose The network layer 207, the computing layer 205, or the memory layer 209 may be coupled together by through-silicon vias (TSV) 214. Additionally and alternatively, the network layer 207, the computing layer 205, or the memory layer 209 may be bonded together by direct bonding, where one or more contact points 212 of a first tile in a first layer is in direct contact with one or more contact points of a second tile of a second layer, the first layer or the second layer may be selected from the network layer 207, the computing layer 205, or the memory layer 209.).
Referring to claim 5, Steely discloses the system of claim 4, wherein the conductive structures include one or more of traces, vias, contacts, or terminals (Steely – Fig. 2 & col. 9, lines 47-56 disclose The network layer 207, the computing layer 205, or the memory layer 209 may be coupled together by through-silicon vias (TSV) 214. Additionally and alternatively, the network layer 207, the computing layer 205, or the memory layer 209 may be bonded together by direct bonding, where one or more contact points 212 of a first tile in a first layer is in direct contact with one or more contact points of a second tile of a second layer, the first layer or the second layer may be selected from the network layer 207, the computing layer 205, or the memory layer 209.).
Referring to claim 6, Steely discloses the system of claim 2, wherein the network layer includes: an active surface (Steely – Fig. 4(a) shows a top surface having network tiles 416 of a network layer 407.); and a second surface opposite the active surface (Steely – Col. 6, lines 47-48 disclose the network layer 107 has a first side and a second side opposite to the first side.).
Referring to claim 7, Steely discloses the system of claim 6, wherein the ASIC layer (Steely – Fig. 4(b) & col. 12, lines 8-10 disclose there may be other computing elements, e.g., a processor core, or an application specific integrated circuit (ASIC) in the computing tile 414.) includes: an active surface (Steely – Fig. 4(a) shows a top surface having computing tiles 414 in a computing layer 405.); and a second surface opposite the active surface (Steely – Fig. 2 shows a second side opposite to the top side.).
Referring to claim 8, Steely discloses the system of claim 7, wherein the active surface of the ASIC layer and the second surface of the network layer each includes one or more contacts, wherein the network layer is bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer (Steely – Fig. 2 & col. 9, lines 49-56 disclose additionally and alternatively, the network layer 207, the computing layer 205, or the memory layer 209 may be bonded together by direct bonding, where one or more contact points 212 of a first tile in a first layer is in direct contact with one or more contact points of a second tile of a second layer, the first layer or the second layer may be selected from the network layer 207, the computing layer 205, or the memory layer 209.).
Referring to claim 11, Steely discloses the system of claim 6, wherein the second layer is a memory layer including an active surface including one or more contacts (Steely – Fig. 2 & col. 9, lines 49-56 disclose additionally and alternatively, the network layer 207, the computing layer 205, or the memory layer 209 may be bonded together by direct bonding, where one or more contact points 212 of a first tile in a first layer is in direct contact with one or more contact points of a second tile of a second layer, the first layer or the second layer may be selected from the network layer 207, the computing layer 205, or the memory layer 209.).
Referring to claim 12, Steely discloses the system of claim 11, wherein the memory layer is bonded to the network layer via bonds formed between one or more contacts on the active surface of the network layer and the one or more contacts on the active surface of the memory layer (Steely – Fig. 2 & col. 9, lines 49-56 disclose additionally and alternatively, the network layer 207, the computing layer 205, or the memory layer 209 may be bonded together by direct bonding, where one or more contact points 212 of a first tile in a first layer is in direct contact with one or more contact points of a second tile of a second layer, the first layer or the second layer may be selected from the network layer 207, the computing layer 205, or the memory layer 209.).
Referring to claim 14, Steely discloses the system of claim 12, wherein the memory layer includes one or more memory segments (Steely – Fig. 4(c) & col. 11, lines 59-64 disclose the memory tile 418 represents a memory tile stack or a memory stack having multiple tiles in multiple sublayers, e.g., a tile of a control sublayer 451 of the memory layer 409, and one or more storage tiles of one or more storage sublayers 453, e.g., 8 storage sublayers, of the memory layer 409.), the network layer is configured to route data between the at least one component in the ASIC layer and the one or more memory segments (Steely – Fig. 4(d) & col. 13, lines 33-38 disclose The portal 461 can be coupled to a multiplexer 465 to be selectively coupled to a storage cell in the memory layer 409, or to a computing element 469 of the computing tile 414 of the computing layer 405. The network tile 416 functions as an integrated nexus for data movement, both within the tile stack and between the tile and its neighbors.), and wherein each of the one or more memory segments is connected to at least one of the one or more routers in the network layer (Steely – Col. 13, lines 33-45 disclose the network tile 416 having a VC portal 461 coupled to a multiplexer 465 to be selectively coupled to a compute element in the computing layer 405 or to the address ports of a D-bank 452 of the memory layer 409.) via one or more conductive structures (Steely – Fig. 2 & col. 9, lines 47-56 disclose The network layer 207, the computing layer 205, or the memory layer 209 may be coupled together by through-silicon vias (TSV) 214. Additionally and alternatively, the network layer 207, the computing layer 205, or the memory layer 209 may be bonded together by direct bonding, where one or more contact points 212 of a first tile in a first layer is in direct contact with one or more contact points of a second tile of a second layer, the first layer or the second layer may be selected from the network layer 207, the computing layer 205, or the memory layer 209.).
Referring to claim 17, Steely discloses the system of claim 14, wherein the network layer is configured to ignore faulty (Steely – Col. 9, lines 32-34 disclose distributed place and route algorithms for the network layer 107 may route around defective tiles.) memory segments within the one or more memory segments (Steely – Col. 11, lines 43-45 disclose the memory tile 418 may represent a memory tile stack or a memory stack having multiple tiles in multiple sublayers, e.g., a tile of a control sublayer of the memory layer, and one or more storage tiles of one or more storage sublayers of the memory layer.).
Referring to claim 18, Steely discloses the system of claim 1, wherein the plurality of routers are connected via one or more routing traces in the network layer (Steely – Fig. 1(a) & col. 7, lines 35-47 disclose the network layer 107 may include a single-hop circuit-switched network to support circuit-switching, where the single-hop circuit-switched network is configured by software. The single-hop circuit-switched network may include one or more signal pathways or virtual circuits (VC). For example, the network layer 107 may include a VC 142 starting at a tile 141 and ending at a tile 143, where the VC 142 is a direct, unbuffered signal pathway extending through multiple tiles of the network layer 107. The network layer 107 may include one or more signal pathways or VCs, e.g., the VC 142, dynamically configurable between multiple pre-defined topologies for the multiple tiles on the die of the network layer 107.).
Referring to claim 20, Steely discloses the system of claim 2, wherein the at least one component includes one or more of processors, graphics processing units (GPUs), logic boards, digital sound processors (DSP), or network adaptors (Steely – Fig. 4(b) & col. 12, lines 8-10 disclose there may be other computing elements, e.g., a processor core, or an application specific integrated circuit (ASIC) in the computing tile 414.).
Claim Rejections - 35 USC § 103
11. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claims 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Steely in view of Teig et al. (US Patent No. 10,672,744 B2 hereinafter “Teig” – IDS Submission).
Referring to claim 9, Steely discloses the system of claim 8, however, fails to explicitly disclose wherein the bonds are formed via ZiBond direct bonding and/or direct bond interconnect (DBI) hybrid bonding.
Teig discloses the bonds are formed via ZiBond direct bonding and/or direct bond interconnect (DBI) hybrid bonding (Teig – Fig. 5 shows a DBI Bonding Layer between each of the dies.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Teig’s teachings with Steely’s techniques because it is advantageous to use DBI connections to connect overlapping connected regions on two dies that are vertically stacked because DBI allows for far greater density of connections than other z-axis connection schemes (Teig – Col. 18, lines 35-39).
Referring to claim 13, Steely discloses the system of claim 12, however, fails to explicitly disclose wherein the bonds are formed via ZiBond direct bonding and/or direct bond interconnect (DBI) hybrid bonding.
Teig discloses the bonds are formed via ZiBond direct bonding and/or direct bond interconnect (DBI) hybrid bonding (Teig – Fig. 5 shows a DBI Bonding Layer between each of the dies.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Teig’s teachings with Steely’s techniques because it is advantageous to use DBI connections to connect overlapping connected regions on two dies that are vertically stacked because DBI allows for far greater density of connections than other z-axis connection schemes (Teig – Col. 18, lines 35-39).
13. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Steely in view of Barowski et al. (US Patent No. 9,501,603 B2 hereinafter “Barowski”).
Referring to claim 10, Steely discloses the system of claim 6, wherein the second surface of the ASIC layer to form electrical connections between the SoC with one or more components external to the SoC (Steely – See fig. 1(a) showing a computing layer 105 within a package 103 coupled to a PCB 101.).
Barowski discloses the second surface of the processor layer includes one or more terminals configured to form electrical connections between the SoC with one or more components external to the SoC (Barowski – Fig. 2 & col. 7, lines 26-37 disclose C4s 212 of processor chip 218 are then subsequently bonded to conductive pads 220 of PC board 222. PC board 222 may be useful as a platform on which to mechanically mount and through which to electrically interconnect a 3-D IC, including chips 204, 218, with other electronic devices.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Barowski’s teachings with Steely’s techniques for providing cost-effective design changes for use in 3-D IC designs by using existing and proven design, floorplanning, routing and 3-D IC fabrication technologies (Barowski – Col. 2, lines 24-26).
14. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Steely in view of Solomon (US Patent No. 8,042,082 B2 hereinafter “Solomon” – IDS Submission).
Referring to claim 19, Steely discloses the system of claim 1, however, fails to explicitly disclose wherein the network layer is connected to memory located outside of the SoC.
Solomon discloses the network layer is connected to memory located outside of the SoC (Solomon – Col. 19, lines 60-65 disclose FIG. 31 shows a router on a layer of a multilayer IC. The router (R1) transfers data from external devices to the multilayer memory module. Data are imported both through the router and through the logic layer. Data are also transferred from the memory module to external devices from the router and the logic layer. Col. 19, lines 26-29 disclose data are sent to these crossbars on the outside edges of the iSoC package as an intermediate destination before off-loading to external memory devices.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Solomon’s teachings with Steely’s techniques because it uses 3D logic and memory nodes, the system has closer memory access and faster response (Solomon – Col. 5, lines 66-66).
15. Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Steely in view of Small et al. (US Pub. No. 2008/0144513 A1 hereinafter “Small”).
Referring to claim 21, Steely discloses the system of claim 1, however, fails to explicitly disclose wherein the plurality of routers arranged in a ring pattern.
Small discloses wherein the network layer includes a plurality of routers arranged in a ring pattern (Small – Par. [0017] discloses routers 130-135, 140-142 of the example transport network 110 of FIG. 1 are arranged and/or communicatively coupled to create any type of transport network topology, such as a mesh topology, a ring topology, a star topology, and/or any combination(s) of such topologies.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Small’s teachings with Steely’s techniques for providing Methods and apparatus to manage network transport paths in accordance with network policies (Small – Abstract).
Referring to claim 22, Steely discloses the system of claim 1, however, fails to explicitly disclose wherein the network layer includes a plurality of routers arranged in a star pattern.
Small discloses wherein the plurality of routers arranged in a star pattern (Small – Par. [0017] discloses routers 130-135, 140-142 of the example transport network 110 of FIG. 1 are arranged and/or communicatively coupled to create any type of transport network topology, such as a mesh topology, a ring topology, a star topology, and/or any combination(s) of such topologies.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Small’s teachings with Steely’s techniques for providing Methods and apparatus to manage network transport paths in accordance with network policies (Small – Abstract).
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Ill(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
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/DAYTON LEWIS-TAYLOR/Examiner, Art Unit 2181
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