Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
6 pending office actions • 6 art units • 6 examiners • 0 of 6 (0%) have an AI response strategy ready • 11 patents granted in the last 365 days
Adeia Semiconductor Technologies LLC is managing 6 pending office actions in the Semiconductors, Circuits & Optics technology area. These actions are distributed across 6 distinct examiners, resulting in a diverse set of interactions for the applicant. The portfolio also spans 6 distinct art units, which suggests that each pending application involves a unique technical niche or specialized set of patent rules within the semiconductor field. This level of dispersion, where 6 actions are split among 6 examiners, requires a versatile prosecution approach.
JASON CRAWFORD is the busiest examiner for this portfolio, though they are responsible for only 1 busiest examiner pending action. This indicates that no single examiner has a dominant influence over the current docket. Practitioners must therefore adapt to the specific examination styles of six different individuals across six different units, as the workload is perfectly distributed without any examiner concentration. Managing 6 distinct art units simultaneously means the applicant must stay informed on the specific examination guidelines and internal practices of multiple USPTO divisions.
Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 2 (33%) |
| §102 only | 1 (17%) |
| §112 only | 1 (17%) |
| Multi-statute (no §101) | 2 (33%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| CRAWFORD, JASON | 1 | 85.0% | +9.1% |
| HUGHES, DEANDRA M | 1 | 78.5% | +18.4% |
| GAMINO, CARLOS J | 1 | 35.3% | +45.6% |
| RAHMAN, ARIFUR | 1 | — | — |
| GHEYAS, SYED I | 1 | 82.5% | +3.9% |
| LEWIS-TAYLOR, DAYTON A. | 1 | 81.1% | +2.7% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 19084097 | Symbiotic Network On Layers | CRAWFORD, JASON | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18467481 | MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER | GHEYAS, SYED I | 13d |
| 17577944 | Network On Layer Enabled Architectures | LEWIS-TAYLOR, DAYTON A. | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18885513 | CIRCUIT ASSEMBLIES WITH MULTIPLE INTERPOSER SUBSTRATES, AND METHODS OF FABRICATION | HUGHES, DEANDRA M | — |
| 18601402 | Advanced Device Assembly Structures And Methods | GAMINO, CARLOS J | — |
| Art Unit | Apps |
|---|---|
| 2845 | 1 |
| 3992 | 1 |
| 1735 | 1 |
| 2800 | 1 |
| 2893 | 1 |
| 2181 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19084097 | Symbiotic Network On Layers | CRAWFORD, JASON | 2845 | §102 | Non-Final OA | — | Pending | Mar 19, 2025 |
| 18885513 | CIRCUIT ASSEMBLIES WITH MULTIPLE INTERPOSER SUBSTRATES, AND METHODS OF FABRICATION | HUGHES, DEANDRA M | 3992 | §112 | Non-Final OA | — | Pending | Sep 13, 2024 |
| 18601402 | Advanced Device Assembly Structures And Methods | GAMINO, CARLOS J | 1735 | §103 | Non-Final OA | — | Pending | Mar 11, 2024 |
| 18372947 | ACTIVE BRIDGING APPARATUS | RAHMAN, ARIFUR | 2800 | §103 | Final Rejection | — | Pending | Sep 26, 2023 |
| 18467481 | MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER | GHEYAS, SYED I | 2893 | §102§103 | Final Rejection | 13d | Pending | Sep 14, 2023 |
| 17577944 | Network On Layer Enabled Architectures | LEWIS-TAYLOR, DAYTON A. | 2181 | §102§103 | Non-Final OA | — | Pending | Jan 18, 2022 |
IP Author helps IP teams respond to office actions faster with AI-generated responses, examiner analytics, and prosecution intelligence.
Start Free Trial