DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in CN on01/19/2021. It is noted, however, that applicant has not filed a certified copy of the CN 202110067073.2 application as required by 37 CFR 1.55. Applicant should refer to the procedure outlined in practice TIP #2 “What should I do if a foreign priority document is available via the WIPO DAS but is not visible in the U.S. application file?” in the Electronic Priority Document Exchange (PDX) Program website. Of note, “the applicant should… request that the matter be escalated to determine why the priority document is not yet in the file” and “the applicant continues to bear the ultimate responsibility for ensuring that the priority document is filed during the pendency of the application before the patent is issued.”
Response to Arguments
Drawing Objections
Applicant has amended the drawings at issue and the previous objections have therefore been withdrawn.
Specification Objections
Applicant has amended the specification at issue and the previous objections have therefore been withdrawn.
Claim Rejections – 35 USC 112
Applicant has amended the claims at issue and the previous 112 rejections have therefore been withdrawn.
Claim Rejections – 35 USC 101
Applicant’s arguments, filed 10/2/2025, with respect to claims 1, 24 have been fully considered and are persuasive. The 101 rejection has been withdrawn.
Prior Art Rejections
Applicant's arguments filed 10/2/2025 have been fully considered but they are not persuasive.
Applicant asserts Khedr fails to teach or suggest a scheduler that schedules arithmetic operations on decoded to-be-executed homomorphic encryption instructions, with the interpretation the master control circuitry of Khedr corresponds to a scheduler and ciphertext of Khedr corresponds to the to-be-executed instructions. Examiner respectfully disagrees. The Examiner interprets the operations of Khedr to correspond with instructions, and the ciphertext is encrypted data which corresponds with homomorphic encrypted data. Thus, it will be explained that the operations of Khedr correspond to decoded instructions, and not the ciphertext. Instruction decoding is well understood, routine, and conventional in the art. Hennessy et al. (Computer Architecture A Quantitative Approach, hereinafter “Hennessy”) shows that instruction decoding is well understood, routine and conventional (Figs. 3.36, 3.37, 3.41; pg. 169 “In the classic five-stage pipeline, both structural and data hazards could be checked during instruction decode (ID):”; Appendix pg. C-5, C-6). Hence, one of ordinary skill in the art would understand the master control circuitry of Khedr, which schedules homomorphic operations (Khedr: [0026], [0027]), would output control signals to the parallel coprocessors that are in a decoded form, relative to the operations that are input to the master control circuitry. Therefore, Khedr teaches a scheduler that assigns operations that are decoded to-be-executed homomorphic encryption instructions. Furthermore, the previous rejection of claim 2 includes circuitry for performing the instruction decoding.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Number theoretic transform unit and Arithmetic logic unit in claim 1 and claim 24.
Butterfly processing subunit in claim 11.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
As to claim 1 and 24’s number theoretic transform unit, the examiner interprets the means plus function limitation to the corresponding structure: a first polynomial coefficient storage subunit; a second polynomial coefficient storage subunit; a twiddle factor storage subunit; and a butterfly processing subunit as disclosed in Fig. 4, [91] – [92] of the applicant’s specification.
As to claim 1 and 24’s arithmetic logic unit, the examiner interprets the means plus function limitation to the corresponding structure: modulus adder, a modulus multiplier, a fifth multi-path gating selector, a sixth multi-path gating selector, and a seventh multi-path gating selector as disclosed in Fig. 6, [113] – [121] of the applicant’s specification.
As to claim 11’s butterfly processing unit, the examiner interprets the means plus function limitation to the corresponding structure: a first multi-path gating selector, a second multi-path gating selector, a third multi-path gating selector, a fourth multi-path gating selector, a first adder, a second adder, a first subtractor, a second subtractor, and a first multiplier as disclosed in Fig.5, [93] – [95] of the applicant’s specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Turan et al. (HEAWS: An Accelerator for Homomorphic Encryption on the Amazon AWS FPGA, hereinafter “Turan”) in view of Khedr et al. (US 20180294950 A1, hereinafter “Khedr”).
As per claim 1, Turan teaches An acceleration unit, comprising: one or more number theoretic transform units adapted to perform number theoretic transform on homomorphic encrypted data (Turan: Fig. 3, page 1186 right column first paragraph);
one or more arithmetic logic units adapted to perform arithmetic operations on the homomorphic encrypted data (Turan: Fig. 3, page 1186 right column first paragraph; RPAUs corresponding to arithmetic logic units);
However, while Turan discloses coprocessors with dedicated instruction set (section 4 paragraph), Turan does not explicitly disclose circuitry that assigns the operations. Thus, Turan does not teach and a scheduler adapted to assign operations in a to-be-executed homomorphic encryption instruction, involving homomorphic encrypted data, to at least one of the one or more number theoretic transform units and at least one of the one or more arithmetic logic units, wherein the to-be-executed homomorphic encryption instruction is a decoded to-be-executed homomorphic encryption instruction.
Khedr teaches and a scheduler adapted to assign operations in a to-be-executed homomorphic encryption instruction to at least one of the one or more number theoretic transform units and at least one of the one or more arithmetic logic units, wherein the to-be-executed homomorphic encryption instruction is a decoded to-be-executed homomorphic encryption instruction (Khedr: Fig. 2 element 218, [0024] – [0027], [0098]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the coprocessor of Turan with the control unit of Khedr. One would have been motivated to combine these references because both references disclose accelerators for homomorphic processing, and combining prior art elements according to known methods to yield predictable results (controlling the coprocessors).
As per claim 4, Turan/Khedr further teaches The acceleration unit according to claim 1, wherein the scheduler divides the to-be-executed homomorphic encryption instruction into at least one of the following: modulus multiply operation, modulus add operation, number theoretic transform, inverse number theoretic transform, modulus switch, key switch, and rescale (Turan: pg. 1192 “These instructions are used for coefficient-wise addition/multiplication, NTT, inverse-NTT, coefficient rearrangement, Liftq!Q , and ScaleQ!q”).
As per claim 5, Turan/Khedr further teaches The acceleration unit according to claim 4, wherein the scheduler assigns the modulus multiply operation or modulus add operation to at least one of the one or more arithmetic logic units (Turan: pg. 1190 “The two basic operations performed by these RPAUs are addition and multiplication of the residue polynomials.”).
As per claim 6, Turan/Khedr further teaches The acceleration unit according to claim 4, wherein the scheduler assigns the number theoretic transform to at least one of the one or more number theoretic transform units (Turan: section 3.1.1).
As per claim 7, Turan/Khedr further teaches The acceleration unit according to claim 4, wherein for the inverse number theoretic transform, the scheduler decomposes the inverse number theoretic transform into a combination of a number theoretic transform and a modulus multiply operation, and assigns the number theoretic transform resulting from decomposition to at least one of the one or more number theoretic transform units, and assigns the modulus multiply operation resulting from decomposition to at least one of the one or more arithmetic logic units (Turan: pg. 1188 right column “The inverse NTT operation is similar to the forward NTT and requires an additional scaling of the resulting coefficients by n.sup.-1”).
As per claim 24, the claim is directed to a homomorphic encryption method that implements the same features as the acceleration unit of claim 1, and is therefore rejected for at least the same reasons therein.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Turan/Khedr in further view of Hennessy et al. (Computer Architecture A Quantitative Approach, hereinafter “Hennessy”).
As per claim 2, Turan/Khedr further teaches The acceleration unit according to claim 1.
However, while Turan discloses coprocessors with dedicated instruction set (section 4 paragraph), Turan does not explicitly disclose circuitry that processes the instructions. Thus, Turan does not teach further comprising: an instruction buffer adapted to receive a control signal, wherein the control signal comprises the to-be-executed homomorphic encryption instruction; an instruction fetch unit adapted to fetch the to-be-executed homomorphic encryption instruction from the instruction buffer; and an instruction decoding unit adapted to decode the to-be-executed homomorphic encryption instruction fetched by the instruction fetch unit and send to the scheduler the to-be-executed homomorphic encryption instruction that has been decoded.
Hennessey teaches further comprising: an instruction buffer adapted to receive a control signal, wherein the control signal comprises the to-be-executed homomorphic encryption instruction (Hennessey: Fig. 3.41; instruction cache corresponding to instruction buffer);
an instruction fetch unit adapted to fetch the to-be-executed homomorphic encryption instruction from the instruction buffer (Hennessey: Fig. 3.41 instruction fetch hardware);
and an instruction decoding unit adapted to decode the to-be-executed homomorphic encryption instruction fetched by the instruction fetch unit and send to the scheduler the to-be-executed homomorphic encryption instruction that has been decoded (Hennessey: Fig. 3.41; op decoders corresponding to instruction decoding unit).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the coprocessor of Turan with the instruction pipeline of Hennessey. One would have been motivated to combine these references because both references disclose processors executing instructions, and combining prior art elements according to known methods to yield predictable results (processing instructions to be performed).
As per claim 3, Turan/Khedr/Hennessey further teaches The acceleration unit according to claim 2, wherein: the control signal further comprises an access memory address (Hennessey: pg. C-5 “Send the program counter (PC) to memory and fetch the current instruction from memory.”);
and the acceleration unit further comprises: a memory interface for performing data transmission with a memory (Turan: pg. 1192 “The communication ports of AWS Shell are of two types. The first type is a 32-bit port for performing address mapped communication between applications and accelerators.”);
and a direct memory access unit adapted to receive an access memory address sent by the instruction buffer, and indicate the memory interface to fetch, according to the access memory address, data required by the to-be-executed homomorphic encryption instruction (Turan: pg. 1192 “The other type is a 512-bit port for Direct Memory Access (DMA) of the accelerators.”).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Turan/Khedr in further view of Riazi et al. (HEAX: An Architecture for Computing on Encrypted Data, hereinafter “Riazi”).
As per claim 8, Turan/Khedr further teaches The acceleration unit according to claim 7.
However, Turan/Khedr does not teach wherein for the modulus switch, the scheduler decomposes the modulus switch into a combination of a modulus add and a modulus multiply, and assigns the decomposition result to at least one of the one or more arithmetic logic units.
Riazi teaches wherein for the modulus switch, the scheduler decomposes the modulus switch into a combination of a modulus add and a modulus multiply, and assigns the decomposition result to at least one of the one or more arithmetic logic units (Riazi: pg. 1299 Algorithm 4, pg. 1302 “The MS module embeds multiplication and subtraction operations.” Of note the MS module comprising of modulus add of a negative number and modulus multiply operations).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the accelerator of HEAWS with the additional algorithms of HEAX. One would have been motivated to combine these references because both references disclose controlling accelerators for homomorphic processing, and the combination is obvious because it renders an improved system/method that allows for a more robust processing technique that allows for more useful applications within the field (by allowing the accelerator to process a wider variety of homomorphic operations).
As per claim 9, Turan/Khedr/Riazi further teaches The acceleration unit according to claim 8, wherein for the key switch, the scheduler decomposes the key switch into a combination of a number theoretic transform, an inverse number theoretic transform, a modulus multiply, and a modulus switch, and assigns the decomposition result to at least one of the one or more number theoretic transform units or at least one of the one or more arithmetic logic units (Riazi: pg. 1302, particularly the modules in Algorithm 5).
As per claim 10, Turan/Khedr/Riazi further teaches The acceleration unit according to claim 8, wherein for the rescale, the scheduler decomposes the rescale into a combination of a number theoretic transform, an inverse number theoretic transform, and a modulus switch, and assigns the decomposition result to at least one of the one or more number theoretic transform units or at least one of the one or more arithmetic logic units (Riazi: pg. 1299 Algorithm 4, “An important operation that is used during key switching and rescaling is called flooring”).
Claims 11, 13-14, 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Turan/Khedr in further view of Banerjee et al. (Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols (Extended Version), hereinafter “Banerjee”).
As per claim 11, Turan/Khedr further teaches The acceleration unit according to claim 1.
However, while Turan discloses memory access for NTT modules (pg. 1191 left column second paragraph) and a butterfly operation, Turan does not explicitly disclose how the memories store data, or the butterfly operation circuitry (pg. 1188 Algorithm 1). Thus, Turan does not teach wherein at least one of the one or more number theoretic transform units comprises: a first polynomial coefficient storage subunit; a second polynomial coefficient storage subunit; a twiddle factor storage subunit adapted to store a twiddle factor for the number theoretic transform; and a butterfly processing subunit adapted to perform first butterfly processing and second butterfly processing, wherein the first butterfly processing comprises: reading a first polynomial coefficient pair from the first polynomial coefficient storage subunit, obtaining a twiddle factor corresponding to the first polynomial coefficient pair from the twiddle factor storage subunit, obtaining a second polynomial coefficient pair based on the first polynomial coefficient pair and the twiddle factor, and writing the second polynomial coefficient pair into the second polynomial coefficient storage subunit; and the second butterfly processing comprises: reading a third polynomial coefficient pair from the second polynomial coefficient storage subunit, obtaining a twiddle factor corresponding to the third polynomial coefficient pair from the twiddle factor storage subunit, obtaining a fourth polynomial coefficient pair based on the third polynomial coefficient pair and the twiddle factor, and writing the fourth polynomial coefficient pair into the first polynomial coefficient storage subunit.
Banerjee teaches wherein at least one of the one or more number theoretic transform units comprises: a first polynomial coefficient storage subunit; a second polynomial coefficient storage subunit; a twiddle factor storage subunit adapted to store a twiddle factor for the number theoretic transform (Banerjee: Fig. 5(b); Constants RAM corresponding to twiddle factor storage);
and a butterfly processing subunit adapted to perform first butterfly processing and second butterfly processing, wherein the first butterfly processing comprises: reading a first polynomial coefficient pair from the first polynomial coefficient storage subunit, obtaining a twiddle factor corresponding to the first polynomial coefficient pair from the twiddle factor storage subunit, obtaining a second polynomial coefficient pair based on the first polynomial coefficient pair and the twiddle factor, and writing the second polynomial coefficient pair into the second polynomial coefficient storage subunit; and the second butterfly processing comprises: reading a third polynomial coefficient pair from the second polynomial coefficient storage subunit, obtaining a twiddle factor corresponding to the third polynomial coefficient pair from the twiddle factor storage subunit, obtaining a fourth polynomial coefficient pair based on the third polynomial coefficient pair and the twiddle factor, and writing the fourth polynomial coefficient pair into the first polynomial coefficient storage subunit (Banerjee: Fig. 7, pg. 10 first paragraph; wherein the memory banks alternate read and writes for each stage. The examiner notes the examples shown are for 8 polynomials, but Sapphire discloses it is applicable for 4 polynomials among others (pg. 10 second paragraph)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the memories of Turan with the memory banks of Banerjee. One would have been motivated to combine these references because both references disclose accelerators for homomorphic processing, and it is an area-efficient NTT memory architecture (Banerjee: section 3.3 first paragraph).
As per claim 13, Turan/Khedr/Banerjee further teaches The acceleration unit according to claim 11, wherein the first polynomial coefficient storage subunit and the second polynomial coefficient storage subunit each comprise a plurality of banks, each bank having a corresponding index, the first polynomial coefficient pair and the third polynomial coefficient pair are from banks with a same index, and the second polynomial coefficient pair and the fourth polynomial coefficient pair are from banks with a same index (Banerjee: Fig. 7, pg. 9 first paragraph “we create two memory banks – left and right – to store these two polynomials while allowing the butterfly inputs and outputs to ping-pong between them during each stage of the transform”).
As per claim 14, Turan/Khedr/Banerjee further teaches The acceleration unit according to claim 13, wherein M banks are comprised in the first polynomial coefficient storage subunit or the second polynomial coefficient storage subunit, and there are M/2 butterfly processing subunits; and for a single butterfly processing subunit, indexes of a pair of banks for the first polynomial coefficient pair are the same as indexes of a pair of banks for the third polynomial coefficient pair, and a difference between indexes of two banks in the pair of banks is M/2; and indexes of a pair of banks for the second polynomial coefficient pair are the same as indexes of a pair of banks for the fourth polynomial coefficient pair, and indexes of two banks in the pair of banks are adjacent (Banerjee: Fig. 6, pg. 9 both paragraphs).
As per claim 16, Turan/Khedr/Banerjee further teaches The acceleration unit according to claim 11, wherein the butterfly processing subunit comprises a first multi-path gating selector, a second multi-path gating selector, a third multi-path gating selector, a fourth multi-path gating selector, a first adder, a second adder, a first subtractor, a second subtractor, and a first multiplier (Banerjee Fig. 4).
As per claim 17, Turan/Khedr/Banerjee further teaches The acceleration unit according to claim 16, wherein a first coefficient of the first polynomial coefficient pair or third polynomial coefficient pair is input to a first input terminal of the first multi- path gating selector, and after being added to a second coefficient of the first polynomial coefficient pair or third polynomial coefficient pair by the first adder, is input to a second input terminal of the first multi-path gating selector; one of the first input terminal and the second input terminal is selected by using a first gating signal of the first multi-path gating selector to connect to an output terminal; the second coefficient is input to a second input terminal of the third multi-path gating selector, and after subtraction is performed on the second coefficient and the first coefficient by the first subtractor, is input to a first input terminal of the third multi-path gating selector; and one of the first input terminal and the second input terminal is selected by using a third gating signal of the third multi-path gating selector to connect to an output terminal, and is multiplied with a corresponding twiddle factor by the first multiplier to obtain a product signal (Banerjee: Fig. 4, section 3.2).
As per claim 18, Turan/Khedr/Banerjee further teaches The acceleration unit according to claim 17, wherein a signal output from an output terminal of the first multi-path gating selector is input to a first input terminal of the second multi-path gating selector, and after being added to the product signal by the second adder, is input to a second input terminal of the second multi-path gating selector; one of the first input terminal and the second input terminal is selected by using a second gating signal of the second multi-path gating selector to connect to an output terminal as one coefficient of the second polynomial coefficient pair or fourth polynomial coefficient pair; the product signal is input to a second input terminal of the fourth multi-path gating selector, and after subtraction is performed by the second subtractor on the product signal and the signal output from the first multi-path gating selector, is input to a first input terminal of the fourth multi-path gating selector; and one of the first input terminal and the second input terminal is selected by using a fourth gating signal of the fourth multi-path gating selector to connect to an output terminal as the other coefficient of the second polynomial coefficient pair or fourth polynomial coefficient pair (Banerjee: Fig. 4, section 3.2).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Turan/Khedr/Banerjee in further view of Riazi.
As per claim 12, Turan/Khedr/Banerjee further teach The acceleration unit according to claim 11.
However, while Turan discloses controlling the NTT unit (Fig. 3 description), Turan does not explicitly disclose a control unit within the NTT unit. Thus, Turan does not teach wherein at least one of the one or more number theoretic transform units further comprises: a control unit adapted to control running of the first polynomial coefficient storage subunit, the second polynomial coefficient storage subunit, the twiddle factor storage subunit, and the butterfly processing subunit.
Riazi teaches wherein at least one of the one or more number theoretic transform units further comprises: a control unit adapted to control running of the first polynomial coefficient storage subunit, the second polynomial coefficient storage subunit, the twiddle factor storage subunit, and the butterfly processing subunit (Riazi: Fig. 3 control unit).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the function of control signals of Turan with the control unit of Riazi. One would have been motivated to combine these references because both references disclose controlling accelerators for homomorphic processing, and combining prior art elements according to known methods to yield predictable results (controlling the data flow of NTT units).
Allowable Subject Matter
Claims 15, 19-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The state of reasons for the indication of allowable subject matter was discussed in non-final rejection mailed 07/02/2025.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182