DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination
1- A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/25/2026 has been entered.
Amendment
2- The Request for Continued Examination amendment has been entered and fully considered. Claims 1-7 and 11-23 remain pending in the application, where the independent claims have been amended. New claims 24-28 have been added.
Response to Arguments
3- Applicants’ amendments and their corresponding arguments with respect to the rejections of the pending claims under 35 USC §103 have been fully considered but are found not persuasive to overcome the prior art used in the previous office action, despite the fact that the amendments changed the scope of the invention, especially for the dependent claims.
4- Therefore, the amendments necessitated, upon further consideration, new grounds of rejection using additional teachings/suggestions from the same references of the previous office action. The new limitations are addressed in the rejections here under in more details.
Claim Rejection - 35 USC § 112
5- The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6- Claims 4, 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
As to claims 4 and 11, which read “further comprising a marker”, and “introducing a marker to the chip”, respectively, it is not clear whether the “a marker” is the same or an additional “marker” to the “a marker” in independent claim 1.
For examination purposes, all the options will be considered.
Claims 12-16 are similarly rejection by virtue of their dependence on claim 11.
Claim Rejections - 35 USC § 103
7- The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8- Claims 1-3, 5-7, 11-12, 17-24, 28 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ymeti et al. (PGPUB No. 2012/0214707, cited by Applicants)
As to claims 1, 11, 24, Ymeti teaches an interferometric chip and its method of making (Abstract and Figs. 1-12) comprising: a substrate (Fig. 1 for ex; substrate SUB) having one or more waveguide channels having a sensing layer thereon (¶ 84-89;WGS consists of the substrate, a core layer and cover layer having a measuring region MRG and a reference region RRG), the sensing layer adapted to bind or otherwise be selectively disturbed by one or more analytes, and to form an interferometer (¶ 84-89, 95-97; a reception REC is used to bind respective analytes for detection); a marker physically positioned at an end portion of the substrate to provide orientation during assembly or analysis, the marker selected from the group consisting of a colorant, a cut edge, an etching, an affixed label, and any combination thereof, and.
(Claim 11) introducing a marker to the chip (¶ 142, 149); (Claim 11) wherein the one or more waveguide channels are formed by an additive manufacturing technique and are not formed by etching, milling, machining, or carving and (Claim 24) wherein the additive manufacturing technique deposits the optical material in individual layers to form the one or more waveguide channels (¶ 84 for ex; waveguides are formed by stacking substrate, core and cover layer and choosing appropriately their indexes for a proper guiding of light).
Ymeti does not teach expressly wherein the one or more waveguide flow channels exhibiting a length of from about 1.0 mm to about 20 mm; a width of from about 0.1 mm to about 0.3 mm; and a depth of from about 0.0001 mm to about 0.0010 mm;
However, Ymeti does disclose adapting the dimensions of the structure according to the measurement applications and needs (¶ 84, 141). In addition, Ymeti insists on the use of such portable miniature measurement chip in microfluidic systems (¶ 60, 85, 138-144 for ex.), known for their millimeter to sub-micron dimensions (See references incorporated in ¶ 102 as evidence), which would suggest to one PHOSITA to adapt those dimensions, to match or overlap with the claimed dimension ranges, as a mere obvious practice since no specificities are presented with this claimed ranges, and since it has been held that where the general condition of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 23.
Therefore, it would have been obvious to one with ordinary skills in the art before the effective filing date of the instant application to use the apparatus of Ymeti so that wherein the one or more waveguide flow channels exhibiting a length of from about 1.0 mm to about 20 mm; a width of from about 0.1 mm to about 0.3 mm; and a depth of from about 0.0001 mm to about 0.0010 mm, with the advantage of effectively optimizing the optical measurements of the targeted analytes.
Moreover, Ymeti appears to teach/suggest:
(claims 2, 7) comprising at least two waveguide channels coated with the sensing layer and at least two waveguide channels not coated with the sensing layer; wherein the one or more waveguide channels each comprises a different sensing layer to allow the interferometric system comprising the chip to detect different analytes on each waveguide flow channel (¶ 59, 85-88, 102 for ex.)
(claim 3) further comprising a blocking coating (Figs. 1-2; 85-89 for ex.).
(claim 12) wherein the marker is selected from the group consisting of a colorant, a cut edge, an etching, an affixed label, and any combination thereof (¶ 142, 149).
(Claim 5) wherein the substrate comprises at least one optical material (¶ 84 for ex.; substrate optical cladding).
(Claim 6) wherein the sensing layer comprises one or more proteins, enzymes, aptamers, peptides, nucleic acids, carbohydrates, lipids, or monomers and polymers, or whole cell microorganisms suitable for binding one or more analytes (¶ 49, 85-87 for ex.)
(Claim 17) wherein the blocking coating comprises at least one blocking protein or protein-based blocking reagent (¶ 105 for ex).
(Claim 18) wherein a blocking coating is applied to at least one external surface of the substrate and to at least one reference waveguide channel (Abstract,¶ 13, 18-21, 98-100, 105 for ex.).
(Claim 19) wherein each waveguide channel comprises a different sensing layer, and the chip is configured to be used in an interferometric system adapted to independently detect different analytes in parallel (fig. 2, ¶ 11, 34, 102, 106, 110 for ex.).
(Claim 20) wherein the chip comprises at least one measurement waveguide channel and at least two reference waveguide channels arranged to enable correction of drift during interferometric detection (¶ 97, 110 for ex.)
(Claims 21, 27) further comprising a flow cell wafer positioned above the chip, wherein the flow cell comprises at least two detection microchannels, each adapted to communicate a test sample composition to one or more waveguide channels (Fig. 2, ¶ 97-101, 138-140 for ex); (Claim 27) further comprising a microfluidic system in fluid communication with the at least two detection microchannels (Fig. 10, ¶ 60, 138, 142-147 for ex), the microfluidic system comprising a mixing bladder, a microchannel section having an end in communication with the mixing bladder so as to form a closed loop (Fig. 10, ¶ 60, 142-147 for ex); and at least one micropump configured to circulate the test sample composition through the closed loop (¶ 60, 142-147 for ex).
(Claim 22) wherein each detection microchannel is formed by etching or molding a concave path into a surface of the flow cell wafer (Fig. 10, ¶ 59, 142).
(Claims 23, 28) wherein each detection microchannel is arranged in a serpentine flow pattern positioned above parallel waveguide channels (Fig. 10 A-B); (Claim 28) wherein the serpentine flow pattern is configured such that the test sample composition flows over the parallel waveguide channels without varying flow dynamics (Figs. 7, 10 for ex; the microfluidic passes the sample test above the core COR of the waveguide).
9- Claims 13-16 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ymeti in view of Paul et al. (PGPUB 20120263938)
As to claims 13-16, Ymeti teaches the interferometric chip method of claim 11.
Ymeti does not teach expressly wherein the step of coating the chip with a sensing layer is performed via a technique selected from the group consisting of micro-dripping, wick threading, inkjet printing, additive manufacturing, gravure printing, aerosol jet printing, spin-coating, dip- coating, silk screen application, felt marker application, and micro paintbrush application; (claim 14) wherein the micro-dripping utilizes one or more micro-pumps and, optionally, one or more nozzles in liquid communication with the one or more micro-pumps; (claim 15) further comprising the step of applying a waveguide channel coating to the one or more waveguide channels; (claim 16) wherein the waveguide channel coating comprises at least one metal oxide or metal dioxide.
However, in a similar field of endeavor of fabricating metal oxide films for biology and medicine applications, Paul teaches methods of producing porous metal oxide films using spray deposition (Abstract, ¶ 2 and Figs. 1-6) wherein the step of coating the chip with a sensing layer is performed via a technique selected from the group consisting of micro-dripping, wick threading, inkjet printing, additive manufacturing, gravure printing, aerosol jet printing, spin-coating, dip- coating, silk screen application, felt marker application, and micro paintbrush application; (claim 14) wherein the micro-dripping utilizes one or more micro-pumps and, optionally, one or more nozzles in liquid communication with the one or more micro-pumps; (claim 15) further comprising the step of applying a waveguide channel coating to the one or more waveguide channels; (claim 16) wherein the waveguide channel coating comprises at least one metal oxide or metal dioxide (¶3, 8-11, 26-27, 38-40).
Therefore, it would have been obvious to one with ordinary skills in the art before the effective filing date of the instant application to use the apparatus of Ymeti so that wherein the step of coating the chip with a sensing layer is performed via a technique selected from the group consisting of micro-dripping, wick threading, inkjet printing, additive manufacturing, gravure printing, aerosol jet printing, spin-coating, dip- coating, silk screen application, felt marker application, and micro paintbrush application; wherein the micro-dripping utilizes one or more micro-pumps and, optionally, one or more nozzles in liquid communication with the one or more micro-pumps; further comprising the step of applying a waveguide channel coating to the one or more waveguide channels; wherein the waveguide channel coating comprises at least one metal oxide or metal dioxide, with the advantage of effectively optimizing the manufacturing of the measuring system.
10- Claims 4, 25-26 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ymeti in view of Cottier (EP 2137514)
As to claims 4, 25, Ymeti teaches the interferometric chip of claim 1, further comprising a marker physically positioned at an end portion of the substrate to provide orientation during assembly or analysis, the marker selected from the group consisting of a colorant, a cut edge, an etching, an affixed label, and any combination thereof (¶ 142, 149); (Claim 25) wherein the substrate is substantially transparent (any material presents substantial transparency in given arbitrary ranges).
Ymeti does not teach expressly wherein the marker comprises a cut edge defining a diagonally cut corner positioned on one of four corners of the substrate; (Claim 25) wherein the chip is configured such that a light signal passing through the one or more waveguide channels is deflected by one or more gratings downward to a detector unit positioned beneath the chip; (Claim 26) wherein the one or more gratings comprise a plurality of entry gradients and a plurality of exit gradients.
However, in a similar field of endeavor of fabricating waveguide sensors for biology and medicine applications, Cottier teaches integrated optical sensors (Abstract, and Figs. 1-13) wherein the marker comprises a cut edge defining a diagonally cut corner positioned on one of four corners of the substrate (Figs. 1-4, 10-12 and ¶ 40; multiple diagonal cuts at the edge/corners of waveguide substrates 40s to waveguide/direct lights signals between 3/14 to regions 5); (Claims 25-26) wherein the chip is configured such that a light signal passing through the one or more waveguide channels is deflected by one or more gratings downward to a detector unit positioned beneath the chip (Figs. 1-3; lights 14/15 are deflected by gratings 6 downward towards detector 22); wherein the one or more gratings comprise a plurality of entry gradients and a plurality of exit gradients (¶ 17 ll. 44-46).
Therefore, it would have been obvious to one with ordinary skills in the art before the effective filing date of the instant application to use the apparatus of Ymeti in view of Cottier’s suggestions so that wherein the marker comprises a cut edge defining a diagonally cut corner positioned on one of four corners of the substrate, with the advantage of effectively coupling light between waveguides of different substrate regions in an efficient 3D configuration.
Conclusion
Helmers et al. “Performance of a compact, hybrid optical evanescent-wave sensor for chemical and biological applications”, APPLIED OPTICS @ Vol. 35, No. 4 @ 1 February 1996.
The examiner has pointed out particular references contained in the prior art of record in the body of this action for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. Applicant should consider the entire prior art as applicable as to the limitations of the claims. It is respectfully requested from the applicant, in preparing the response, to consider fully the entire references as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED K AMARA whose telephone number is (571)272-7847. The examiner can normally be reached on Monday-Friday: 9:00-17:00
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tarifur Chowdhury can be reached on (571-272-2287. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mohamed K AMARA/
Primary Examiner, Art Unit 2877
Prosecution Insights