DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/21/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 9-13, 15-21, 23 & 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Pub. 2020/0411445) in view of Cook et al. (US Pub. 2018/0012786).
Regarding claim 1, Chen teaches an embedded component stack, comprising:
a support substrate 102 (Fig. 4)
a patterned first conductive layer formed on the support substrate 102 (see the annotations in Fig. 4 below);
a first dielectric layer 300 disposed on the first conductive layer (Fig. 1 & Fig. 4);
a patterned second conductive layer 300 formed on the first dielectric layer 300 (see Fig. 4);
a first component embedded entirely within the first dielectric layer 300 and entirely between the patterned first conductive layer and the patterned second conductive layer (e.g. see Fig. 4 below);
a second dielectric layer 300 formed on the second conductive layer (Fig. 4 below); and
a second component disposed on or embedded entirely within the second dielectric layer 300 (see Fig. 3 below),
wherein the patterned first conductive layer has a planar surface, the patterned second conductive layer has a planar surface, and the embedded component stack forms a solid structure (see Fig. 3 below).
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Chen is silent on wherein each of the first component and the second component comprises a broken or separated tether extending from or attached to a side of each of the first component and the second component, respectively. However, Cook teaches wherein a first component 205/305 and a second component 205/305 comprises a broken or separated tether 240/240C extending from or attached to a side of each of the first component and the second component, respectively (Fig. 14-Fig. 16). Tethers are remnants of a manufacturing technique where chips (components) are transferred to a substrate/host device. This technique presents the advantages of enabling placement of semiconductor components to create a more advanced, efficient and flexible electronics. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Chen with the transfer and placement of semiconductor components, as taught by Cook, so as to obtain a more advanced, efficient and flexible semiconductor device.
Regarding claim 2, the combination of Chen and Cook teaches the embedded component stack of claim 1, wherein the first component is a self- supporting structure comprising a component substrate 202 (Chen’s Fig. 1 and Fig. 4).
Regarding claim 3, the combination of Chen and Cook teaches the embedded component stack of claim 1, wherein each of the first component and the second component is or comprises an integrated circuit that can be an unpackaged bare die (Chen’s Fig.1 & Fig. 4).
Regarding claim 5, the combination of Chen and Cook teaches the embedded component stack of claim 1, wherein the first component and the second component are one or more of: functionally similar, structurally similar, and substantially identical (Chen’s Fig. & Fig. 4).
Regarding claim 9, the combination of Chen and Cook teaches the embedded component stack of claim 1, wherein the second component is at least partially directly above or below the first component in the stack (Chen’s Fig. 4).
Regarding claim 10, the combination of Chen and Cook teaches the embedded component stack of claim 1, wherein no portion of the second component is directly above or below the first component in the stack (e.g. Chen’s Fig. 8).
Regarding claim 11, the combination of Chen and Cook teaches the embedded component stack of claim 1, comprising a patterned third conductive layer 400’ formed on the second dielectric layer 300, wherein the second component is embedded entirely within the second dielectric layer 300 and entirely between the patterned second conductive layer and the patterned third conductive layer (see Chen’s Fig. 4) .
Regarding claim 12, the combination of Chen and Cook teaches the embedded component stack of claim 11, comprising a third dielectric layer 300 formed on the patterned third conductive layer and a third component disposed on or embedded entirely within the third dielectric layer (see Chen’s Fig. 4 above).
Regarding claim 13, the combination of Chen and Cook teaches the embedded component stack of claim 1, wherein the first component is electrically connected to the patterned first conductive layer, the first component is electrically connected to the second conductive layer, or the first component is electrically connected to the patterned first conductive layer and to the patterned second conductive layer (see Chen’s Fig. 4 & Fig. 5-9).
Regarding claim 15, the combination of Chen and Cook teaches the embedded component stack of claim 1, comprising an electrically conductive via disposed in and passing entirely through the first dielectric layer (see Chen’s Fig. 4 above).
Regarding claim 16, the combination of Chen and Cook teaches the embedded component stack of claim 15, wherein (i) the first component is electrically connected to the electrically conductive via, (ii) the patterned first conductive layer is electrically connected to the electrically conductive via, (iii) the patterned second conductive layer is electrically connected to the electrically conductive via, or (iv) any combination of (i), (ii), (iii) (see Chen’s Fig. 4 above).
Regarding claim 17, the combination of Chen and Cook teaches the embedded component stack of claim 1, wherein the embedded component stack is an offset stack (e.g. Chen’s Fig. 9).
Regarding claim 18, the combination of Chen and Cook teaches the embedded component stack of claim 1, wherein the embedded component stack is an aligned stack (Chen’s Fig. 4).
Regarding claim 19, the combination of Chen and Cook teaches the embedded component stack of claim 1, comprising an electrically conductive via TSV disposed in and passing through the first component and electrically connected to the patterned first conductive layer and the patterned second conductive layer (Chen’s Fig. 12).
Regarding claim 20, the combination of Chen and Cook teaches the embedded component stack of claim 1, comprising a plurality of first components embedded entirely in the first dielectric layer 300, comprising a plurality of second components each disposed on or embedded in the second dielectric layer 300, or both (see Chen’s Fig. 6).
Regarding claim 23, the combination of Chen and Cook teaches the embedded component stack of claim 1 or claim 21, wherein (i) the patterned first conductive layer is a metal layer, (ii) the patterned second conductive layer is a metal layer, or (iii) both (i) and (ii) (Chen’s Fig. 4-9).
Regarding claim 25, the combination of Chen and Cook teaches the embedded component stack of claim 1, wherein the first component and the second component are each a transistor (Chen’s Para [0029 & 0034]).
Regarding claim 26, the combination of Chen and Cook teaches the embedded component stack of claim 25, wherein the first component and the second component are electrically connected in parallel (Chen’s Fig. 4).
Regarding claim 27, the combination of Chen and Cook teaches the embedded component stack of claim 1, wherein the first component and the second component are non-native to the substrate 12 (Chen’s Fig. 4).
Regarding claim 21, Chen teaches an embedded component stack, comprising:
a support substrate 102 (Fig. 4)
a patterned first conductive layer formed on the support substrate 102 (see Fig. 4 above);
a first dielectric layer 300 disposed on the patterned first conductive layer (Fig. 4 above);
a patterned second conductive layer 400’ formed on the first dielectric layer 300 (see Fig. 4 above);
a component (see first component in Fig. 4 above) embedded entirely within the first dielectric layer 300 and entirely between the patterned first conductive layer and the patterned second conductive layer 400’ (see Fig. 4 above),
wherein the patterned first conductive layer is directly electrically connected to the patterned second conductive layer (see Fig. 4 above),
wherein the patterned first conductive layer has a planar surface, the patterned second conductive layer has a planar surface, and the embedded component stack forms a solid structure (see Fig. 4 above).
Chen is silent on wherein each of the first component and the second component comprises a broken or separated tether extending from or attached to a side of each of the first component and the second component, respectively. However, Cook teaches wherein a first component 205/305 and a second component 205/305 comprises a broken or separated tether 240/240C extending from or attached to a side of each of the first component and the second component, respectively (Fig. 14-Fig. 16). Tethers are remnants of a manufacturing technique where chips (components) are transferred to a substrate/host device. This technique presents the advantages of enabling placement of semiconductor components to create a more advanced, efficient and flexible electronics. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Chen with the transfer and placement of semiconductor components, as taught by Cook, so as to obtain a more advanced, efficient and flexible semiconductor device.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen and Cook as applied to claim 1 above, and in further view of LEE et al. (US PUB. 2021/0098425).
Regarding claims 6, the combination of Chen and Cook is silent on the embedded component stack of claim 5, wherein the first component is rotated by 90 degrees with respect to the second components. However, LEE teaches wherein a first component (first chip) is rotated with respect to a second component (second chip); and wherein the rotation is 90 degrees or 180 degrees (see Para [0050]). This has the advantage of providing an alternative stacked layout/arrangement. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Chen & Cook with the rotated component layout, as taught by LEE, so as to provide an alternative stacked layout that could improve further scaling.
Claims 22 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Chen and Cook as applied to claim 1 above.
Regarding claim 22, Chen teaches the embedded component stack of claim 1 or claim 21, wherein the first component, the patterned first metal layer, the patterned second metal layer together have a thickness no greater 35 microns (e.g. Para [0040]). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 24, Chen teaches the embedded component stack of claim 1 or claim 21, wherein each of the first component and the second component has (i) a length, a width, or both a length and a width of no greater than 200 microns and (ii) a thickness no greater than 50 microns (e.g. Para [0040]). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Response to Arguments
Applicant's arguments filed 12/19/2025 have been fully considered but they are moot in light of new grounds of rejection.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818