Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. In response to the Office Action dated on 08/11/2025, applicant(s) amend the application as follow:
Claims amended: 1-6, 8-10, 13-19, 21-25 and 27-32
Claims canceled: none
Claims newly added: none
Claims pending: 1-32
Response to Arguments
2. Applicant's arguments with respect to claim(s) 1, 9, 17 and 25 have been considered but
are moot because the new ground of rejection does not rely on any reference applied in the
prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues “applicant respectfully submits that claim 1 is allowable under 35 U.S.C & 101 at least for satisfying Step 2A of the Office’s criteria for subject matter eligibility. See MPEP 2016…”
Examiner respectfully disagrees. As the claim amended, the determining step is an abstract idea which is mental process.
Applicant argues “… applicant respectfully submits that Lynch and Lundin, viewed individual or in combination, fail to teach or suggest “circuitry to decode coded data, wherein to decode of the coded data comprising an incomplete code by at least assigning an accelerator thread to each of the plurality of overlapping…”
Examiner respectfully disagreed with the above argument. Please see the below rejection.
Applicant argues “applicant respectfully submits the claims 10, 19 and 25 are allowable at least for the same reason including some of those discussed above in connection with claim 1…”
Examiner respectfully disagreed with the above argument Please see the above response in claim 1.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
3. Claims 1-32 are rejected under 35 U.S.C. 101 because the claimed
invention is directed to abstract idea without significantly more.
Step 1 (See MPEP 2106)
Claims 1-32 are directed to a processor, a computer-implemented method, non-
transitory computer readable storage medium and a system which belongs to a statutory
class.
Step 2A, Prong One:
Claims 1, 9, 17 and 25, "determines, a starting of a variable-length segment of the coded data comprising an incomplete code by at least assigning an accelerator thread to each of a plurality of overlapping portions of the coded data in parallel" which is a process
that, under its broadest reasonable interpretation, covers performance of the limitation by
Mental Process, but for the recitation of generic computer components. Nothing in the claim
element precludes the steps from practically being performed in the human mind. If a claim
limitation, under its broadest reasonable interpretation, covers performance of the limitation by
mental process, but for the recitation of generic computer components, then it falls within the
"Mental Processes" grouping of abstract ideas. Accordingly, the claim recites an abstract
idea.
The limitation is thus insignificant extra-solution activity. Limitations that the courts have
found not to be enough to qualify as "significantly more" when recited in a claim with a judicial
exception include: i. Adding the words "apply it" (or an equivalent) with the judicial exception, or
mere instructions to implement an abstract idea on a computer, e.g., a limitation indicating that a
particular function such as creating and maintaining electronic records is performed by
a computer, as discussed in Alice Corp., 134 S. Ct. at 2360, 110 USPQ2d at 1984 (see
MPEP § 2106.05(f)). 2106.05(g)-Insignificant Extra-Solution Activity.
Step 2A, Prong Two:
As to claims 1, 9, 17 and 25, claim 1 include processor, claim 17 includes processor
executes the instruction in non-transitory computer readable storage media, and system include
processor and memory which instruction is executed by processor" are the generic computer
components to decode the coded information. The user is performing the mental steps of
selecting inputted information for processing, by using the computer as a generic tool.
See MPEP 2106. 04. (a)(2).III.C. , 2106.05(a),2106.05(c)-(d) II.
“Decoding the incomplete code based, at least in part, on the determined starting location and combining coded data, corresponding to the incomplete code, obtained from two or more of the accelerator threads” which is performed by human.
The limitation is thus insignificant extra-solution activity. Limitations that the courts have
found not to be enough to qualify as "significantly more" when recited in a claim with a judicial
exception include: i. Adding the words "apply it" (or an equivalent) with the judicial exception, or
mere instructions to implement an abstract idea on a computer, e.g., a limitation indicating that a
particular function such as creating and maintaining electronic records is performed by
a computer, as discussed in Alice Corp., 134 S. Ct. at 2360, 110 USPQ2d at 1984 (see
MPEP § 2106.05(f)). 2106.05(g)--Insignificant Extra-Solution Activity.
As to claim 2, the limitation "the circuitry is further to store a value representing the position of the variable of the variable-length segment of data in the overlapping portions of the coded data" is an additional element which is insignificantly to amount significantly more and the circuitry is generic processor to decode data.
As to claims 3 and 32, the limitation "circuitry assign an accelerator thread to each of a plurality of overlapping positions of the coded data by at least; dividing the coded data into overlapping portions of the coded data, based at least in part, on a number of available accelerator threads" which is a computation algorithm to decode the overlapping data is a calculation algorithm and is abstract idea and the circuitry is generic processor to decode data.
As to claim 4, the limitation "circuitry decodes at least: creates a vector based, at least in part, on decoding the overlapping portions of the coded data" is an additional element to amount which is insignificant to amount significantly more and the circuitry is
generic processor to decode data.
As to claims 5, 11, 19 and 28, the limitation "the one or more circuits calculates a number of extra bits required to complete decoding of the overlapping portions of
the coded data based, at least in part, on incomplete codes in overlapping portions of the coded data" is a calculation algorithm which is abstract idea and the circuitry is generic processor to decode data.
As to claim 6, the limitation "the circuitry further decodes portion of data in
portion of the coded data, wherein the coded data overlaps" is an abstract idea which a human
can decode the coded portion and the circuitry is generic processor to decode data.
As to claim 7, the limitation "the circuitry to decode the coded data, at last decodes in full
some, but not all, of the overlapping portions of the coded data" is abstract idea which can be
perform by human and the circuitry is generic processor to decode data.
As to claim 8, the limitation "the circuitry further outputs element of the decoded data, decoded from the coded data" is additional element which is insignificant to amount significantly more and the circuitry is generic processor to decode data.
As to claims 10 and 18, the limitation “decoding the overlapping portion of the coded data in parallel comprise: calculating the starting locations of the variable-length segment of the overlapping portions of the coded data, wherein the overlapping portions of the coded data each begin different location of the coded data” is abstract idea which can perform by human and
the circuitry is generic processor to decode data.
As to claim 12, the limitations "creating one or more vectors based, at least in part on
decoding the overlapping portions of the coded data; and scanning the vectors to determine, at
least in part, starting locations in the coded data when decoding the data" are the additional
elements which are insignificant to amount significantly more.
As to claim 13, the limitation " decoding the sub-portion of the overlapping portions of the coded data, wherein sub-portion coded data overlap" is abstract idea which can performed by human and the circuitry is generic processor to decode data.
As to claim 14, the limitation “decoding the overlapping portions of the coded data in parallel comprises: copying a result from the decoding a first portion of the overlapping portion of the coded data; and applying the result to another portion of the overlapping portions of the coded data, wherein the another portion overlaps the first portion” are the processes which a human can perform.
As to claim 15, the limitation "outputting an element of decoded data, decoded from the
coded data, by combining at least two instructions to copy other identical element into copy
instructions" is an additional element which is insignificant to amount significantly more.
As to claim 16, the limitation "outputting elements of decided data, the decoded from the
coded data, in parallel, wherein the assigned thread accelerator thread of a graphic processing unit (GPU) outputs one element before outputting another element" is an additional element which is insignificant to amount significantly more.
As to claim 18, the limitation “the overlapping portion of the coded data each begin at a different location of the coded data” is only further what the overlapping portion of the coded data is and significantly amount significantly more.
As to claim 20, the limitation "calculate values based, at least in part, on decoding the
overlapping portion of the coded data; and store the values in an array" are the additional
elements which are insignificant to amount significantly more.
As to claim 21, the limitation "scan an array using composition operations to determine staring locations of the variable-length segment” is human activity which the process can performed by the human.
As to claim 22, the limitation “output elements of first decoded data, decoded from a first portion of the overlapping portion of the decoded data write the elements of the first decoded data to the storage medium to be copied by at least one assigned accelerator thread, wherein the elements of the first coded data are used to decode another portion of the overlapping portion of the coded data” is additional elements which is insignificantly more to amount significantly more.
As to claim 23, the limitation "outputting an element of decoded, wherein the
processor includes a plurality of accelerator threads, an at least one accelerator thread outputs one element by copying another element" is the tool to provide information to user which is insignificantly to amount significantly more.
As to claim 24, the limitation "the variable length segment of the coded data is Huffman
coded" is only further defined what variable length segment is.
As to claim 26, the limitation "decode the overlapping portions of the coded data,
wherein each portion stores begins with a different bit of the coded data and ends with the last
bit of the coded data" is an abstract idea and human being can perform the decoding the
overlapping portions.
As to claim 27, the limitation "store a value a position of the starting location of variable-length segment of data, in the overlapping portions of the coded data” is an additional element which is insignificant to amount significantly more.
The limitation “calculate a number of extra bits required to complete decoding any incomplete codes in overlapping portions of the data" is an calculation algorithm which provide solution to the decoding.
As to claim 29, the limitation "creating one or more vectors based, at least in part on
decoding the overlapping portion of the coded data, wherein the data was compressed, at least in part, with a Deflate algorithm" is an additional element which is insignificant to amount
significantly more.
As to claim 30, the limitation "scan one or more vectors stored in an array and based, at
least in part, on decoding overlapping portions of data, wherein the scanning is a prefix can” is seeking information for process” is an additional element which is insignificantly to amount significantly more.
As to claim 31, the limitation “decode a first code from a first portion of the overlapping portion of the coded data” is a human processor decoding the data.
The limitation “determine based at least in part on calculating an end point of the first code, that further decoding of the first portion of coded data would match another portion of coded data” which is a process that, under its broadest reasonable interpretation, covers performance of the limitation by Mental Process, but for the recitation of generic computer components. Nothing in the claim element precludes the steps from practically being performed in the human mind. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation by mental process, but for the recitation of generic computer components, then it falls within the "Mental Processes" grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
4. Claim(s) 1-4, 6-10, 12-13, 15-18, 21, 23, 25-26 and 30 is/are rejected under 35 U.S.C.
103 as being unpatentable over Lynch et al. (US. Patent No. 5,754,819 A) in view of Parker (Pub. No. US 2002/0069839 A1) in view of Lundin (Pub. No. US 2012/0008681 A1).
As to claim 1. (Currently Amended) Lynch discloses one or more processor comprising:
circuitry to decode coded data, wherein to decode the coded data, the circuitry at least: determines on a starting location of a variable-length segment of the coded data comprising in complete code by at least assign an accelerator thread to each of a plurality of overlapping portions of the coded data and causing the assigned accelerator threads to decode the overlapping portions of the coded data in parallel (each responsive to a unique combination of
said base and offset address bits and including overlapping between segments of said base
address bits and said offset address bits, for providing plurality of hash outputs signals which
are fully decoded and in which more than one of said fully decoded signals bit...) (claim 1). Lynch does not decode the incomplete coded based on, at least in part, on the determined starting location and combined coded data, corresponding to the incomplete, obtained from two or more of the accelerator thread. However, Park discloses decoding the incomplete coded based on, at least in part, on the determined starting location and combined coded data, corresponding to the incomplete, obtained from two or more of the accelerator thread (the metadata 112 may then used by the decompressor 114 to decompress the compressed data 106. For example, each block of the compressed data 106 …. Decompression in parallel—e.g., block A and blocks B… decompress in parallel—e.g., on segment per thread or co-processor…) (paragraph 0044). Lynch fails to disclose the decoding is incomplete code. However, Lundin discloses the decoding is incomplete code in parallel (FIG. 3B illustrates the parallel (and partially overlapping in time operations of primary and secondary decoders when the former has received an incomplete frames according to one embodiment. Similar to as described above in connection with error 318...) (Paragraph 0032-0033). This suggests the concept of decoding the incomplete code in parallel. Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the instant application to modify Lynch to include decoding the incomplete code in parallel as disclosed by Lundin in order to provide decoding incomplete code.
As to claim 2. (Currently Amended) Lynch discloses the one or more processors of claim
1, wherein the circuitry further stores a value representing starting positions of the overlapping portions of the coded data (claim 1).
As to claim 3. (Original) Parker discloses the one or more processors of claim 1, wherein
the circuit assigning an accelerator thread to each of a plurality of overlapping portion of the coded data by at least, dividing the coded data into the overlapping portion of the coded data, based on at least in part, on a number of available accelerator threads (the metadata 112 may then used by the decompressor 114 to decompress the compressed data 106. For example, each block of the compressed data 106 …. Decompression in parallel—e.g., block A and blocks B… decompress in parallel—e.g., on segment per thread or co-processor…) (paragraph 0044). Lynch fails to disclose the decoding is incomplete code. However, Lundin discloses the decoding is incomplete code in parallel (FIG. 3B illustrates the parallel (and partially overlapping in time operations of primary and secondary decoders when the former has received an incomplete frames according to one embodiment. Similar to as described above in connection with error 318...) (Paragraph 0032-0033).
As to claim 4. (Original) discloses the one or more processors of claim 1, wherein the
circuitry decodes the coded data, at least: creates a vector based, at least in part on decoding
the overlapping portions of the coded data (fig. 4, lines 43-67).
As to claim 6. (Original) Lynch discloses the one or more processors of claim 1, wherein
the circuitry is further to: decode a first sub portion of data in portions of the coded data, wherein
the coded data overlaps (col. 11, lines 31-36).
As to claim 7. (Original) Lynch discloses the processor of claim 1, wherein the circuit to
decode the coded data, at least: full decoding, some, but not all, of the overlapping portions of
the coded data (fully decode) (claim 1).
As to claim 8. (Original) Lynch discloses the one or more processors of claim 1, wherein
the circuitry is further to: output of elements of decoded data, decoded from the coded data, in
parallel (Parallel with output) (fig. 2).
Claim 9 is rejected under the same reason as to claim 1, Lynch discloses a computer-implemented method (method) (col. 4, lines 38).
As to claim 10. (Currently Amended) Lynch discloses the method of claim 9, wherein the
operations to decode the overlapping portions of the coded data in parallel comprising: decodes
overlapping portions of the coded data to calculate a location to start decoding the data, wherein
the overlapping portions each begin at a different location of the coded data (col. 6, lines 24-29).
Claim 11 is rejected under the same reason as to claim 5.
As to claim 12. (Original) Lynch discloses the method of claim 9, further comprising:
creating one or more vectors based, at least in part on decoding the overlapping portions of the
coded data; and scanning the vectors to determine, at least in part, starting locations in the data
when decoding the coded data (fig. 4).
As to claim 13. (Original) Lynch discloses the method of claim 9, wherein the operations
comprise: decoding a first code in portions of the coded data, wherein the portions of data
overlap (claim 1).
As to claim 15. (Original) Lynch discloses the method of claim 9, further comprising:
outputting an element of decoded data, decoded from the coded data, by combining at least two
instructions to copy other identical elements into one copy instruction (Parallel with output) (fig.
2).
As to claim 16. (Original) Lynch discloses the method of claim 9, further comprising:
outputting elements of decoded data, decoded from the coded data, in parallel, wherein one
thread of a graphics processing unit (GPU) outputs one element before outputting another
element (CPU) (col. 1, lines 44-52).
As to claim 17. (Currently Amended) Lynch discloses a non-transitory computer-
readable storage medium (memory) (col. 11, line 25) storing instructions that, when executed by a processor of a computing device, causes the computing device to at least: identify a starting location of a variable-length segment of coded data, based, at least in part, on operations to decode overlapping portions of coded data in parallel (claim 1).
As to claim 18. (Currently Amended) Lynch discloses the non-transitory computer-
readable storage medium of claim 17, further comprising further instructions that, when
executed by the processor, causes the computing device, to decode the decoded data, to at
least: decode decoding overlapping portions of the data to determine which overlapping portions
begin with a proper starting location to decode the coded data, wherein the overlapping portions
each begin at a different location of the coded data (claim 1).
As to claim 21. (Currently Amended ) Lynch discloses the non-transitory computer-
readable storage medium of claim 17, further comprising further instructions that, when
executed by the processor, causes the computing device to at least: scan scanning an array
using composition operations to determine, at least in part, starting locations when decoding the
coded data (scan before decode, claim 1).
As to claim 23. (Currently Amended) Lynch discloses the non-transitory computer-
readable storage medium of claim 17, further comprising further instructions that, when
executed by the processor, causes the computing device to at least: output outputting an
element of decoded data in parallel, wherein the processor includes threads, and at least one
thread outputs one element by copying another element (Parallel with output) (fig. 2).
Claim 25 is rejected under the same reason as to claim 1, Lynch discloses a system comprising memory for store instruction that, if execute, cause the system to (system 400) (col. 8, lines 1-2)
As to claim 26. (Original) Lynch discloses the system of claim 25, wherein the memory
stores further instructions, that if executed, further cause the system to: decode overlapping
portions of the data, wherein each portion begins with a different bit of the data and ends with
the last bit of the data (claim 1).
As to claim 30. (Original) Lynch disclose the system of claim 25, the memory stores
further instructions, that if executed, further cause the system to: scan on or more vectors stored
in an array and based, at least in part, on decoding overlapping portions of the data, wherein the
scanning is a prefix scan (scan before decode, claim 1).
Claim 32 is rejected under the same reason as to claim 3.
5. Claim(s) 24 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Lynch et al. (US. Patent No. 5,754,819 A) in view of Parker (Pub. No. US 2002/0069839 A1) and further in view of Lundin (Pub. No. US 2012/0008681 A1) and in view of Diamant et al. (Patent No. US 10.020.819 B1).
As to claim 24. (Currently Amended) Lynch and Lundin disclose the non-transitory
computer- readable storage medium of claim 17 excepting for wherein the variable-length
segment of coded data is Huffman coded. However, Diamant discloses wherein the variable-
length segment of coded data is Huffman coded (rather than sequentially decoding each code
word of a series of Huffman codewords, the disclosed embodiments speculatively and
concurrently (e.g., in parallel) detect code-word in each of a plurality of overlapping bit window S
within the series of Huffman codewords to thereby increase the decoding speed) (col. 1, lines
56-61). Therefore, would have been obvious to one ordinary skill in the art before the effective
filing date of the instant application to modify teaching of Lynch and Lundin to include wherein
the variable-length segment of coded data is Huffman coded as disclosed by Diamant in order
to decode segment.
As to claim 29. (Original) Lynch discloses the system of claim 25 excepting for wherein
the memory stores further instructions, that if executed, further cause the system to: creating
one or more vectors based, at least in part on decoding overlapping portions of the data,
wherein the data was compressed, at least in part, with a Deflate algorithm. However, Diamant
discloses wherein the memory stores further instructions, that if executed, further cause the
system to: creating one or more vectors based, at least in part on decoding overlapping portions
of the data, wherein the data was compressed, at least in part, with a Deflate algorithm (the data
that is Huffman-compress may comprise plaintext data. In other examples, the Deflate algorithm
may be used which combines the LZ compression process with the Huffman compression
process...) (col. 2, lines 23-32).
6. Claim(s) 5, 11, 19-20 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable
over Lynch et al. (US. Patent No. 5,754,819 A) in view of Parker (Pub. No. US 2002/0069839 A1) and further in view of Lundin (Pub. No. US 2012/0008681A1) and further in view of Ueno et al. (Pub. No. US 2010/0295713 A1).
As to claim 5, Lynch, Parker and Lundin disclose the one or more processors of claim 1
excepting for the one or more circuits is further to calculate number of extra bits required to
complete decoding of the overlapping portion of the coded data, at least in part on incomplete
codes in overlapping portion of the data. However, Ueno discloses the one or more circuits is
further to calculate number of extra bits required to complete decoding of the overlapping
portion of the coded data, at least in part on incomplete codes in overlapping portion of the data
(after the decoding of a binary symbols is completed, the coder information determining means
1209 and the number-of-additional-bits calculation means 1210 calculate the number of
additional bits...) (paragraph 0156). This suggests the claimed limitation the one or more
circuits is further to calculate number of extra bits required to complete decoding of the
overlapping portion of the coded data, at least in part on incomplete codes in overlapping
portion of the data. Therefore, it would have been obvious to one ordinary skill in the art before
the effective filing date of the instant applications to include the one or more circuits is further to
calculate number of extra bits required to complete decoding of the overlapping portion of the
coded data, at least in part on incomplete codes in overlapping portion of the data as disclosed
by Ueno in order to complete coding.
As to claim 11, Lynch, Parker and Lundin disclose the method of claim 9 excepting for
calculating a number of extra bits required to complete decoding the overlapping portions of the
coded data. However, Ueno discloses calculating a number of extra bits required to complete
decoding the overlapping portions of the coded data (after the decoding of a binary symbols is
completed, the coder information determining means 1209 and the number-of-additional-bits calculation means 1210 calculate the number of additional bits...) (paragraph 0156). This
suggests the claimed limitation calculating a number of extra bits required to complete decoding
the overlapping portions of the coded data. Therefore, it would have been obvious to one
ordinary skill in the art before the effective filing date of the instant applications to include
calculating a number of extra bits required to complete decoding the overlapping portions of the
coded data as disclosed by Ueno in order to complete coding.
Claim 19 is rejected under the same reason as top claim 11.
As to claim 28, Lynch, Parker and Lundin disclose the concept of claim 25 excepting the
memory stores further instructions, that if executed, further cause the system to: store a value
based on calculating a number of extra bits required from data next in sequence to complete
decoding any incomplete codes in the overlapping portions of the coded data. However, Ueno
discloses store a value based on calculating a number of extra bits required from data next in
sequence to complete decoding any incomplete codes in the overlapping portions of the coded
data (a memory for storing the latest five bytes of code data including from Code[n] is need)
(paragraph 0157). This suggested the concept of store a value based on calculating a number
of extra bits required from data next in sequence to complete decoding any incomplete codes in
the overlapping portions of the coded data. Therefore, it would have been obvious to one
ordinary skill in the art before the effective fling date of the instant applications Lynch and
Lundin store a value based on calculating a number of extra bits required from data next in
sequence to complete decoding any incomplete codes in the overlapping portions of the coded
data as disclosed by Ueno to archiving the decoded data.
7. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable
over Lynch et al. (US. Patent No. 5,754,819 A) in view of Parker (Pub. No. US 2002/0069839 A1) and further in view of Lundin (Pub. No. US 2012/0008681A1) and further in view of Florencio (Pub. No. US 2013/0101039 A1).
As to claim 14. (Amended) Lynch, Parker and Lundin discloses the method of claim 9 excepting for wherein decoding the overlapping portion of the decoded data in parallel comprises: copying a result from decoding a first portion of the overlapping portion of the decoded data; and applying the result to another portion of the overlapping portion of the coded data, wherein another portion overlapping the first portion. However, Florencio discloses copying a result from decoding a first portion of the overlapping portion of the decoded data; and applying the result to another portion of the overlapping portion of the coded data, wherein another portion overlapping the first portion (generating by decoding the encoded transformation and applying the decoded transformation to one or more previously decoded video frames, is copied into a portion of the region…) (claim 8). This concept can be used to perform the recited language copying a result from decoding a first portion of the overlapping portion of the decoded data; and applying the result to another portion of the overlapping portion of the coded data, wherein another portion overlapping the first portion. Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the instant application to include language copying a result from decoding a first portion of the overlapping portion of the decoded data; and applying the result to another portion of the overlapping portion of the coded data, wherein another portion overlapping the first portion as disclosed by Florencio in order to provide decoded data and reducing work load.
8. Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable
over Lynch et al. (US. Patent No. 5,754,819 A) in view of Parker (Pub. No. US 2002/0069839 A1) and further in view of Lundin (Pub. No. US 2012/0008681A1) and further in view of Koyabu et al. (Pub. No. US 2006/0093321 A1).
As to claim 22, Lynch discloses the non-transitory computer storage medium of claim 17 excepting for comprising further instructions that, when executed by the processor causes the computing device, to decode the coded data at least: outputting elements of first decode data, decoded from first portion of the overlapping portion of the decoded data write the elements of the first decoded data to the storage medium to be copied by at least one accelerator threads, wherein the elements of the first coded data are used to decode portion of the overlapping portions of the coded data. However, Koyabu discloses outputting elements of first decode data, decoded from first portion of the overlapping portion of the decoded data write the elements of the first decoded data to the storage medium to be copied by at least one accelerator threads, wherein the elements of the first coded data are used to decode portion of the overlapping portions of the coded data (decoder writes the decoding results of said first type of picture data in a first storage region of said reproduction memory and writes the decoded results of said second type of picture data in a second storage…) (claim 7). This suggest the claimed language outputting elements of first decode data, decoded from first portion of the overlapping portion of the decoded data write the elements of the first decoded data to the storage medium to be copied by at least one accelerator threads, wherein the elements of the first coded data are used to decode portion of the overlapping portions of the coded data as disclosed by Koyabu in order provide decoded data for further processing.
9. Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable
over Lynch et al. (US. Patent No. 5,754,819 A) in view of Parker (Pub. No. US 2002/0069839 A1) and further in view of Lundin (Pub. No. US 2012/0008681A1) and further in view of Ueno et al. (Pub. No. US 2010/0295713 A1) and further in view of Cronie et al. (Patent No. US 9,268,683 A1).
As to claim 27, Lynch, Parker and Lundin discloses the system of claim 25 wherein the memory stores further instructions, that if executed, further cause the system to store a value representing starting positions of overlapping portions of the data excepting for calculate a number of extra bits required to complete decoding any incomplete codes in overlapping portions of the data; create at least one vector based on a mapping of the values and calculations; and store the at least one vector in an array. However, Ueno discloses calculate a number of extra bits required to complete decoding any incomplete codes in overlapping portions of the data (after the decoding of a binary symbols is completed, the coder information determining means 1209 and the number-of-additional-bits calculation means 1210 calculate the number of additional bits...) (paragraph 0156). Furthermore, Cronie discloses create at least one vector based on a mapping of the values and calculations (creating sets of state vectors 563 which in combination…) (col. 9, lines 57-67); and store the at least one vector in an array (write data 565 that are stored in DRAM array 565…) (col. 9, lines 57-67). Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the instant application to modify teaching of Lynch to include calculate a number of extra bits required to complete decoding any incomplete codes in overlapping portions of the data; create at least one vector based on a mapping of the values and calculations; and store the at least one vector in an array as disclosed by Ueno and Cronie in order to calculate and decode information.
10. Claim(s) 20 and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable
over Lynch et al. (US. Patent No. 5,754,819 A) in view of Parker (Pub. No. US 2002/0069839 A1) and further in view of Lundin (Pub. No. US 2012/0008681A1) and further in view of Ueno et al. (Pub. No. US 2010/0295713 A1) and further in view of Sakuguchi (Pub. No. US 2007/0146173 A1).
As to claim 20, Lynch, Parker and Lundin discloses the non-transitory computer readable storage medium of claim excepting for comprising further instruction that, when executed by the processor, causes the computing device to at least: calculate values based, at least in part, on decoding the overlapping portion of the coded data; and store the value in the array. However, Ueno discloses calculate values based, at least in part, on decoding the overlapping portion of the coded data (after the decoding of a binary symbols is completed, the coder information determining means 1209 and the number-of-additional-bits calculation means 1210 calculate the number of additional bits...) (paragraph 0156). Sakaguchi discloses store the value in the array (… then the determined sub-string of characters is copied character by character starting with the head character and a result of copy process is concatenated to the already decoded…) (paragraph 0011). Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the instant application to include calculate values based, at least in part, on decoding the overlapping portion of the coded data; and store the value in the array as disclosed by Ueno and Sakaguchi in order to provide decode the coded data.
As to claim 31, Lynch, Parker and Lundin discloses wherein the memory stores further instructions, that if executed, further cause the system to: decoding a first code for portions of data excepting for wherein determine, calculating, based at least in part on the first code's end point, if subsequent decoding of one portion would match subsequent decoding of another portion; and copying subsequent decoding results from the other portion as results of the one portion. However, Ueno discloses determine, calculating, based at least in part on the first code's end point, if subsequent decoding of one portion would match subsequent decoding of another portion (after the decoding of a binary symbols is completed, the coder information determining means 1209 and the number-of-additional-bits calculation means 1210 calculate the number of additional bits...) (paragraph 0156). Sakaguchi discloses copying subsequent decoding results from the other portion as results of the one portion (… then the determined sub-string of characters is copied character by character starting with the head character and a result of copy process is concatenated to the already decoded…) (paragraph 0011). Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the instant application to include determine, calculating, based at least in part on the first code's end point, if subsequent decoding of one portion would match subsequent decoding of another portion; and copying subsequent decoding results from the other portion as results of the one portion as disclosed by Ueno and Sakaguchi in order to provide decode the coded data.
Conclusion
11. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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BAOQUOC N. TO
Examiner
Art Unit 2154
/BAOQUOC N TO/Primary Examiner, Art Unit 2154