DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s reply filed on 29 September 2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 28 August 2025 is in compliance with the provisions of 37 CFR 1.97 and has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 9-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (U.S. Pub. 2018/0102311) in view of Liu et al. (U.S. Pub. 2015/0028486).
Claim 1: Shih discloses a multi-chip package, in annotated Fig. 14 below and in paragraphs 27, 39, 43, 49, 56 and 60, comprising:
an interconnect bridge (101) having a first contact pad (204) and a second contact pad (204) thereon, the interconnect bridge (101) comprising a silicon die;
a conductive structure (lower portion of 510) laterally spaced spart from the interconnect bridge (101);
a second dielectric layer (202 and 550) on the interconnect bridge, the second dielectric layer (202 and 550) over the conductive structure (lower portion of 510);
a first via (204) in the second dielectric layer (202 and 550), the first via (204) coupled to the first contact pad; (204);
a second via (204) in the second dielectric layer (202 and 550), the second via (204) coupled to the second contact pad (204);
a third via (upper portion of 510) in the second dielectric layer (202 and 550), the third via (upper portion of 510) above and coupled to the conductive structure (lower portion of 510);
a third dielectric layer (912) on the second dielectric layer (202 and 550), the third dielectric layer (912) over the interconnect bridge (101) and over the conductive structure (lower portion of 510);
a first conductive trace (918) in the third dielectric layer (912), the first conductive trace (918) coupled to the first via (204);
a second conductive trace (918) in the third dielectric layer (912), the second conductive trace (918) coupled to the conductive structure (lower portion of 510);
a first die (11) over the third dielectric layer (912), the first die (11) over the interconnect bridge (101) and over the conductive structure (lower portion of 510), and the first die (101) coupled to the first conductive trace (912) and to the second conductive trace (912); and
a second die (12) over the interconnect bridge (101), the second die (12) coupled to the first die (11) by the interconnect bridge (101).
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Shih appears not to explicitly disclose wherein the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer,
wherein the third via is separate and distinct from the conductive structure, and
wherein the third via has a width at a bottom of the third via less than a width of the uppermost surface of the conducive structure.
Liu et al., however, in Figs. 3a-3i and 3o and in paragraphs 22, 32, 35, 36 and 39, discloses the conductive structure (104c and 104e) has an uppermost surface (upper side surface of 104c) above a bottommost surface (bottom surface of 105) of the interconnect bridge (105),
a first dielectric layer (104a in N-2), the first dielectric layer (104a in N-2) laterally adjacent the interconnect bridge (105), and the first dielectric layer (104a in N-2) laterally adjacent and in contact with the conductive structure (104c and 104e),
the second dielectric layer (104a in N-1) on the first dielectric layer (104a in N-2),
wherein the third via (103b) is separate and distinct from the conductive structure (104c and 104e), and
wherein the third via (103b) has a width at a bottom (bottom of 103b) of the third via (103b) less than a width of the uppermost surface (upper surface of 104c) of the conducive structure (104c and 104e) in order to route electrical signals to different parts of the package.
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It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih with the disclosure of Liu et al. to have made the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer,
wherein the third via is separate and distinct from the conductive structure, and
wherein the third via has a width at a bottom of the third via less than a width of the uppermost surface of the conducive structure in order to be able to route electrical signals to different parts of the package (paragraph 22 of Liu et al.).
Claim 2: Shih in view of Liu et al. discloses the multi-chip package of claim 1, and in Fig. 14, Shih further discloses wherein the first conductive trace is not coupled to the second conductive trace.
Claim 9: Shih discloses a system, in annotated Fig. 14 below and in paragraphs 27, 39, 43, 47, 49, 56 and 60, comprising:
a package substrate (10);
a first die (11) coupled to the package substrate (10); and
a second die (12) coupled to the package substrate (10), wherein the package substrate (10) comprises:
an interconnect bridge (101) having a first contact pad (204) and a second contact pad (204) thereon, the interconnect bridge (101) comprising a silicon die;
a conductive structure (lower portion of 510) laterally spaced apart from the interconnect bridge (101);
a second dielectric layer (202 and 550) on the interconnect bridge (101), the second dielectric layer (202 and 550) over the conductive structure (lower portion of 510);
a first via (204) in the second dielectric layer (202 and 550), the first via (204) coupled to the first contact pad (204);
a second via (204) in the second dielectric layer (202 and 550), the second via (204) coupled to the second contact pad (204);
a third via (upper portion of 510) in the second dielectric layer (202 and 550), the third via (upper portion of 510) above and coupled to the conductive structure (lower portion of 510);
a third dielectric layer (912) on the second dielectric layer (202 and 550), the third dielectric layer (912) over the interconnect bridge (101) and over the conductive structure (lower portion of 510);
a first conductive trace (918) in the third dielectric layer (912), the first conductive trace (918) coupled to the first via (204);
a second conductive trace (918) in the third dielectric layer (912), the second conductive trace (918) coupled to the conductive structure (lower portion of 510);
wherein the first die (11) is over the third dielectric layer (912), and the first die (11) is over the interconnect bridge (101) and over the conductive structure (lower portion of 510), the first die (11) coupled to the first conductive trace (918) and to the second conductive trace (918); and
wherein the second die (12) is over the interconnect bridge (101), the second die (12) coupled to the first die (11) by the interconnect bridge (101).
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Shih appears not to explicitly disclose a printed circuit board; and
the package substrate coupled to a printed circuit board.
Shih, however, in paragraph 52, discloses solder balls 801 may have a ball pitch that is equal to the ball pad pitch on a printed circuit board.
Therefore, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih to have a printed circuit board; and the package substrate coupled to a printed circuit board since the solder balls are spaced to have the same spacing as pads on a printed circuit board.
Further, it would also have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih to have a printed circuit board; and the package substrate coupled to a printed circuit board in order to connect the package substrate to other chips.
Shih also appears not to explicitly disclose wherein the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer,
wherein the third via is separate and distinct from the conductive structure, and
wherein the third via has a width at a bottom of the third via less than a width of the uppermost surface of the conducive structure.
Liu et al., however, in Figs. 3a-3i and 3o and in paragraphs 22, 32, 35, 36 and 39, discloses the conductive structure (104b, 104c and 104e) has an uppermost surface (upper side surface of 104b) above a bottommost surface (bottom surface of 105) of the interconnect bridge (105),
a first dielectric layer (104a in N-2), the first dielectric layer (104a in N-2) laterally adjacent the interconnect bridge (105), and the first dielectric layer (104a in N-2) laterally adjacent and in contact with the conductive structure (104b, 104c and 104e),
the second dielectric layer (104a in N-1) on the first dielectric layer (104a in N-2), and
wherein the third via (103b) is separate and distinct from the conductive structure (104a, 104c and 104e),
wherein the third via (103b) has a width at a bottom (bottom of 103b) of the third via (103b) less than a width of the uppermost surface (upper surface of 104c) of the conducive structure (104c and 104e) in order to route electrical signals to different parts of the package.
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It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih with the disclosure of Liu et al. to have made the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer,
wherein the third via is separate and distinct from the conductive structure, and
wherein the third via has a width at a bottom of the third via less than a width of the uppermost surface of the conducive structure in order to be able to route electrical signals to different parts of the package (paragraph 22 of Liu et al.).
Claim 10: Shih in view of Liu et al. discloses the system of claim 9, and in Fig. 14 and in paragraph 52, Shih further discloses wherein the package substrate (10) is coupled to the printed circuit board by a plurality of solder balls (810).
Claim 11: Shih in view of Liu et al. discloses the system of claim 10, and in Fig. 14, Shih further discloses wherein a first of the plurality of solder balls (810 below 101) is vertically beneath the interconnect bridge (101), and wherein a second of the plurality of solder balls (two rightmost 810) is vertically beneath the conductive structure (lower portion of 510).
Claim 12: Shih in view of Liu et al. discloses the system of claim 9, and in Fig. 14 and in paragraph 52, Shih further discloses wherein the package substrate is coupled to the printed circuit board by a plurality of solder bumps (810).
Claim 13: Shih in view of Liu et al. discloses the system of claim 12, and in Fig. 14, Shih further discloses wherein a first of the plurality of solder bumps (810 below 101) is vertically beneath the interconnect bridge, and wherein a second of the plurality of solder bumps (two rightmost 810) is vertically beneath the conductive structure.
Claim 14: Shih in view of Liu et al. discloses the system of claim 9, and in Fig. 14, Shih further discloses wherein the first conductive trace is not coupled to the second conductive trace.
Claim(s) 3-8 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Liu et al. as applied to claim 1 above, and further in view of Braunisch et al. (U.S. Pub. 2010/0327424).
Claim 3: Shih in view of Liu et al. disclose the multi-chip package of claim 1.
Shih in view of Liu et al. appears not to explicitly disclose a cavity laterally between the interconnect bridge and the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses a cavity (615) laterally between the interconnect bridge (540) and the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. with the disclosure of Braunisch et al. to have made a cavity laterally between the interconnect bridge and the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claim 4: Shih in view of Liu et al. disclose the multi-chip package of claim 1.
Shih in view of Liu et al. appears not to explicitly disclose wherein the interconnect bridge is laterally spaced apart from the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses the interconnect bridge (540) is laterally spaced apart from the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. with the disclosure of Braunisch et al. to have made the interconnect bridge is laterally spaced apart from the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claims 5 and 6: Shih in view of Liu et al. discloses the multi-chip package of claim 1.
Shih in view of Liu et al. appears not to explicitly disclose wherein the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die.
Braunisch et al., however, in paragraph 74, discloses the first die (1120) is a main die, and the second die (1130) is a secondary die; and
wherein the main die (1120) is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die (1130) is a die selected from the group consisting of a memory die and a transceiver die.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. with the disclosure of Braunisch et al. to have made the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die in order to for the package to have functionality.
Claims 7 and 8: Shih in view of Liu et al. disclose the multi-chip package of claim 1.
Shih in view of Liu et al. appears not to explicitly disclose wherein the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
wherein the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch.
Braunisch et al., however, in Fig. 6 and in paragraphs 22, 46, 48 and 51, discloses the first die (520) is coupled to the interconnect bridge (540) by a first plurality of conductive bumps (bumps between 520 and 540) having a first pitch (fine pitch), and wherein the first die further comprises a second plurality of conductive bumps (bumps between 520 and 610) having a second pitch (course pitch) greater than the first pitch; and
wherein the second die (530) is coupled to the interconnect bridge (540) by a third plurality of conductive bumps (bumps between 530 and 510) having a third pitch (fine pitch), and wherein the second die further comprises a fourth plurality of conductive bumps (bumps between 530 and 610) having a fourth pitch (course pitch) greater than the third pitch in order to increase communication bandwidth.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. with the disclosure of Braunisch et al. to have made the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch in order to increase communication bandwidth (paragraph 22).
Claim 15: Shih in view of Liu et al. discloses the system of claim 9.
Shih in view of Liu et al. appears not to explicitly disclose a cavity laterally between the interconnect bridge and the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses a cavity (615) laterally between the interconnect bridge (540) and the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. with the disclosure of Braunisch et al. to have made a cavity laterally between the interconnect bridge and the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claim 16: Shih in view of Liu et al. discloses the system of claim 9.
Shih in view of Liu et al. appears not to explicitly disclose wherein the interconnect bridge is laterally spaced apart from the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses the interconnect bridge (540) is laterally spaced apart from the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. with the disclosure of Braunisch et al. to have made the interconnect bridge is laterally spaced apart from the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claims 17 and 18: Shih in view of Liu et al. discloses the system of claim 9.
Shih in view of Liu et al. appears not to explicitly disclose wherein the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die.
Braunisch et al., however, in paragraph 74, discloses the first die (1120) is a main die, and the second die (1130) is a secondary die; and
wherein the main die (1120) is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die (1130) is a die selected from the group consisting of a memory die and a transceiver die.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. with the disclosure of Braunisch et al. to have made the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die in order to for the package to have functionality.
Claims 19 and 20: Shih in view of Liu et al. discloses the system of claim 9.
Shih in view of Liu et al. appears not to explicitly disclose wherein the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
wherein the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch.
Braunisch et al., however, in Fig. 6 and in paragraphs 22, 46, 48 and 51, discloses the first die (520) is coupled to the interconnect bridge (540) by a first plurality of conductive bumps (bumps between 520 and 540) having a first pitch (fine pitch), and wherein the first die further comprises a second plurality of conductive bumps (bumps between 520 and 610) having a second pitch (course pitch) greater than the first pitch; and
wherein the second die (530) is coupled to the interconnect bridge (540) by a third plurality of conductive bumps (bumps between 530 and 510) having a third pitch (fine pitch), and wherein the second die further comprises a fourth plurality of conductive bumps (bumps between 530 and 610) having a fourth pitch (course pitch) greater than the third pitch in order to increase communication bandwidth.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. with the disclosure of Braunisch et al. to have made the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch in order to increase communication bandwidth (paragraph 22).
Response to Arguments
Applicant's arguments filed 29 September 2025 have been fully considered but they are not persuasive.
Applicant contends Shih does not disclose the third via has a width at a bottom of the third via less than a width of the uppermost surface of the conducive structure.
Examiner notes that claims 1 and 9 are rejected over Shih in view of Liu et al., and Liu et al., in Figs. 3a-3i and 3o and in paragraphs 22 and 36, discloses wherein the third via (103b) has a width at a bottom (bottom of 103b) of the third via (103b) less than a width of the uppermost surface (upper surface of 104c) of the conducive structure (104c and 104e).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J.L/ Examiner, Art Unit 2815