DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s reply filed on 08 June 2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 20 April 2026 and 06 August 2026 are in compliance with the provisions of 37 CFR 1.97 and have been considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 17/716,928 in view of Shih (U.S. Pub. 2018/0102311).
Regarding claim 1, claim 1 of the copending application discloses the limitations of claim 1. Claim 1 of the copending application appears not to explicitly disclose the second dielectric layer on the interconnect bridge;
a first conductive trace in the third dielectric layer, the first conductive trace coupled to the first via;
a second conductive trace in the third dielectric layer, the second conductive trace coupled to the conductive structure; and
the first die coupled to the first conductive trance and the second conductive trace.
Shih, however, in Fig. 14 (see annotated Fig. 14 below), discloses a second dielectric layer (202 and 550) on the interconnect bridge (101);
a first conductive trace (918) in the third dielectric layer (912), the first conductive trace (918) coupled to the first via (204);
a second conductive trace (918) in the third dielectric layer (912), the second conductive trace (918) coupled to the conductive structure (lower portion of 510); and
the first die (101) coupled to the first conductive trace (912) and to the second conductive trace (912).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claim 1 of the copending application, as disclosed by Shih, to have made the second dielectric layer on the interconnect bridge;
a first conductive trace in the third dielectric layer, the first conductive trace coupled to the first via;
a second conductive trance in the third dielectric layer, the second conductive trance coupled to the conductive structure; and
the first die coupled to the first conductive trance and the second conductive trace in order to provide suitable electrical pathways within the device while protecting the surrounding elements.
Regarding claim 2, claim 1 of the copending application in view of Shih discloses the limitations of claim 2. Claim 1 of the copending application in view of Shih appears not to explicitly disclose the first conductive trace is not coupled to the second conductive trace.
Shih, however, in Fig. 14 (see annotated Fig. 14 below), further discloses wherein the first conductive trace is not coupled to the second conductive trace.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claim 1 of the copending application in view of Shih, as further disclosed by Shih, to have made the first conductive trace is not coupled to the second conductive trace in order to provide suitable electrical pathways within the device.
Regarding claims 3-8, claims 5-10, respectively, of the copending application disclose the limitations of claims 3-8 of the current application.
Regarding claim 9, claim 1 of the copending application discloses the limitations of claim 9. Claim 1 of the copending application appears not to explicitly disclose a printed circuit board; and
the package substrate coupled to a printed circuit board.
Shih, however, in paragraph 52, discloses solder balls 801 may have a ball pitch that is equal to the ball pad pitch on a printed circuit board.
Therefore, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 1 of the copending application, as disclosed by Shih, to have a printed circuit board; and the package substrate coupled to a printed circuit board since the solder balls are spaced to have the same spacing as pads on a printed circuit board.
Further, it would also have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 1 of the copending application, as disclosed by Shih, to have a printed circuit board; and the package substrate coupled to a printed circuit board in order to connect the package substrate to other chips.
Claim 1 of the copending application also appears not to explicitly disclose the first die coupled to the package substrate;
the second die coupled to the package substrate;
the second dielectric on the interconnect bridge;
a first conductive trace in the third dielectric layer, the first conductive trace coupled to the first via;
a second conductive trace in the third dielectric layer, the second conductive trace coupled to the conductive structure; and
the first die coupled to the first conductive trance and the second conductive trace.
Shih, however, in Fig. 14 (see annotated Fig. 14 below), further discloses the first die (11) coupled to a package substrate (10);
the second die (12) coupled to the package substrate (10);
the second dielectric layer (202 and 550) on the interconnect bridge (101);
a first conductive trace (918) in the third dielectric layer (912), the first conductive trace (918) coupled to the first via (204);
a second conductive trace (918) in the third dielectric layer (912), the second conductive trace (918) coupled to the conductive structure (lower portion of 510); and
the first die (11) coupled to the first conductive trace (912) and to the second conductive trace (912).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claim 1 of the copending application, as disclosed by Shih, to have made the first die coupled to the package substrate;
the second die coupled to the package substrate
the second dielectric on the interconnect bridge;
a first conductive trace in the third dielectric layer, the first conductive trace coupled to the first via;
a second conductive trace in the third dielectric layer, the second conductive trace coupled to the conductive structure; and
the first die coupled to the first conductive trance and the second conductive trace in order to provide suitable electrical pathways within the device while protecting the surrounding elements.
Regarding claim 10, claim 1 of the copending application in view of Shih discloses the limitations of claim 10. Claim 1 of the copending application in view of Shih appears not to explicitly disclose wherein the package substrate is coupled to the printed circuit board by a plurality of solder balls.
Shih, however, in Fig. 14 and in paragraph 52, further discloses the package substrate (10) is coupled to the printed circuit board by a plurality of solder balls (810).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claim 1 of the copending application in view of Shih, as further disclosed by Shih, to have made the package substrate is coupled to the printed circuit board by a plurality of solder balls in order to provide suitable electrical pathways within the device.
Regarding claim 11, claim 1 of the copending application in view of Shih discloses the limitations of claim 11. Claim 1 of the copending application in view of Shih appears not to explicitly disclose wherein a first of the plurality of solder balls is vertically beneath the interconnect bridge, and wherein a second of the plurality of solder balls is vertically beneath the conductive structure.
Shih, however, in Fig. 14, further discloses a first of the plurality of solder balls (810 below 101) is vertically beneath the interconnect bridge (101), and wherein a second of the plurality of solder balls (two rightmost 810) is vertically beneath the conductive structure (lower portion of 510).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claim 1 of the copending application in view of Shih, as further disclosed by Shih, to have made a first of the plurality of solder balls is vertically beneath the interconnect bridge, and wherein a second of the plurality of solder balls is vertically beneath the conductive structure in order to provide suitable electrical pathways within the device.
Regarding claim 12, claim 1 of the copending application in view of Shih discloses the limitations of claim 12. Claim 1 of the copending application in view of Shih appears not to explicitly disclose wherein the package substrate is coupled to the printed circuit board by a plurality of solder balls.
Shih, however, in Fig. 14 and in paragraph 52, further discloses the package substrate is coupled to the printed circuit board by a plurality of solder bumps (810).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claim 1 of the copending application in view of Shih, as further disclosed by Shih, to have made the package substrate is coupled to the printed circuit board by a plurality of solder balls in order to provide suitable electrical pathways within the device.
Regarding claim 13, claim 1 of the copending application in view of Shih discloses the limitations of claim 13. Claim 1 of the copending application in view of Shih appears not to explicitly disclose wherein a first of the plurality of solder bumps is vertically beneath the interconnect bridge, and wherein a second of the plurality of solder bumps is vertically beneath the conductive structure.
Shih, however, in Fig. 14, further discloses a first of the plurality of solder balls (810 below 101) is vertically beneath the interconnect bridge (101), and wherein a second of the plurality of solder balls (two rightmost 810) is vertically beneath the conductive structure (lower portion of 510).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claim 1 of the copending application in view of Shih, as further disclosed by Shih, to have made a first of the plurality of solder balls is vertically beneath the interconnect bridge, and wherein a second of the plurality of solder balls is vertically beneath the conductive structure in order to provide suitable electrical pathways within the device.
Regarding claim 14, claim 1 of the copending application in view of Shih discloses the limitations of claim 14. Claim 1 of the copending application in view of Shih appears not to explicitly disclose the first conductive trace is not coupled to the second conductive trace.
Shih, however, in Fig. 14 (see annotated Fig. 14 below), further discloses wherein the first conductive trace is not coupled to the second conductive trace.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claim 9 of the copending application in view of Shih, as further disclosed by Shih, to have made the first conductive trace is not coupled to the second conductive trace in order to provide suitable electrical pathways within the device.
Regarding claims 15-20, claims 5-10, respectively, of the copending application disclose the limitations of claims 15-20 of the current application.
This is a provisional nonstatutory double patenting rejection.
Claims 1-6 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of copending Application No. 18/128,964 in view of Shih (U.S. Pub. 2018/0102311) in view of Liu et al. (U.S. Pub. 2015/0028486) in view of Teh et al. (U.S. Pub. 2014/0093999).
Regarding claim 1, claims 1 and 2 of the copending application discloses the limitations of claim 1. Claims 1 and 2 of the copending application appears not to explicitly disclose a conductive structure laterally spaced apart from the interconnect bridge,
the second dielectric layer over the conductive structure;
the third via above and coupled to the conductive structure;
the third dielectric layer over the conductive structure;
the second conductive trace coupled to the conductive structure; and
the first die over the conductive structure, and the first die coupled to the first conductive trace and the second conductive trace.
Shih, however, in Fig. 14 (see annotated Fig. 14 below) discloses a conductive structure (lower portion of 510) laterally spaced spart from the interconnect bridge (101);
the second dielectric layer (202 and 550) over the conductive structure (lower portion of 510);
the third via (upper portion of 510) above and coupled to the conductive structure (lower portion of 510);
the third dielectric layer (912) over the conductive structure (lower portion of 510);
the second conductive trace (918) coupled to the conductive structure (lower portion of 510); and
the first die (11) over the conductive structure (lower portion of 510), and the first die (101) coupled to the first conductive trace (912) and to the second conductive trace (912).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claim 13 of the copending application, as disclosed by Shih, to have made a conductive structure laterally spaced apart from the interconnect bridge,
the second dielectric layer over the conductive structure;
the third via above and coupled to the conductive structure;
the third dielectric layer over the conductive structure;
the second conductive trace coupled to the conductive structure; and
the first die over the conductive structure, and the first die coupled to the first conductive trace and the second conductive trace in order to provide suitable electrical pathways within the device while protecting the surrounding elements.
Claims 1 and 2 of the copending application in view of Shih appears not to explicitly disclose wherein the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge;
the first dielectric layer laterally adjacent and in contact with the conductive structure; and
wherein the third via is separate and distinct from the conductive structure.
Liu et al., however, in Figs. 3a-3i and 3o, discloses the conductive structure (104c and 104e) has an uppermost surface (upper side surface of 104c) above a bottommost surface (bottom surface of 105) of the interconnect bridge (105),
the first dielectric layer (104a in N-2) laterally adjacent and in contact with the conductive structure (104c and 104e), and
wherein the third via (103b) is separate and distinct from the conductive structure (104c and 104e) in order to route electrical signals to different parts of the package.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claims 1 and 2 of the copending application in view of Shih, as disclosed by Liu et al., to have made the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge;
the first dielectric layer laterally adjacent and in contact with the conductive structure; and
wherein the third via is separate and distinct from the conductive structure in order to be able to route electrical signals to different parts of the package (paragraph 22 of Liu et al.).
Claims 1 and 2 of the copending application in view of Shih in view of Liu et al. appears not to explicitly disclose the third via is through the second dielectric layer.
Teh et al., however, in Fig. 1(L), discloses the third via (30) is through the second dielectric layer (20 and 34).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Teh et al. that is in the same field of endeavor with claims 1 and 2 of the copending application in view of Shih in view of Liu et al., before the effective filing date of the claimed invention in order to substitute the third via is through the second dielectric layer as disclosed by Teh et al. for the third via that is in the second dielectric layer disclosed by claims 1 and 2 of the copending application in view of Shih in view of Liu et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the third via is through the second dielectric layer disclosed by Teh et al. for the third via that is in the second dielectric layer disclosed by claims 1 and 2 of the copending application in view of Shih in view of Liu et al. would have yielded predictable results, namely providing a suitable electrical paths while protecting the surrounding elements. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 2, claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. discloses the limitations of claim 2. Claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose the first conductive trace is not coupled to the second conductive trace.
Shih, however, in Fig. 14 (see annotated Fig. 14 below), further discloses wherein the first conductive trace is not coupled to the second conductive trace.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al., as further disclosed by Shih, to have made the first conductive trace is not coupled to the second conductive trace in order to provide suitable electrical pathways within the device.
Regarding claim 3, claim 10, respectively, of the copending application disclose the limitations of claim 3 of the current application.
Regarding claim 4, claim 4, respectively, of the copending application disclose the limitations of claim 4 of the current application.
Regarding claims 5 and 6, claims 11 and 12, respectively, of the copending application disclose the limitations of claims 5 and 6 of the current application.
This is a provisional nonstatutory double patenting rejection.
Claims 7 and 8 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 2 of copending Application No. 18/128,964 in view of Shih in view of Liu et al. in view of Teh et al. in view of Braunisch et al. (U.S. Pub. 2010/0327424).
Regarding claims 7 and 8, claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. discloses the limitations of claims 7 and 8. Claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
wherein the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch.
Braunisch et al., however, in Fig. 6, discloses the first die (520) is coupled to the interconnect bridge (540) by a first plurality of conductive bumps (bumps between 520 and 540) having a first pitch (fine pitch), and wherein the first die further comprises a second plurality of conductive bumps (bumps between 520 and 610) having a second pitch (course pitch) greater than the first pitch; and
wherein the second die (530) is coupled to the interconnect bridge (540) by a third plurality of conductive bumps (bumps between 530 and 510) having a third pitch (fine pitch), and wherein the second die further comprises a fourth plurality of conductive bumps (bumps between 530 and 610) having a fourth pitch (course pitch) greater than the third pitch in order to increase communication bandwidth.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al., as disclosed by Braunisch et al., to have made the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch in order to increase communication bandwidth (paragraph 22).
This is a provisional nonstatutory double patenting rejection.
Claims 9-18 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of copending Application No. 18/128,964 in view of Shih (U.S. Pub. 2018/0102311) in view of Liu et al. (U.S. Pub. 2015/0028486) in view of Teh et al. (U.S. Pub. 2014/0093999).
Regarding claim 1, claims 1 and 2 of the copending application discloses the limitations of claim 1. Claims 1 and 2 of the copending application appears not to explicitly disclose a printed circuit board;
a package substrate coupled to a printed circuit board.
Shih, however, in paragraph 52, discloses solder balls 801 may have a ball pitch that is equal to the ball pad pitch on a printed circuit board.
Therefore, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 1 of the copending application, as disclosed by Shih, to have a printed circuit board; and the package substrate coupled to a printed circuit board since the solder balls are spaced to have the same spacing as pads on a printed circuit board.
Further, it would also have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify claim 1 of the copending application, as disclosed by Shih, to have a printed circuit board; and the package substrate couple to a printed circuit board in order to connect the package substrate to other chips.
Claims 1 and 2 of the copending application appears not to explicitly disclose the first die coupled to the package substrate;
the second die coupled to the package substrate;
a conductive structure laterally spaced apart from the interconnect bridge,
the second dielectric layer over the conductive structure;
the third via above and coupled to the conductive structure;
the third dielectric layer over the conductive structure;
the second conductive trace coupled to the conductive structure;
the first die over the conductive structure, the first die coupled to the first conductive trace and to the second conductive trace.
Shih, however, in Fig. 14 (see annotated Fig. 14 below) discloses the first die (11) coupled to the package substrate (10); and
the second die (12) coupled to the package substrate (10)
a conductive structure (lower portion of 510) laterally spaced spart from the interconnect bridge (101);
the second dielectric layer (202 and 550) over the conductive structure (lower portion of 510);
the third via (upper portion of 510) above and coupled to the conductive structure (lower portion of 510);
the third dielectric layer (912) over the conductive structure (lower portion of 510);
the second conductive trace (918) coupled to the conductive structure (lower portion of 510); and
the first die (11) over the conductive structure (lower portion of 510), and the first die (101) coupled to the first conductive trace (912) and to the second conductive trace (912).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claim 13 of the copending application, as disclosed by Shih, to have made the first die coupled to the package substrate;
the second die coupled to the package substrate;
a conductive structure laterally spaced apart from the interconnect bridge,
the second dielectric layer over the conductive structure;
the third via above and coupled to the conductive structure;
the third dielectric layer over the conductive structure;
the second conductive trace coupled to the conductive structure; and
the first die over the conductive structure, and the first die coupled to the first conductive trace and the second conductive trace in order to provide suitable electrical pathways within the device while protecting the surrounding elements.
Claims 1 and 2 of the copending application in view of Shih appears not to explicitly disclose wherein the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge;
the first dielectric layer laterally adjacent and in contact with the conductive structure; and
wherein the third via is separate and distinct from the conductive structure.
Liu et al., however, in Figs. 3a-3i and 3o, discloses the conductive structure (104c and 104e) has an uppermost surface (upper side surface of 104c) above a bottommost surface (bottom surface of 105) of the interconnect bridge (105),
the first dielectric layer (104a in N-2) laterally adjacent and in contact with the conductive structure (104c and 104e), and
wherein the third via (103b) is separate and distinct from the conductive structure (104c and 104e) in order to route electrical signals to different parts of the package.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claims 1 and 2 of the copending application in view of Shih, as disclosed by Liu et al., to have made the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge;
the first dielectric layer laterally adjacent and in contact with the conductive structure; and
wherein the third via is separate and distinct from the conductive structure in order to be able to route electrical signals to different parts of the package (paragraph 22 of Liu et al.).
Claims 1 and 2 of the copending application in view of Shih in view of Liu et al. appears not to explicitly disclose the third via is through the second dielectric layer.
Teh et al., however, in Fig. 1(L), discloses the third via (30) is through the second dielectric layer (20 and 34).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Teh et al. that is in the same field of endeavor with claims 1 and 2 of the copending application in view of Shih in view of Liu et al., before the effective filing date of the claimed invention in order to substitute the third via is through the second dielectric layer as disclosed by Teh et al. for the third via that is in the second dielectric layer disclosed by claims 1 and 2 of the copending application in view of Shih in view of Liu et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the third via is through the second dielectric layer disclosed by Teh et al. for the third via that is in the second dielectric layer disclosed by claims 1 and 2 of the copending application in view of Shih in view of Liu et al. would have yielded predictable results, namely providing a suitable electrical paths while protecting the surrounding elements. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 10, claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. discloses the limitations of claim 10. Claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein the package substrate is coupled to the printed circuit board by a plurality of solder balls.
Shih, however, in Fig. 14 and in paragraph 52, further discloses the package substrate (10) is coupled to the printed circuit board by a plurality of solder balls (810).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al., as further disclosed by Shih, to have made the package substrate is coupled to the printed circuit board by a plurality of solder balls in order to provide suitable electrical pathways within the device.
Regarding claim 11, claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. discloses the limitations of claim 11. Claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein a first of the plurality of solder balls is vertically beneath the interconnect bridge, and wherein a second of the plurality of solder balls is vertically beneath the conductive structure.
Shih, however, in Fig. 14, further discloses a first of the plurality of solder balls (810 below 101) is vertically beneath the interconnect bridge (101), and wherein a second of the plurality of solder balls (two rightmost 810) is vertically beneath the conductive structure (lower portion of 510).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al., as further disclosed by Shih, to have made a first of the plurality of solder balls is vertically beneath the interconnect bridge, and wherein a second of the plurality of solder balls is vertically beneath the conductive structure in order to provide suitable electrical pathways within the device.
Regarding claim 12, claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. discloses the limitations of claim 12. Claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein the package substrate is coupled to the printed circuit board by a plurality of solder balls.
Shih, however, in Fig. 14 and in paragraph 52, further discloses the package substrate is coupled to the printed circuit board by a plurality of solder bumps (810).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al., as further disclosed by Shih, to have made the package substrate is coupled to the printed circuit board by a plurality of solder balls in order to provide suitable electrical pathways within the device.
Regarding claim 13, claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. discloses the limitations of claim 13. Claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein a first of the plurality of solder bumps is vertically beneath the interconnect bridge, and wherein a second of the plurality of solder bumps is vertically beneath the conductive structure.
Shih, however, in Fig. 14, further discloses a first of the plurality of solder balls (810 below 101) is vertically beneath the interconnect bridge (101), and wherein a second of the plurality of solder balls (two rightmost 810) is vertically beneath the conductive structure (lower portion of 510).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al., as further disclosed by Shih, to have made a first of the plurality of solder balls is vertically beneath the interconnect bridge, and wherein a second of the plurality of solder balls is vertically beneath the conductive structure in order to provide suitable electrical pathways within the device.
Regarding claim 14, claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. discloses the limitations of claim 14. Claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose the first conductive trace is not coupled to the second conductive trace.
Shih, however, in Fig. 14 (see annotated Fig. 14 below), further discloses wherein the first conductive trace is not coupled to the second conductive trace.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al., as further disclosed by Shih, to have made the first conductive trace is not coupled to the second conductive trace in order to provide suitable electrical pathways within the device.
Regarding claim 15, claim 10, respectively, of the copending application disclose the limitations of claim 3 of the current application.
Regarding claim 16, claim 4, respectively, of the copending application disclose the limitations of claim 4 of the current application.
Regarding claims 17 and 18, claims 11 and 12, respectively, of the copending application disclose the limitations of claims 5 and 6 of the current application.
This is a provisional nonstatutory double patenting rejection.
Claims 19 and 20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of copending Application No. 18/128,964 in view of Shih in view of Liu et al. in view of Teh et al. in view of Braunisch et al. (U.S. Pub. 2010/0327424).
Regarding claims 19 and 20, claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. discloses the limitations of claims 19 and 20. Claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
wherein the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch.
Braunisch et al., however, in Fig. 6 and in paragraphs 22, 46, 48 and 51, discloses the first die (520) is coupled to the interconnect bridge (540) by a first plurality of conductive bumps (bumps between 520 and 540) having a first pitch (fine pitch), and wherein the first die further comprises a second plurality of conductive bumps (bumps between 520 and 610) having a second pitch (course pitch) greater than the first pitch; and
wherein the second die (530) is coupled to the interconnect bridge (540) by a third plurality of conductive bumps (bumps between 530 and 510) having a third pitch (fine pitch), and wherein the second die further comprises a fourth plurality of conductive bumps (bumps between 530 and 610) having a fourth pitch (course pitch) greater than the third pitch in order to increase communication bandwidth.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify claims 1 and 2 of the copending application in view of Shih in view of Liu et al. in view of Teh et al., as disclosed by Braunisch et al., to have made the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
wherein the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch in order to increase communication bandwidth (paragraph 22).
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 9-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (U.S. Pub. 2018/0102311) in view of Liu et al. (U.S. Pub. 2015/0028486) in view of Teh et al. (U.S. Pub. 2014/0093999).
Claim 1: Shih discloses a multi-chip package, in annotated Fig. 14 below and in paragraphs 27, 39, 43, 49, 56 and 60, comprising:
an interconnect bridge (101) having a first contact pad (204) and a second contact pad (204) thereon, the interconnect bridge (101) comprising a silicon die;
a conductive structure (lower portion of 510) laterally spaced spart from the interconnect bridge (101);
a second dielectric layer (202 and 550) on the interconnect bridge, the second dielectric layer (202 and 550) over the conductive structure (lower portion of 510);
a first via (204) in the second dielectric layer (202 and 550), the first via (204) coupled to the first contact pad; (204);
a second via (204) in the second dielectric layer (202 and 550), the second via (204) coupled to the second contact pad (204);
a third via (upper portion of 510) in the second dielectric layer (202 and 550), the third via (upper portion of 510) above and coupled to the conductive structure (lower portion of 510);
a third dielectric layer (912) on the second dielectric layer (202 and 550), the third dielectric layer (912) over the interconnect bridge (101) and over the conductive structure (lower portion of 510);
a first conductive trace (918) in the third dielectric layer (912), the first conductive trace (918) coupled to the first via (204);
a second conductive trace (918) in the third dielectric layer (912), the second conductive trace (918) coupled to the conductive structure (lower portion of 510);
a first die (11) over the third dielectric layer (912), the first die (11) over the interconnect bridge (101) and over the conductive structure (lower portion of 510), and the first die (101) coupled to the first conductive trace (912) and to the second conductive trace (912); and
a second die (12) over the interconnect bridge (101), the second die (12) coupled to the first die (11) by the interconnect bridge (101).
PNG
media_image1.png
548
1001
media_image1.png
Greyscale
Shih appears not to explicitly disclose wherein the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer, and
wherein the third via is separate and distinct from the conductive structure.
Liu et al., however, in Figs. 3a-3i and 3o and in paragraphs 22, 32, 35, 36 and 39, discloses the conductive structure (104c and 104e) has an uppermost surface (upper side surface of 104c) above a bottommost surface (bottom surface of 105) of the interconnect bridge (105),
a first dielectric layer (104a in N-2), the first dielectric layer (104a in N-2) laterally adjacent the interconnect bridge (105), and the first dielectric layer (104a in N-2) laterally adjacent and in contact with the conductive structure (104c and 104e),
the second dielectric layer (104a in N-1) on the first dielectric layer (104a in N-2), and
wherein the third via (103b) is separate and distinct from the conductive structure (104c and 104e) in order to route electrical signals to different parts of the package.
PNG
media_image2.png
381
776
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih with the disclosure of Liu et al. to have made the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer, and
wherein the third via is separate and distinct from the conductive structure in order to be able to route electrical signals to different parts of the package (paragraph 22 of Liu et al.).
Shih in view of Liu et al. appears not to explicitly disclose the first via is through the second dielectric layer;
the second via is through the second dielectric layer; and
the third via is through the second dielectric layer.
Teh et al., however, in Fig. 1(L) and in paragraphs 16 and 19, discloses the first via (right 42) is through the second dielectric layer (20 and 34);
the second via (left 42) is through the second dielectric layer (20 and 34); and
the third via (30) is through the second dielectric layer (20 and 34).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Teh et al. that is in the same field of endeavor with Shih in view of Liu et al., before the effective filing date of the claimed invention in order to substitute the first via is through the second dielectric layer; the second via is through the second dielectric layer; and the third via is through the second dielectric layer as disclosed by Teh et al. for the first via, the second via and the third via that are in the second dielectric layer disclosed by Shih in view of Liu et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the first via is through the second dielectric layer; the second via is through the second dielectric layer; and the third via is through the second dielectric layer disclosed by Teh et al. for the first via, the second via and the third via that are in the second dielectric layer disclosed by Shih in view of Liu et al. would have yielded predictable results, namely providing a suitable electrical paths while protecting the surrounding elements. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 2: Shih in view of Liu et al. in view of Teh et al. discloses the multi-chip package of claim 1, and in Fig. 14, Shih further discloses wherein the first conductive trace is not coupled to the second conductive trace.
Claim 9: Shih discloses a system, in annotated Fig. 14 below and in paragraphs 27, 39, 43, 47, 49, 56 and 60, comprising:
a package substrate (10);
a first die (11) coupled to the package substrate (10); and
a second die (12) coupled to the package substrate (10), wherein the package substrate (10) comprises:
an interconnect bridge (101) having a first contact pad (204) and a second contact pad (204) thereon, the interconnect bridge (101) comprising a silicon die;
a conductive structure (lower portion of 510) laterally spaced apart from the interconnect bridge (101);
a second dielectric layer (202 and 550) on the interconnect bridge (101), the second dielectric layer (202 and 550) over the conductive structure (lower portion of 510);
a first via (204) in the second dielectric layer (202 and 550), the first via (204) coupled to the first contact pad (204);
a second via (204) in the second dielectric layer (202 and 550), the second via (204) coupled to the second contact pad (204);
a third via (upper portion of 510) in the second dielectric layer (202 and 550), the third via (upper portion of 510) above and coupled to the conductive structure (lower portion of 510);
a third dielectric layer (912) on the second dielectric layer (202 and 550), the third dielectric layer (912) over the interconnect bridge (101) and over the conductive structure (lower portion of 510);
a first conductive trace (918) in the third dielectric layer (912), the first conductive trace (918) coupled to the first via (204);
a second conductive trace (918) in the third dielectric layer (912), the second conductive trace (918) coupled to the conductive structure (lower portion of 510);
wherein the first die (11) is over the third dielectric layer (912), and the first die (11) is over the interconnect bridge (101) and over the conductive structure (lower portion of 510), the first die (11) coupled to the first conductive trace (918) and to the second conductive trace (918); and
wherein the second die (12) is over the interconnect bridge (101), the second die (12) coupled to the first die (11) by the interconnect bridge (101).
PNG
media_image1.png
548
1001
media_image1.png
Greyscale
Shih appears not to explicitly disclose a printed circuit board; and
the package substrate coupled to a printed circuit board.
Shih, however, in paragraph 52, discloses solder balls 801 may have a ball pitch that is equal to the ball pad pitch on a printed circuit board.
Therefore, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih to have a printed circuit board; and the package substrate coupled to a printed circuit board since the solder balls are spaced to have the same spacing as pads on a printed circuit board.
Further, it would also have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih to have a printed circuit board; and the package substrate coupled to a printed circuit board in order to connect the package substrate to other chips.
Shih also appears not to explicitly disclose wherein the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer, and
wherein the third via is separate and distinct from the conductive structure.
Liu et al., however, in Figs. 3a-3i and 3o and in paragraphs 22, 32, 35, 36 and 39, discloses the conductive structure (104b, 104c and 104e) has an uppermost surface (upper side surface of 104b) above a bottommost surface (bottom surface of 105) of the interconnect bridge (105),
a first dielectric layer (104a in N-2), the first dielectric layer (104a in N-2) laterally adjacent the interconnect bridge (105), and the first dielectric layer (104a in N-2) laterally adjacent and in contact with the conductive structure (104b, 104c and 104e),
the second dielectric layer (104a in N-1) on the first dielectric layer (104a in N-2), and
wherein the third via (103b) is separate and distinct from the conductive structure (104a, 104c and 104e) in order to route electrical signals to different parts of the package.
PNG
media_image2.png
381
776
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih with the disclosure of Liu et al. to have made the conductive structure has an uppermost surface above a bottommost surface of the interconnect bridge,
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure,
the second dielectric layer on the first dielectric layer, and
wherein the third via is separate and distinct from the conductive structure in order to be able to route electrical signals to different parts of the package (paragraph 22 of Liu et al.).
Shih in view of Liu et al. appears not to explicitly disclose the first via is through the second dielectric layer;
the second via is through the second dielectric layer; and
the third via is through the second dielectric layer.
Teh et al., however, in Fig. 1(L) and in paragraphs 16 and 19, discloses the first via (right 42) is through the second dielectric layer (20 and 34);
the second via (left 42) is through the second dielectric layer (20 and 34); and
the third via (30) is through the second dielectric layer (20 and 34).
Accordingly, it would have been obvious to one of ordinary skill in the art to substitute the disclosure of Teh et al. that is in the same field of endeavor with Shih in view of Liu et al., before the effective filing date of the claimed invention in order to substitute the first via is through the second dielectric layer; the second via is through the second dielectric layer; and the third via is through the second dielectric layer as disclosed by Teh et al. for the first via, the second via and the third via that are in the second dielectric layer disclosed by Shih in view of Liu et al. The substituted components were known in the art, one of ordinary skill could have substituted the elements, and the simple substitution of the first via is through the second dielectric layer; the second via is through the second dielectric layer; and the third via is through the second dielectric layer disclosed by Teh et al. for the first via, the second via and the third via that are in the second dielectric layer disclosed by Shih in view of Liu et al. would have yielded predictable results, namely providing a suitable electrical paths while protecting the surrounding elements. (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 10: Shih in view of Liu et al. in view of Teh et al. discloses the system of claim 9, and in Fig. 14 and in paragraph 52, Shih further discloses wherein the package substrate (10) is coupled to the printed circuit board by a plurality of solder balls (810).
Claim 11: Shih in view of Liu et al. in view of Teh et al. discloses the system of claim 10, and in Fig. 14, Shih further discloses wherein a first of the plurality of solder balls (810 below 101) is vertically beneath the interconnect bridge (101), and wherein a second of the plurality of solder balls (two rightmost 810) is vertically beneath the conductive structure (lower portion of 510).
Claim 12: Shih in view of Liu et al. in view of Teh et al. discloses the system of claim 9, and in Fig. 14 and in paragraph 52, Shih further discloses wherein the package substrate is coupled to the printed circuit board by a plurality of solder bumps (810).
Claim 13: Shih in view of Liu et al. in view of Teh et al. discloses the system of claim 12, and in Fig. 14, Shih further discloses wherein a first of the plurality of solder bumps (810 below 101) is vertically beneath the interconnect bridge, and wherein a second of the plurality of solder bumps (two rightmost 810) is vertically beneath the conductive structure.
Claim 14: Shih in view of Liu et al. in view of Teh et al. discloses the system of claim 9, and in Fig. 14, Shih further discloses wherein the first conductive trace is not coupled to the second conductive trace.
Claim(s) 3-8 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih in view of Liu et al. in view of Teh et al. as applied to claim 1 above, and further in view of Braunisch et al. (U.S. Pub. 2010/0327424).
Claim 3: Shih in view of Liu et al. in view of Teh et al. disclose the multi-chip package of claim 1.
Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose a cavity laterally between the interconnect bridge and the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses a cavity (615) laterally between the interconnect bridge (540) and the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. in view of Teh et al. with the disclosure of Braunisch et al. to have made a cavity laterally between the interconnect bridge and the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claim 4: Shih in view of Liu et al. in view of Teh et al. disclose the multi-chip package of claim 1.
Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein the interconnect bridge is laterally spaced apart from the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses the interconnect bridge (540) is laterally spaced apart from the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. in view of Teh et al. with the disclosure of Braunisch et al. to have made the interconnect bridge is laterally spaced apart from the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claims 5 and 6: Shih in view of Liu et al. in view of Teh et al. discloses the multi-chip package of claim 1.
Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die.
Braunisch et al., however, in paragraph 74, discloses the first die (1120) is a main die, and the second die (1130) is a secondary die; and
wherein the main die (1120) is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die (1130) is a die selected from the group consisting of a memory die and a transceiver die.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. in view of Teh et al. with the disclosure of Braunisch et al. to have made the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die in order to for the package to have functionality.
Claims 7 and 8: Shih in view of Liu et al. in view of Teh et al. disclose the multi-chip package of claim 1.
Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
wherein the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch.
Braunisch et al., however, in Fig. 6 and in paragraphs 22, 46, 48 and 51, discloses the first die (520) is coupled to the interconnect bridge (540) by a first plurality of conductive bumps (bumps between 520 and 540) having a first pitch (fine pitch), and wherein the first die further comprises a second plurality of conductive bumps (bumps between 520 and 610) having a second pitch (course pitch) greater than the first pitch; and
wherein the second die (530) is coupled to the interconnect bridge (540) by a third plurality of conductive bumps (bumps between 530 and 510) having a third pitch (fine pitch), and wherein the second die further comprises a fourth plurality of conductive bumps (bumps between 530 and 610) having a fourth pitch (course pitch) greater than the third pitch in order to increase communication bandwidth.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. in view of Teh et al. with the disclosure of Braunisch et al. to have made the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch in order to increase communication bandwidth (paragraph 22).
Claim 15: Shih in view of Liu et al. in view of Teh et al. discloses the system of claim 9.
Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose a cavity laterally between the interconnect bridge and the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses a cavity (615) laterally between the interconnect bridge (540) and the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. in view of Teh et al. with the disclosure of Braunisch et al. to have made a cavity laterally between the interconnect bridge and the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claim 16: Shih in view of Liu et al. in view of Teh et al. discloses the system of claim 9.
Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein the interconnect bridge is laterally spaced apart from the first dielectric layer.
Braunisch et al., however, in Fig. 6 and in paragraph 49 and 62, discloses the interconnect bridge (540) is laterally spaced apart from the first dielectric layer (610) in order to prevent underfillings of dies from being disturbed.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. in view of Teh et al. with the disclosure of Braunisch et al. to have made the interconnect bridge is laterally spaced apart from the first dielectric layer in order to prevent underfillings of dies from being disturbed (paragraph 49 of Braunisch).
Claims 17 and 18: Shih in view of Liu et al. in view of Teh et al. discloses the system of claim 9.
Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die.
Braunisch et al., however, in paragraph 74, discloses the first die (1120) is a main die, and the second die (1130) is a secondary die; and
wherein the main die (1120) is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die (1130) is a die selected from the group consisting of a memory die and a transceiver die.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. in view of Teh et al. with the disclosure of Braunisch et al. to have made the first die is a main die, and the second die is a secondary die; and
wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die in order to for the package to have functionality.
Claims 19 and 20: Shih in view of Liu et al. in view of Teh et al. discloses the system of claim 9.
Shih in view of Liu et al. in view of Teh et al. appears not to explicitly disclose wherein the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
wherein the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch.
Braunisch et al., however, in Fig. 6 and in paragraphs 22, 46, 48 and 51, discloses the first die (520) is coupled to the interconnect bridge (540) by a first plurality of conductive bumps (bumps between 520 and 540) having a first pitch (fine pitch), and wherein the first die further comprises a second plurality of conductive bumps (bumps between 520 and 610) having a second pitch (course pitch) greater than the first pitch; and
wherein the second die (530) is coupled to the interconnect bridge (540) by a third plurality of conductive bumps (bumps between 530 and 510) having a third pitch (fine pitch), and wherein the second die further comprises a fourth plurality of conductive bumps (bumps between 530 and 610) having a fourth pitch (course pitch) greater than the third pitch in order to increase communication bandwidth.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Shih in view of Liu et al. in view of Teh et al. with the disclosure of Braunisch et al. to have made the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch; and
the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch in order to increase communication bandwidth (paragraph 22).
Response to Arguments
Applicant's arguments filed 08 June 2026 have been fully considered but they are not persuasive.
Applicant contends Shih does not disclose the first via coupled to the first contact pad and the second via coupled to the second contact pad.
Examiner notes that Shih, in Fig. 14, discloses the first via coupled to the first contact pad and the second via coupled to the second contact pad (see annotated Fig. 14 above).
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
Prosecution Insights