DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Remarks
This Office Action is responsive to the PTAB decision of 27 August 2025. In that decision the rejection of claims 8, 24, and 31 were affirmed and the rejection of claims 1-7, 9-23, and 25-30 was reversed.
New grounds of rejection under 35 USC 112(a) (enablement) and 35 USC 103 are set forth in the Office Action. The TC director has signed this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
The Wands factors, see MPEP § 2164.01(a) that support this conclusion are the breadth of the claims, level of predictability in the art, the amount of direction provided by the inventor and quantity of experimentation needed to make or use the invention based on the content of the disclosure.
Independent claim 1 recites, in its entirety, “a processor, comprising: one or more circuits to cause one or more different cache eviction policies to be used for different portions of one or more neural networks”. Independent claim 9 recites, in its entirety, “A system, comprising: a processor to cause one or more different cache eviction policies to be used for different portions of one or more neural networks”.
With respect to the breadth of a claim, the relevant concern is whether the scope of enablement provided to one skilled in the art by the disclosure is commensurate with the scope of protection sought by the claims, see MPEP § 2164.08.
In both claims the processor is the only element used to achieve the desired result. The claims as presented do not offer details of the processor or its circuits, and do not specify how they are configured or arranged to achieve said result. The claims limitations appear to cover every conceivable processor and/or processor circuit that can achieve the desired result. As such, claims 1 and 9 are unpatentable under, 35 U.S.C. § 112, first paragraph, for lack of an enabling disclosure commensurate with the scope of the claims.
With respect to the amount of direction provided by the inventor, the examiner points to paragraphs [0059] - [0062], [0064], [100] and figure 1 (elements 112a and 112b), cited as support for the invention.
Paragraphs [0059] recites “policies are referred to as cache eviction policies or cache replacement policies, and can include techniques potentially including but not limited to least-recently used ("LRU"), least-frequently used ("LFU"), adaptive replacement cache ("ARC"), dynamic insertion policy ("DIP")”, which broadly discusses the processor cache eviction/replacement policies. However, it does not discuss “one or more different cache eviction policies to be used for different portions of one or more neural networks”.
Paragraph [0060] recites “processor100 includes circuitry and/or instructions to implement a plurality of cache policies. For example, in at least one embodiment, processor100 includes circuitry and/or instructions for implementing an LRU policy and an ARC policy, and circuitry and/or instructions for switching between these policies”, which broadly discusses the processor switching between cache eviction/replacement policies. However, it does not discuss “one or more different cache eviction policies to be used for different portions of one or more neural networks”.
Paragraph [0061] recites “an application114 comprises executable instructions to be executed by processor100, in order to cause a computing system comprising said processor100 to perform one or more computing functions” which broadly discusses a processor executing an application with a function using a neural network. However, it does not discuss “one or more different cache eviction policies to be used for different portions of one or more neural networks”.
Paragraph [0062] recites “application114 includes code to evaluate one or more layers of a neural network, and causes said cache policy to be activated while these one or more layers are evaluated” which broadly discusses evaluating and activating one or more layers of a neural network. However, it does not discuss the specifics of how a cache policy is activated for different layers of the neural network.
Paragraphs [0063-0064] and [0100] recite “selecting optimal cache policies is based on simulation and analysis 202 of a neural networks performance” which broadly discusses using simulation of a neural networks to select cache policies used. However, it does not discuss how the simulation would be utilized for every processor within the breadth of the claims.
The claim scope is broader than the process described in the specification, and “the specification must teach those skilled in the art how to make and use the full scope of the claimed invention without ‘undue experimentation’,” see MPEP § 2164.08. As the specification requires an application comprising or utilizing code that interacts with said processor to cause it to switch to a cache policy selected by said application, then the specification does not support the full scope of the claim, meriting a rejection for failure to comply with the enablement requirement.
With respect to the level of predictability in the art, the examiner again looks to the paragraphs [0059] - [0062], [0064], [100], discussed above.
In claims 1 and 9 the processor is the only element used to achieved the desired result. The claims as presented do not offer details of the processor or its circuits, and do not specify how they are configured or arranged to achieve said result.
Paragraphs [0059] - [0062], [0064], [100], as discussed above, broadly discuss a processor executing an application with a function using a neural network and using simulation of a neural networks to select cache policies used. However, “if one skilled in the art can readily anticipate the effect of a change within the subject matter to which the claimed invention pertains, then there is predictability in the art. On the other hand, if one skilled in the art cannot readily anticipate the effect of a change within the subject matter to which that claimed invention pertains, then there is lack of predictability in the art”, see MPEP § 2164.03. There are no specific details on how to anticipate or predict how the simulation would be utilized for every conceivable processor, as covered by the claims, in a way to obtain the desired result.
With respect to the quantity of experimentation needed to make or use the invention based on the content of the disclosure, the examiner again looks to the paragraphs [0059] - [0062], [0064], [100], discussed above.
In claims 1 and 9 the processor is the only element used to achieved the desired result. The claims as presented do not offer details of the processor or its circuits, and do not specify how they are configured or arranged to achieve said result.
Paragraphs [0059] - [0062], [0064], [100], as discussed above, broadly discuss a processor executing an application with a function using a neural network and using simulation of a neural networks to select cache policies used. However, there are no specific details in the specification of how the processor and the application interact to obtain the desired result by the applicant. There is no detail on how the simulation would be utilized for every conceivable processor, as covered by the claims, in a way to obtain the desired result by the applicant with only a reasonable amount of experimentation.
The dependent claims are rejected as dependent on either claim 1 or 9.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chandrasekaran et al. (US 2021/0157743).
With respect claim 24, Chandrasekaran et al. teaches causing the one or more different cache eviction policies to be used by a processor to use for different portions of one or more neural networks (see paragraphs 120, 123 and 129; this may allow the neural network to provide cache replacement policies that are output in a sequence. For example, as traffic increases for a certain attribute, a sequence of cache replacement policies may be provided that gradually reduce the impact of the increasing traffic on the cache performance. This may also allow the neural network to take the cache replacement policies of other partitions into account when selecting a new cache replacement policy for a particular partition); and
selecting one or more different cache eviction policies to be used by a processor for the different portions of the one or more neural networks (see paragraphs 120, 123 and 129; This may also allow the neural network to take the cache replacement policies of other partitions into account when selecting a new cache replacement policy for a particular partition. For example, some embodiment may use a long short-term memory (LSTM) neural network to select a cache replacement policy. Note that recurrent neural networks are not required by all embodiments, and simple feedforward neural networks may also be used to select a cache replacement policy based on the inputs collected during the time interval).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 7-10, 12-14, 16-17, 19-21, 23, 25, 27-28 and 30-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandrasekaran et al. (US 2021/0157743) in view of Gottin et al. (US 2021/0374523).
With respect claim 1, Chandrasekaran et al. teaches one or more different cache eviction policies (see paragraphs 120, 123 and 129; this may allow the neural network to provide cache replacement policies that are output in a sequence. For example, as traffic increases for a certain attribute, a sequence of cache replacement policies may be provided that gradually reduce the impact of the increasing traffic on the cache performance. This may also allow the neural network to take the cache replacement policies of other partitions into account when selecting a new cache replacement policy for a particular partition) to be used for different portions of one or more neural networks (see paragraphs 120, 123 and 129; This may also allow the neural network to take the cache replacement policies of other partitions into account when selecting a new cache replacement policy for a particular partition. For example, some embodiment may use a long short-term memory (LSTM) neural network to select a cache replacement policy. Note that recurrent neural networks are not required by all embodiments, and simple feedforward neural networks may also be used to select a cache replacement policy based on the inputs collected during the time interval).
Chandrasekaran et al. does not teach one or more circuits to cause one or more different cache eviction policies.
However, Gottin et al. teaches wherein cache policy parameters are dynamically changed by simulating usage of data (see paragraphs 18, 31, 88 and 90); and that may be implemented as software configured to be executed in control logic such as contained in a Central Processing Unit (CPU) or Graphics Processing Unit (GPU) of an electronic device such as a computer … all logic described herein can be embodied using discrete components, integrated circuitry, programmable logic used in conjunction with a programmable logic device such as a Field Programmable Gate Array (FPGA) or microprocessor (i.e., circuitry causing different cache evictions to be used) (see paragraph 97).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Chandrasekaran et al. to include the above mentioned to optimize the cache algorithm parameters (see Gottin, paragraphs 22 and 81).
With respect claim 2, Chandrasekaran et al. teaches wherein the one or more circuits are to cause the one or more different cache eviction policies to be selected based, at least in part, on analysis of a layer of the one or more neural networks (see paragraphs 120, 123 and 129; in addition to the input layer of the neural network comprising inputs 1602 and/or inputs 1608, the neural network may also include one or more internal or hidden layers 1604. In some embodiments, the neural network may be a recurrent neural network (RNN) where connections between the nodes form a directed graph along a temporal sequence. This allows the neural network to exhibit temporal dynamic behavior and thus use an internal state (i.e., a memory-like behavior) to process sequences of events. This may allow the neural network to provide cache replacement policies that are output in a sequence).
With respect claim 4, Chandrasekaran et al. teaches wherein the one or more circuits are to select one or more of the different cache eviction policies based, at least in part, on analysis of performance data associated with use of the one or more neural networks (see paragraphs 120 and 123; this may allow the neural network to provide cache replacement policies that are output in a sequence. For example, as traffic increases for a certain attribute, a sequence of cache replacement policies may be provided that gradually reduce the impact of the increasing traffic on the cache performance… performance of the current cache replacement policy may then be evaluated to label the data sets for training the neural network. For example, if a default cache replacement policy is initially used, the cache replacement policy and a metric describing the performance of the cache may be provided to a labeling process 1714. The labeling process 1714 may evaluate the cache performance metric, such as a number of cache misses 1702 to determine whether the cache replacement policy 1504 currently being output by the neural network is performing adequately).
With respect claim 5, Chandrasekaran et al. teaches wherein the one or more circuits are to cause the one or more different cache eviction policies to be used in response to an instruction from at least one of an application, runtime, or operating system (see paragraphs 111; cache replacement policies 1402, 1404, 1406 may be changed dynamically at runtime by number different methods).
With respect claim 7, Chandrasekaran et al. teaches wherein the one or more circuits are to select the one or more different cache eviction policies based, at least in part, on one or more types of operations associated with a portion of the one or more neural networks (see paragraph 115, 120 and 129; the policy selection process 1502 monitors the incoming requests 1508 and determines that the attributes 1510 associated with those requests 1508 have shifted to a new attribute for that cache partition, the policy selection process 1502 may send the new attribute to the policy data store 1506. The policy data store 1506 may then select a policy that corresponds to the new attribute. In some embodiments, the cache replacement policies 1501, 1503 may be associated with different patterns in the request traffic 1508. For request patterns that are received at a relatively high rate and requesting similar objects, an LRU cache replacement policy may be selected for that particular partition. If the request pattern changes such that objects in that partition are rarely requested multiple times, the cache replacement policy may be changed to a different cache replacement policy from the policy data store).
With respect claim 8, Chandrasekaran et al. do not teach wherein the one or more different cache eviction policies are selected based, at least in part, on simulated use of the one or more neural networks.
However, Gottin et al. teaches wherein the one or more cache policies are selected based, at least in part, on simulated use of the one or more neural networks (see paragraphs 18, 31, 88 and 90; cache policy parameters are dynamically changed by simulating usage of data).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the processor taught by Chandrasekaran et al. to include the above mentioned to optimize the cache algorithm parameters (see Gottin, paragraphs 22 and 81).
With respect claim 9, Chandrasekaran et al. teaches cause one or more different cache eviction policies (see paragraphs 120, 123 and 129; this may allow the neural network to provide cache replacement policies that are output in a sequence. For example, as traffic increases for a certain attribute, a sequence of cache replacement policies may be provided that gradually reduce the impact of the increasing traffic on the cache performance. This may also allow the neural network to take the cache replacement policies of other partitions into account when selecting a new cache replacement policy for a particular partition) to be used for different portions of one or more one or more neural networks (see paragraphs 120, 123 and 129; This may also allow the neural network to take the cache replacement policies of other partitions into account when selecting a new cache replacement policy for a particular partition. For example, some embodiment may use a long short-term memory (LSTM) neural network to select a cache replacement policy. Note that recurrent neural networks are not required by all embodiments, and simple feedforward neural networks may also be used to select a cache replacement policy based on the inputs collected during the time interval).
Chandrasekaran et al. does not teach wherein a processor causes the one or more different cache eviction policies to be used.
However, Gottin et al. teaches wherein cache policy parameters are dynamically changed by simulating usage of data (see paragraphs 18, 31, 88 and 90); and that may be implemented as software configured to be executed in control logic such as contained in a Central Processing Unit (CPU) or Graphics Processing Unit (GPU) of an electronic device such as a computer … all logic described herein can be embodied using discrete components, integrated circuitry, programmable logic used in conjunction with a programmable logic device such as a Field Programmable Gate Array (FPGA) or microprocessor (i.e., circuitry causing different cache evictions to be used) (see paragraph 97).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Chandrasekaran et al. to include the above mentioned to optimize the cache algorithm parameters (see Gottin, paragraphs 22 and 81).
With respect claim 10, Chandrasekaran et al. teaches wherein the processor is to cause the one or more different cache eviction policies to be selected based, at least in part, on analysis of a layer of the one or more neural networks (see paragraphs 120, 123 and 129; in addition to the input layer of the neural network comprising inputs 1602 and/or inputs 1608, the neural network may also include one or more internal or hidden layers 1604. In some embodiments, the neural network may be a recurrent neural network (RNN) where connections between the nodes form a directed graph along a temporal sequence. This allows the neural network to exhibit temporal dynamic behavior and thus use an internal state (i.e., a memory-like behavior) to process sequences of events. This may allow the neural network to provide cache replacement policies that are output in a sequence).
With respect claim 12, Chandrasekaran et al. teaches wherein the one or more circuits are to select one or more of the different cache eviction policies based, at least in part, on analysis of performance data associated with use of the one or more neural networks (see paragraphs 120 and 123; this may allow the neural network to provide cache replacement policies that are output in a sequence. For example, as traffic increases for a certain attribute, a sequence of cache replacement policies may be provided that gradually reduce the impact of the increasing traffic on the cache performance… performance of the current cache replacement policy may then be evaluated to label the data sets for training the neural network. For example, if a default cache replacement policy is initially used, the cache replacement policy and a metric describing the performance of the cache may be provided to a labeling process 1714. The labeling process 1714 may evaluate the cache performance metric, such as a number of cache misses 1702 to determine whether the cache replacement policy 1504 currently being output by the neural network is performing adequately).
With respect claim 13, Chandrasekaran et al. teaches wherein the one or more circuits are to cause the one or more different cache eviction policies to be used in response to an instruction from at least one of an application, runtime, or operating system (see paragraphs 111; cache replacement policies 1402, 1404, 1406 may be changed dynamically at runtime by number different methods).
With respect claim 14, Gottin et al. does not explicitly teach wherein the one or more different cache eviction policies comprise at least one of an algorithm or heuristic to select data for replacement in one or more caches (see paragraph 108; cache replacement policy may also be referred to as a cache replacement algorithm or simply as a cache algorithm. The cache replacement policy may include optimizing instructions and software and/or hardware that govern how object portions are stored and replaced in each of the partitions. For example, when a partition in the cache is full, the cache replacement policy may include algorithms that determine which object portions should be discarded to make room for new object portions as they are requested by client devices).
With respect claim 16, Chandrasekaran et al. teaches wherein the processor is to select the one or more different cache eviction policies based, at least in part, on one or more types of operations associated with a portion of the one or more neural networks (see paragraph 115, 120 and 129; the policy selection process 1502 monitors the incoming requests 1508 and determines that the attributes 1510 associated with those requests 1508 have shifted to a new attribute for that cache partition, the policy selection process 1502 may send the new attribute to the policy data store 1506. The policy data store 1506 may then select a policy that corresponds to the new attribute. In some embodiments, the cache replacement policies 1501, 1503 may be associated with different patterns in the request traffic 1508. For request patterns that are received at a relatively high rate and requesting similar objects, an LRU cache replacement policy may be selected for that particular partition. If the request pattern changes such that objects in that partition are rarely requested multiple times, the cache replacement policy may be changed to a different cache replacement policy from the policy data store).
With respect claim 17, Chandrasekaran et al. teaches a machine-readable medium having stored thereon instructions which, if performed by one or more processors (see paragraphs 180-182; computer readable storage medium), cause one or more different cache eviction policies (see paragraphs 120, 123 and 129; this may allow the neural network to provide cache replacement policies that are output in a sequence. For example, as traffic increases for a certain attribute, a sequence of cache replacement policies may be provided that gradually reduce the impact of the increasing traffic on the cache performance. This may also allow the neural network to take the cache replacement policies of other partitions into account when selecting a new cache replacement policy for a particular partition) to be used for different portions of one or more neural networks (see paragraphs 120, 123 and 129; This may also allow the neural network to take the cache replacement policies of other partitions into account when selecting a new cache replacement policy for a particular partition. For example, some embodiment may use a long short-term memory (LSTM) neural network to select a cache replacement policy. Note that recurrent neural networks are not required by all embodiments, and simple feedforward neural networks may also be used to select a cache replacement policy based on the inputs collected during the time interval).
Chandrasekaran et al. does not teach wherein one or more processors that causes the one or more different cache eviction policies to be used.
However, Gottin et al. teaches wherein cache policy parameters are dynamically changed by simulating usage of data (see paragraphs 18, 31, 88 and 90); and that may be implemented as software configured to be executed in control logic such as contained in a Central Processing Unit (CPU) or Graphics Processing Unit (GPU) of an electronic device such as a computer … all logic described herein can be embodied using discrete components, integrated circuitry, programmable logic used in conjunction with a programmable logic device such as a Field Programmable Gate Array (FPGA) or microprocessor (i.e., circuitry causing different cache evictions to be used) (see paragraph 97).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Chandrasekaran et al. to include the above mentioned to optimize the cache algorithm parameters (see Gottin, paragraphs 22 and 81).
With respect claim 19, Chandrasekaran et al. teaches wherein the one or more processors are to select one or more of the different cache eviction policies based, at least in part, on analysis of performance data associated with use of the one or more neural networks (see paragraphs 120 and 123; this may allow the neural network to provide cache replacement policies that are output in a sequence. For example, as traffic increases for a certain attribute, a sequence of cache replacement policies may be provided that gradually reduce the impact of the increasing traffic on the cache performance… performance of the current cache replacement policy may then be evaluated to label the data sets for training the neural network. For example, if a default cache replacement policy is initially used, the cache replacement policy and a metric describing the performance of the cache may be provided to a labeling process 1714. The labeling process 1714 may evaluate the cache performance metric, such as a number of cache misses 1702 to determine whether the cache replacement policy 1504 currently being output by the neural network is performing adequately).
With respect claim 20, Chandrasekaran et al. teaches cause the one or more different cache eviction policies to be used in response to an instruction from at least one of an application, runtime, or operating system (see paragraphs 111; cache replacement policies 1402, 1404, 1406 may be changed dynamically at runtime by number different methods).
With respect claim 21, Gottin et al. does not explicitly teach wherein the one or more different cache eviction policies comprise at least one of an algorithm or heuristic to select data for replacement in one or more caches (see paragraph 108; cache replacement policy may also be referred to as a cache replacement algorithm or simply as a cache algorithm. The cache replacement policy may include optimizing instructions and software and/or hardware that govern how object portions are stored and replaced in each of the partitions. For example, when a partition in the cache is full, the cache replacement policy may include algorithms that determine which object portions should be discarded to make room for new object portions as they are requested by client devices).
With respect claim 23, Chandrasekaran et al. teaches select the one or more different cache eviction policies based, at least in part, on one or more types of operations associated with a portion of the one or more neural networks (see paragraph 115, 120 and 129; the policy selection process 1502 monitors the incoming requests 1508 and determines that the attributes 1510 associated with those requests 1508 have shifted to a new attribute for that cache partition, the policy selection process 1502 may send the new attribute to the policy data store 1506. The policy data store 1506 may then select a policy that corresponds to the new attribute. In some embodiments, the cache replacement policies 1501, 1503 may be associated with different patterns in the request traffic 1508. For request patterns that are received at a relatively high rate and requesting similar objects, an LRU cache replacement policy may be selected for that particular partition. If the request pattern changes such that objects in that partition are rarely requested multiple times, the cache replacement policy may be changed to a different cache replacement policy from the policy data store).
With respect claim 25, Chandrasekaran et al. teaches wherein the one or more different cache eviction policies are selected based, at least in part, on analysis of a layer of the one or more neural networks (see paragraphs 120, 123 and 129; in addition to the input layer of the neural network comprising inputs 1602 and/or inputs 1608, the neural network may also include one or more internal or hidden layers 1604. In some embodiments, the neural network may be a recurrent neural network (RNN) where connections between the nodes form a directed graph along a temporal sequence. This allows the neural network to exhibit temporal dynamic behavior and thus use an internal state (i.e., a memory-like behavior) to process sequences of events. This may allow the neural network to provide cache replacement policies that are output in a sequence).
With respect claim 27, Chandrasekaran et al. teaches wherein selecting the one or more of the different cache eviction policies based, at least in part, on analysis of performance data associated with use of the one or more neural networks (see paragraphs 120 and 123; this may allow the neural network to provide cache replacement policies that are output in a sequence. For example, as traffic increases for a certain attribute, a sequence of cache replacement policies may be provided that gradually reduce the impact of the increasing traffic on the cache performance… performance of the current cache replacement policy may then be evaluated to label the data sets for training the neural network. For example, if a default cache replacement policy is initially used, the cache replacement policy and a metric describing the performance of the cache may be provided to a labeling process 1714. The labeling process 1714 may evaluate the cache performance metric, such as a number of cache misses 1702 to determine whether the cache replacement policy 1504 currently being output by the neural network is performing adequately).
With respect claim 28, Chandrasekaran et al. teaches wherein the one or more different cache eviction policies are selected in response to an instruction from at least one of an application, runtime, or operating system (see paragraphs 111; cache replacement policies 1402, 1404, 1406 may be changed dynamically at runtime by number different methods).
With respect claim 30, Chandrasekaran et al. teaches selecting the one or more different cache eviction policies based, at least in part, on one or more types of operations associated with a portion of the one or more neural networks (see paragraph 115, 120 and 129; the policy selection process 1502 monitors the incoming requests 1508 and determines that the attributes 1510 associated with those requests 1508 have shifted to a new attribute for that cache partition, the policy selection process 1502 may send the new attribute to the policy data store 1506. The policy data store 1506 may then select a policy that corresponds to the new attribute. In some embodiments, the cache replacement policies 1501, 1503 may be associated with different patterns in the request traffic 1508. For request patterns that are received at a relatively high rate and requesting similar objects, an LRU cache replacement policy may be selected for that particular partition. If the request pattern changes such that objects in that partition are rarely requested multiple times, the cache replacement policy may be changed to a different cache replacement policy from the policy data store).
With respect claim 31, Chandrasekaran et al. do not teach wherein the one or more different cache eviction policies are selected based, at least in part, on simulated use of the one or more neural networks.
However, Gottin et al. teaches wherein the one or more cache policies are selected based, at least in part, on simulated use of the one or more neural networks (see paragraphs 18, 31, 88 and 90; cache policy parameters are dynamically changed by simulating usage of data).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Chandrasekaran et al. to include the above mentioned to optimize the cache algorithm parameters (see Gottin, paragraphs 22 and 81).
Allowable Subject Matter
Claims 18, 22, 26 and 29 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Grover et al. (US 2023/0025245) teaches neural network evaluation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
/JOHN R COTTINGHAM/Director, Art Unit 2100
Prosecution Insights