DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 13 January 2026, 13 February 2026 has been entered.
Claim Construction
Regarding claim 1, the preamble is given patentable weight. Claim 4 contains the
limitation “the neural processor circuit” in the body, which is referring to the limitations as recited in the preamble of claim 1. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to the technological environment of a neural processor circuit performing the particular functionalities. The body of the claim depends on the preamble for completeness, and
gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 1 should
be afforded patentable weight.
Claim Objections
Claims 3 and 14 are objected to because of the following informalities: “after a rounding location” although the initial instance of the “rounding location” is first recited in claims 1 and 13, respectively to claims 3 and 14. Should the instance in claims 3 and 14 be meant to antecedently refer back to the instance in claims 1 and 13, Applicant should amend claims 3 and 14 to recite “after [[a]] the rounding location”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 11-15, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 11449574 B2 Lie et al. (hereinafter “Lie”) in view of US 20180322607 A1 Mellempudi et al. (hereinafter “Mellempudi”) in view of Sewak, Mohit and Karim, Md. Rezaul. and Pujari, Pradeep. "Practical Convolution Neural Networks - Implement advanced deep learning models using Python". Packt Publishing. ISBN 978-1-78839-230-3. February 2018. (hereinafter “Sewak”) in view of US 20170192752 A1 Bradbury et al. (hereinafter “Bradbury”).
Regarding claim 1, Lie teaches:
a neural processor circuit (Fig. 1, 100, Col. 28, lines 6-11) comprising:
a neural engine (Fig. 1, 120; Col. 33, lines 4-6, 42-47; Fig. 4, 400; Col. 62, lines 12-20) configured to perform a convolutional operation related to a neural network (Col. 14, lines 35-58) to generate a processed value (Fig. 29, 2955; Col. 106, lines 62-67, Col. 107, lines 1-3) and
a post-processing circuit (Fig. 29, 2900; Col. 105, lines 36-49, 65-67, Col. 106, lines 1-4) coupled to neural engine (Col. 32, lines 47-51), the post-processing circuit configured to round the processed value stochastically (Col. 105, lines 36-45), the post-processing circuit comprising:
a random bit generator (Fig. 29, 2921; Col. 106, lines 13-19) configured to generate an initial random string of bits (Fig. 29, 2962; Col. 107, lines 33-34);
an adder circuit (Fig. 29, 2922; Col. 108, lines 3-6) configured to add (Col. 107, lines 51-55) a random string of bits determined based on the initial random string of bits to a version of the processed value (Fig. 29, 2957.1; Col. 107, lines 10-22) to generate an added value (Fig. 29, 2963; Col. 107, lines 51-56); and
a rounding circuit (Fig. 29, 2914; Col. 106, lines 5-9; Note: “incrementer” 2914 performs same functionality of “rounding circuit” despite having a different name) configured to truncate (Col. 107, lines 55-67, Col. 108, lines 1-8; Col. 104, lines 24-38, truncation) the added value to generate an output value (Fig. 29, 2964; Col. 107, lines 19-25; Col. 108, lines 17-22) of the convolutional operation (Fig. 29, 2964; Col. 107, lines 19-25; Col. 108, lines 17-22),
wherein the post-processing circuitry is configured to provide multiple modes of rounding (Fig. 30A, 3021; Col. 107, lines 26-33; Col. 109, lines 30-33) and the multiple modes include a standard rounding mode (Col. 109, lines 30-33; Col. 104, lines 21-38), an integer stochastic rounding mode (Col. 109, lines 7-18; Col. 112, lines 60-67, Col. 113, lines 1-3) and a floating-point stochastic rounding mode (Col. 105, lines 36-40; Col. 106, lines 44-49),
a rounding location (Fig. 30D, 3002.1; Col. 111, lines 30-32).
Although Lie generally discloses a multiply-accumulate operation, they are silent with explicitly disclosing such multiply-accumulate operation is a convolutional operation. Further, while Lie discloses multiple modes of rounding, it appears they are silent with disclosing the integer stochastic rounding mode in response to the processed value being an integer, the floating-point stochastic rounding mode in response to the processed value being a floating-point format, wherein the version of the processed value comprises a floating-point number converted from the integer in response to the post-processing circuit operating in the integer stochastic rounding mode. Lie is silent with disclosing a random string of bits, as necessitated by the amendment, and in response to the post-processing circuit operating in the integer stochastic rounding mode, the random string of bits is generated by truncating the initial random string of bits at a rounding location in the floating-point number, the rounding location being determined based on the integer.
Mellempudi teaches:
a convolutional operation ([0153]);
the integer stochastic rounding mode in response to the processed value being an integer (Fig. 14, 1420, [0190-0191]; Fig. 15B, 1524, [0195]), the floating-point stochastic rounding mode in response to the processed value being a floating-point format (Fig. 14, 1410, [0190-0191]; Fig. 15A, 1512, [0194]; Fig. 17, [0217]), wherein the version of the processed value comprises a floating-point number (Fig. 15B, 1520, 1534A, 1534B, [0195-0196]) converted from the integer in response to the post-processing circuit operating in the integer stochastic rounding mode ([0195] converting given a magnitude integer and in de-quantization);
and in response to the post-processing circuit operating in the integer stochastic rounding mode (Fig. 14, 1420, [0190-0191]; Fig. 15B, 1524, [0195]), and in the floating-point number (Fig. 14, 1410, [0190-0191]; Fig. 15A, 1512, [0194]; Fig. 17, [0217]), the rounding location being determined based on the integer (Fig. 15B “1533”, [0194-0195], Fig. 17 dashed line [0217]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Lie’s rounding device with Mellempudi’s convolution techniques and integer/floating-point features because they are in the claimed invention’s same field of endeavor of stochastic rounding ([0213]).
Although Lie generally teaches convolutional neural networks (Col. 14, lines 44-48), they are silent with disclosing explicitly performing convolution operations. It would have been obvious to one of ordinary skill in the art to implement the convolution feature as convolutions are well-known techniques for training and inferencing neural networks, the building block for convolutional neural networks (see Sewak, Pg. 11-13, Convolutional Operations), and would have yielded predictable results when implemented.
Further, it would have been obvious to one of ordinary skill in the art to implement processing of integer values, as Lie teaches only processing the mantissa of floating-point values in the rounding modes (Fig. 30A, 3021; Col. 107, lines 26-33; Col. 109, lines 30-33). By expanding Lie’s capability to process integer values in addition to floating-point values, not only would it give Lie’s system more flexibility in terms of the type of data it can process, but also allow it to process lower precisions for rounding (Fig. 14, 1421, 1422, [0191] 16-bits as an example, and where the size can vary for different fixed-point representations [0189]). It would have been obvious to one of ordinary skill in the art to implement processing of floating-point values in their entirety, as Lie teaches only processing the mantissa value in the rounding modes (Fig. 29, 2958; Col. 107, lines 26-33; Col. 109, lines 30-33). By expanding Lie’s capability to process all parts of the floating-point values, it would give Lie’s system more flexibility with processing lower floating-point precisions ([0212]).
Using the known arithmetic operation to provide a predictable outcome in Lie would have been obvious to one of ordinary skill in the art, since one of ordinary skill in the art would recognize that Lie was ready for improvement to incorporate the well-known operation. Further, it would have been obvious to expand Lie’s processing capabilities to include integer/floating-point values as doing so would allow for more flexibility in data type processing and lower precisions for rounding.
Lie in view of Mellempudi in view of Sewak appear to be silent to disclosing a random string of bits, the random string of bits is generated by truncating the initial random string of bits at a rounding location.
Bradbury discloses a random string of bits (Fig. 1 “130” [0015]), the random string of bits is generated by truncating ([0015] truncated to produce “130”) the initial random string of bits at a rounding location.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Lie in view of Mellempudi in view of Sewak’s rounding system with Bradbury’s truncation feature because they are in the claimed invention’s same field of endeavor of stochastic rounding ([Abstract]). It would have been obvious to one of ordinary skill in the art to implement the truncation feature because it is a well-known technique in the art ([0002]), and would have yielded predictable results when implemented in Lie in view of Mellempudi in view of Sewak’s rounding system. Although Lie generally discloses truncation as it relates to rounding (co. 104 ln. 29-38), they appear to be silent with disclosing it as it relates to generating random string of bits. Using the known truncation technique to provide a predictable outcome in Lie in view of Mellempudi in view of Sewak’s system would have been obvious to one of ordinary skill in the art, since one of ordinary skill in the art would recognize that Lie was ready for improvement to incorporate the truncation feature to attempt to avoid tendencies for one side to benefit when rounding ([0002]), as taught by Bradbury.
Regarding claim 2, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Lie teaches the neural processor circuit further comprising:
a normalization circuit (Fig. 29, 2913; Col. 107, lines 10-15) configured to convert the processed value (Fig. 29, 2955; Col. 106, lines 62-67, Col. 107, lines 1-3) in the floating-point format to a normalized value (Fig. 29, outputs of 2913; Col. 107, lines 16-19) to be added (Col. 107, lines 51-55) to the random string of bits by the adder circuit (Fig. 29, 2922; Col. 108, lines 3-6) in the floating-point stochastic rounding mode (Col. 105, lines 36-40; Col. 106, lines 44-49).
Although Lie generally discloses the processed value, it appears they are silent with disclosing the processed value being in the floating-point format, and as necessitated by the amendment, the random string of bits.
Mellempudi teaches:
the processed value being a floating-point format (Fig. 14, 1410, [0190-0191]; Fig. 15A, 1512, [0194]; Fig. 17, [0217]).
The motivation to combine provided with respect to claim 1 equally applies.
Lie in view of Mellempudi in view of Sewak appear to be silent to disclosing a random string of bits.
Bradbury discloses a random string of bits (Fig. 1 “130” [0015]).
The motivation to combine provided with respect to claim 1 equally applies.
Regarding claim 3, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Lie teaches the neural processor wherein:
the normalization circuit (Fig. 29, 2913; Col. 107, lines 10-15) is further configured to generate (Fig. 29, 2913; Col. 107, lines 10-15) the normalized value (Fig. 29, outputs of 2913; Col. 107, lines 16-19) based on a leading one (Fig. 30D, 2956; Col. 111, lines 22-30) in the processed value (Fig. 29, 2955; Col. 106, lines 62-67, Col. 107, lines 1-3); and
the adder circuit (Fig. 29, 2922; Col. 108, lines 3-6) is configured to add (Col. 107, lines 51-55), after (Fig. 30D, 3003; Col. 111, lines 32-34, 3003 contains 2957.1 and 2957.1 is added with N-bit random number 2962; Fig. 29, 2957.1) a rounding location (Fig. 30D, 3002.1; Col. 111, lines 30-32), the random string of bits to the normalized value to generate the added value (Fig. 29, 2963; Col. 107, lines 51-56), wherein the rounding location is relative to the leading one (Fig. 30D, 2956, 3002.1; Col. 111, lines 26-32).
Lie appears to be silent with disclosing, as necessitated by the amendment, the random string of bits.
Lie in view of Mellempudi in view of Sewak appear to be silent to disclosing, as necessitated by the amendment, a random string of bits.
Bradbury discloses a random string of bits (Fig. 1 “130” [0015]).
The motivation to combine provided with respect to claim 1 equally applies.
Regarding claim 4, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Lie teaches wherein the processed value (see claim 1 mapping) is:
the integer, and the neural processor circuit further comprises a normalization circuit (see claim 1 mapping) configured to:
determine, based on the integer, the rounding location (Fig. 30D, 3002.1; Col. 111, lines 30-32) in the floating-point number; and
convert the integer to the floating-point number (Col. 106, lines 44-49; Col. 108, lines 47-56; Col. 109, lines 3-21);
wherein the adder circuit is further configured to add, after the rounding location, the random string of bits to the floating-point number to generate the added value (see claim 2 mapping).
Although while Lie discloses processing parts of the floating-point value, it appears they are silent with disclosing the processed value being an integer, and as necessitated by the amendment, the floating-point number and the random string of bits.
Mellempudi teaches:
the processed value being an integer (Fig. 14, 1420, [0190-0191]; Fig. 15B, 1524, [0195]) and the floating-point number (Fig. 15B, 1520, 1534A, 1534B, [0195-0196]).
The motivation to combine provided with respect to claim 1 equally applies.
Lie in view of Mellempudi in view of Sewak appear to be silent to disclosing, as necessitated by the amendment, a random string of bits.
Bradbury discloses a random string of bits (Fig. 1 “130” [0015]).
The motivation to combine provided with respect to claim 1 equally applies.
Regarding claim 6, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Lie teaches wherein the post-processing circuit (see claim 1 mapping) is configured to:
support rounding operations of a plurality of processed values, the plurality of processed values comprising the processed value and other processed values generated by the neural engine (Col. 32, lines 59-67, Col. 33, lines 1-3; Col. 113, lines 17-24).
Regarding claim 7, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Lie teaches wherein the random bit generator (see claim 1 mapping) is coupled to:
a master seed generator (Fig. 29, 2920; Col. 106, lines 9-16; Note: “instruction decode logic” 2920 performs same functionality of “master seed generator” despite having a different name) configured to generate a master seed (Fig. 29, 2961; Col. 107, lines 30-50, instruction decode logic 2920 decodes to generate RNG selector 2961; Col. 106, lines 20-23, seed), and wherein the random bit generator is configured to generate the initial random string of bits derived from the master seed (Col. 107, lines 26-50; Col. 106, lines 20-23, seed).
Regarding claim 8, in addition to the teachings addressed in the claim 7 analysis, the rejection of claim 7 is incorporated and Lie teaches wherein the random bit generator (see claim 1 mapping) comprises:
a linear-feedback shift register (LFSR) (Col. 105, lines 25-35) configured to skip forward based on a value derived from the master seed (Fig. 29, 2961; Col. 107, lines 30-50; Col. 106, lines 20-23, seed).
Regarding claim 11, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Lie teaches wherein the random bit generator (see claim 1 mapping) includes:
a plurality of linear-feedback shift register (LFSR) (Col. 105, lines 25-35) configured to generate multiple strings of bits in parallel (Col. 107, lines 30-50).
Regarding claim 12, in addition to the teachings addressed in the claim 11 analysis, the rejection of claim 11 is incorporated and Lie teaches wherein:
a first LFSR of the plurality of LFSRs (Col. 105, lines 25-35) is configured to skip forward (Col. 107, lines 30-50) a first number of times to generate a first string of bits and a second LFSR of the plurality of LFSRs is configured to skip forward a second number of times to generate a second string of bits different from the first string of bits (Col. 110, lines 23-53).
Claims 13-15, 17-18 are directed to a method that would be practiced by the device of claim 1. All steps recited in claims 13-15, 17-18 are practiced by the device of claims 1, 3-4, 7-8, respectively. The claims 1, 3-4, 7-8 analysis equally applies to claims 13-15, 17-18, respectively.
Claim 14 recites additional limitations not included in claim 3, Lie teaches truncating (Col. 107, lines 55-67, Col. 108, lines 1-8; Col. 104, lines 24-38, truncation) the added value (Fig. 29, 2963; Col. 107, lines 51-56) to generate the output value (Fig. 29, 2964; Col. 107, lines 19-25; Col. 108, lines 17-22).
Claim 15 recites additional limitations not included in claim 4, Lie teaches truncating the added value (see claim 14 mapping); and normalizing (see claim 2 mapping) the added value to generate the output value (see claim 14 mapping).
Claim 19 is directed to a device which recites similar limitations to that of claim 1. The claim 1 analysis equally applies. Additionally, Lie further teaches:
a memory (Fig. 1, 152, 162; Col. 35, lines 15-20) configured to store a neural network (Col. 33, lines 61-67; Col. 15, lines 6-23); and a neural processor circuit (Fig. 1, 100; Col. 28, lines 6-11 ) coupled to the memory (Col. 32, lines 59-67, Col. 33, lines 1-15).
Claims 5, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lie in view of Mellempudi in view of Sewak in view of Bradbury, and in further view of Cusick, Thomas W., Stanica, Pantelimon , Chapter 2 - Fourier Analysis of Boolean Functions, Cryptographic Boolean Functions and Applications (Second Edition), Academic Press, 2009, Pages 7-29, ISBN 9780128111291. (hereinafter “Cusick”).
Regarding claim 5, in addition to the teachings addressed in the claim 1 analysis,
the rejection of claim 1 is incorporated and Lie teaches wherein the random bit generator (see claim 1 mapping) comprises:
a linear-feedback shift register (LFSR) (Col. 105, lines 25-35) having one or more registers whose input bits are linear functions of previous states (Col. 107, lines 40-50).
Lie is silent with explicitly disclosing the linear-feedback shift register having one or more registers whose input bits are linear functions.
Similarly, Mellempudi is silent with explicitly disclosing the linear-feedback shift register having one or more registers whose input bits are linear functions.
Thus, Lie in view of Mellempudi in view of Sewak in view of Bradbury is silent with disclosing the linear-feedback shift register having one or more registers whose input bits are linear functions.
Cusick teaches the linear-feedback shift register having one or more registers (Pg. 20, Para. 3) whose input bits are linear functions (Pg. 19, Para. 2; Pg. 20, Para. 3-4).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Lie in view of Mellempudi in view of Sewak in view of Bradbury’s rounding system with Cusick’s linear-feedback shift register’s (LFSR) subcircuits because they are in the claimed invention’s same field of endeavor of computer architecture (Pg. 19, Para. 1). Although Lie generally teaches a LFSR (Col. 105, lines 25-35), they are silent with disclosing explicitly the subcircuits of which compose it. It would have been obvious to one of ordinary skill in the art to implement the specific LFSR subcircuits because they are well-known in the art (Pg. 19, Para. 4-5), and would have yielded predictable results when implemented. Using the known subcircuits to provide a predictable outcome in Lie in view of Mellempudi in view of Sewak in view of Bradbury’s system would have been obvious to one of ordinary skill in the art, since one of ordinary skill in the art would recognize that Lie was ready for improvement to incorporate the subcircuits, as taught by Cusick.
Claim 16 is directed to a method that would be performed by the device of claim 5. The claim 5 analysis equally applies, and claim 16 is similarly rejected.
Claim 20 is directed to a device that recites similar limitations to the device of claim 5. The claim 5 analysis equally applies, and claim 20 is similarly rejected.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lie in view of Mellempudi in view of Sewak in view of Bradbury, and in further view of US 20210056427 A1 Yoo et al. (hereinafter “Yoo”).
Regarding claim 9, in addition to the teachings addressed in the claim 7 analysis,
the rejection of claim 7 is incorporated and Lie teaches wherein the neural network (see claim 1 mapping) includes:
a plurality of layers (Col. 14, lines 60-67, Col. 15, lines 1-5), and wherein the post-processing circuit (see claim 1 mapping) is configured to generate a different master seed (Fig. 29, 2961; Col. 107, lines 30-50, instruction decode logic 2920 decodes to generate RNG selector 2961; Col. 106, lines 20-23, seed) for each layer of the plurality of layers (Col. 14, lines 60-67, Col. 15, lines 1-5).
Although Lie generally teaches a plurality of layers and the master seed, they are silent with explicitly disclosing a different master seed for each layer.
Similarly, Mellempudi is silent with disclosing a different master seed for each layer.
Thus, Lie in view of Mellempudi in view of Sewak in view of Bradbury is silent with disclosing a different master seed for each layer.
Yoo teaches a different seed for each layer ([0027], [0062-0063]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Lie in view of Mellempudi in view of Sewak in view of Bradbury’s rounding system with Yoo’s different seed for each layer feature because they are in the claimed invention’s same field of endeavor of neural network operations [abstract]. It would have been obvious to one of ordinary skill in the art to implement the different seed for each layer feature as it allows the system to perform error propagation, a neural network training task, more effectively by allowing each layer to have its own seed ([0063]). Making this modification would be beneficial, as Lie in view of Mellempudi in view of Sewak in view of Bradbury’s rounding system is now capable of performing this training task more efficiently without needing to fetch from external memory, thus reducing memory accesses by about 42.8% ([0064]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lie in view of Mellempudi in view of Sewak in view of Bradbury, and in further view of US 6985583 B1 Brainard et al. (hereinafter “Brainard”).
Regarding claim 10, in addition to the teachings addressed in the claim 7 analysis,
the rejection of claim 7 is incorporated.
Although Lie generally teaches the master seed (Fig. 29, 2961; Col. 107, lines 30-50, instruction decode logic 2920 decodes to generate RNG selector 2961; Col. 106, lines 20-23, seed) and the master seed generator (see claim 7 mapping), they are silent with disclosing storing the master seed for verification.
Similarly, Mellempudi is silent with disclosing storing the master seed for verification.
Thus, Lie in view of Mellempudi in view of Sewak in view of Bradbury is silent with disclosing storing the master seed for verification.
Brainard teaches storing the master seed for verification (Col. 4, lines 48-58; Col. 8, lines 58-67).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Lie in view of Mellempudi in view of Sewak in view of Bradbury’s rounding system with Brainard’s storing feature because they are in the claimed invention’s same field of endeavor of computer architecture (Col. 1, lines 6-8). It would have been obvious to one of ordinary skill in the art to implement the storing feature as it allows the system to use the stored master seed for authentication (Col. 8, lines 58-60). Making this modification would be beneficial, as Lie in view of Mellempudi in view of Sewak in view of Bradbury’s rounding system is now capable of performing authentication to improve security purposes through verification (Col. 2, lines 27-39; Col. 4, lines 48-58).
Response to Arguments
35 USC 103. Arguments are directed to newly amended features.
Applicant’s arguments, see Remarks (Arg. 1: Pg. 10, Para. 2-3), filed 13 January 2026, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Bradbury, as necessitated by the amendment.
Conclusion
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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