Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 26 recites the limitation "conductive interconnects" in line 2 is unclear is that include the conductive interconnect as previous claim in claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8 and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0223557, as disclosed in previous office action) in view Fan (US 2022/0352044).
As for claims 1-2, Chen et al. disclose in Figs. 3A-3N and the related text a microelectronic assembly, comprising:
an interposer 68/76” having a first (upper) face and a second (lower) face opposite to the first face, wherein the interposer 68/76”comprises:
a first layer 76”comprising a die 21 and a first dielectric material [0045] around the die (figs. 3A-3N), and a second layer 68 comprising a second dielectric material [0026] different from the first dielectric material [0045], wherein the second layer 68 is a redistribution layer (RDL);
a conductive pillar 72 through the first layer 76” between the first face and the second face (Figs. 3A-3N);
a package substrate 77 coupled to the first (lower) face;
an integrated circuit (IC) die 22 coupled to the second (upper) face; and
a metal trace 66 in the first RDL 68 and in contact with the second dielectric material (fig. 3N),
Chen does not disclose an edge ring in the interposer, wherein: edge ring comprises: a metal trace in the first RDL and in contact with the second dielectric material, the metal trace being along a periphery of the interposer; and a plurality of metal vias through the RDL, the plurality of metal vias in contact with the metal trace, wherein the metal trace is parallel and proximate to the periphery of the interposer, wherein the plurality of metal vias and the set of stacked metal traces forming a mesh structure through a cross- section of the RDL, wherein the edge ring further comprises bonding pads on the first face of the interposer, wherein: a portion of the plurality of metal vias couple the bonding pads to the metal trace in the RDL, first conductive interconnects at the bonding pads are coupled to the package substrate, and the first conductive interconnects are conductively isolated from conductive pathways in the package substrate.
Fan discloses in Figs. 2-3C and the related text an edge ring in the interposer, wherein: edge ring 130 comprises: a metal trace 131 in the RDL and in contact with the second dielectric material, the metal trace 131 being along a periphery of the interposer (fig. 3C); and a plurality of metal vias 132 through the RDL, the plurality of metal vias 132 in contact with the metal trace 131 (fig. 3C), a bond pad 153 at the first face of the interposer; and a conductive interconnect 152 between and coupled with the bond pad 153 and the package substrate 151, wherein: the bond pad 153 is coupled with the metal trace 131 of the edge ring through a metal via 132 of the plurality of metal vias, and the conductive interconnect 152 is conductively isolated from conductive pathways (connections between inner 152 and 120) in the package substrate 151 (Fig. 3A-3C); wherein the metal trace 131 is parallel and proximate to the periphery of the interposer (fig. 3C).
Chen et al. and Fan are analogous art because they both are directed Fan et al. and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Fan et al. in order to prevent contaminants.
As for claim 3, Chen et al. and Fan et al. disclose the microelectronic assembly of claim 1, Chen et al. further disclose: the first dielectric 76” material is mold compound [0045], and the second dielectric material is one of (i) polyimide and (ii) a compound of silicon and at least one of carbon, nitrogen, and oxygen [0026].
As for claim 4, Chen et al. and Fan et al. disclose the microelectronic assembly of claim 1, Fan further discloses the edge ring 130 further comprises a plurality of metal traces 131 stacked with the metal trace to form a set of stacked metal traces in the RDL, the plurality of metal vias 132 and the set of stacked metal traces forming a mesh structure through a cross- section of the RDL (Fig. 3C).
As for claim 5, Chen et al. and Fan et al. disclose the microelectronic assembly of claim 1, Fan further discloses the RDL 125/110/161/151 further comprises a plurality of layers, metal traces of the set of stacked metal traces 131 are between layers of the plurality of layers, and metal vias 132 in the plurality of metal vias couple the metal traces in the set of stacked metal traces through the plurality of layers (Fig. 3C).
As for claim 6, Chen et al. and Fan et al. disclose the microelectronic assembly of claim 1, Fan further discloses at least one layer 151 of the plurality of layers comprises the second dielectric material, and another layer of the plurality of layers comprises a third dielectric material 110/161 different from the first dielectric material and the second dielectric material (Fig. 3C, [0020], [0027], [0032]).
As for claim 7, Chen et al. and Fan et al. disclose the microelectronic assembly of claim 1, Chen et al. further disclose conductive pillar 72 is coupled with the metal trace 66 (Fig. 3N).
As for claim 8, Chen et al. and Fan et al. disclose the microelectronic assembly of claim 7, Chen et al. further disclose:
the RDL 68 is a first RDL,
the interposer further comprises a third layer 78, wherein the third layer 78 is a second RDL, the second RDL 78 comprising the second dielectric material [0033], and the first layer 76” of the interposer is between the first RDL 68 and the second RDL 78.
As for claim 21, Chen et al. and Fan et al. disclose the microelectronic assembly of claim 1, Chen et al. further disclose conductive interconnects 18 between and coupled with the die and the RDL (fig. 3N), wherein a portion of the conductive pillar 72 is in a plane with the conductive interconnects, wherein the plane is substantially parallel with the RDL (fig. 3N of Chen et al.).
As for claim 22, Chen et al. and Fan et al. disclose the microelectronic assembly of claim 9, Chen et al. further disclose the conductive pillar 72 is between the second layer and the third layer (Fig. 3N), and the conductive pillar 72 is coupled with the first trace and the second trace (Fig. 3N).
As for claim 23, Chen et al. and Fan et al. disclose the microelectronic assembly of claim 22, except a first metal via of the plurality of metal vias has a first width, a second metal via of the plurality of metal vias has a second width, the conductive pillar has a third width, and the third width is greater than the first width and greater than the second width.
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of a via/plug, pad, trace/wiring, DL, solder ball/bump, etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Fan et al. and further in view of Chen et al. (US 2021/0098409).
As for claim 11, Chen et al. and Fan et al. disclosed the microelectronic assembly of claim 1, except further comprising a fiducial mark proximate to a corner of the edge ring.
Chen et al. disclose in Figs. 6A-6C and the related text a fiducial mark 664A proximate to a corner of the edge ring 664.
Chen et al. and Chen et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Chen et al. in order to provide alignment calibration (Chen et al.: [0037]).
Claim(s) 13-14, 16 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun Zhou et al. (US 2020/0335443, as disclosed in previous office action) in view of Fan et al..
As for claim 13, Sun Zhou et al. disclose in Fig. 3 and the related text an interposer in a microelectronic assembly, the interposer comprising:
a core 330 of a first dielectric material [0028], the core having a first (upper) side and an opposing second (lower) side;
a die 340b in the core, wherein the die 340 is at least partially surrounded by the first dielectric material 330 (fig. 3);
a conductive pillar 311/312/321/322/313/323 through the core between the first side and the second side (fig. 3);
an RDL 332 in contact with the first side of the core 330 (fig. 3), the RDL 332 comprising a second dielectric material [0047] different from the first dielectric material [0028]; and
Sun Zhou et al. do not disclose edge ring comprises: a metal trace proximate to the first side of the core along of a periphery of the interposer, the metal trace in contact with the second dielectric material, and a plurality of metal vias through the RDL, the plurality of metal vias in contact with the metal trace; and a bond pad couple with the metal trace of the edge ring through a metal via of the plurality of metal vias.
Fan discloses in Figs. 2-3C and the related text an edge ring 130 comprises: a metal trace 131 proximate to the first side of the core 125 along of a periphery of the interposer, the metal trace 131 in contact with the second dielectric material 151, and a plurality of metal vias 132 through the RDL, the plurality of metal vias 132 in contact with the metal trace 131; and a bond pad 152/153 couple with the metal trace of the edge ring through a metal via of the plurality of metal vias (Fig. 3C).
Sun Zhou et al. and Fan are analogous art because they both are directed Fan et al. and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sun Zhou et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Sun Zhou et al. to include the limitations as taught by Fan et al. in order to prevent contaminants.
As for claim 14, Sun Zhou et al. and Fan disclose the interposer of claim 13, Sun Zhou et al. further disclose a plurality of metal pillars in the core 330, the plurality of metal pillars in contact with at least one of: the metal trace and the plurality of metal vias (Fig. 3).
As for claim 16, Sun Zhou et al. and Fan disclose the interposer of claim 13, Sun Zhou et al. further disclose the interposer is coupled to a package substrate 360 on the first side (fig. 3), and the interposer is coupled to an IC die 340a on the second side (fig. 3).
As for claim 26, Sun Zhou et al. and Fan disclose the interposer of claim 13, Fan further discloses the RDL is a first RDL, the metal trace 131 is a first metal trace, the plurality of metal vias 132 is a first plurality of metal vias, and the interposer further comprises: a third layer 110, wherein the third layer is a second RDL, the second RDL comprising the second dielectric material, the core is between the first RDL and the second RDL (Fig. 3C), and the edge ring 130 further comprises: a second metal trace (lower 152) in the second RDL parallel to the first metal trace, the second metal trace in contact with the second dielectric material of the second RDL, and a second plurality of metal vias 153 through the second RDL in contact with the second metal trace (Fig. 3C).
Claim(s) 24-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Chun et al. (US 2020/0066625).
As for claim 24, Chen et al. disclose in Figs. 3A-3N and the related text a microelectronic assembly, comprising:
an interposer 68/76”/78 comprising:
a first layer 76” comprising a first dielectric material [0045], a second layer 68 comprising a second dielectric material [0026] that is different from the first dielectric material, wherein the second layer is a first redistribution layer (RDL), and a third layer 78 comprising the second dielectric material [0033], wherein the third layer 78 is a second RDL;
an integrated circuit (IC) die 200 over and coupled with the interposer;
a substrate 82/86/88 below and coupled with a face of the interposer (fig. 3N);
a first structure comprising a first conductive trace 66 and a first conductive via (lower portion 72) in the first RDL 68 along a periphery of the interposer (fig. 3N);
a second structure comprising a second conductive trace (upper 80) and a second conductive via (lower 80) in the second RDL 78 along the periphery (fig. 3N);
a conductive pillar (upper portion 72) through the first layer and extending between the first RDL and the second RDL (fig. 3N), wherein the conductive pillar (upper portion 72) is coupled with the first conductive trace and the second conductive trace, and wherein the conductive pillar (upper portion 72) has a greater width than the first conductive via (Fig. 3N);
a bond pad 94 at the face of the interposer; and
a conductive interconnect 92 between and coupled with the bond pad 94 and the substrate 82, wherein: the bond pad 94 is coupled with the first conductive trace 66.
Chen et al. do not disclose the conductive interconnect is conductively isolated from conductive pathways in the substrate.
Chun et al. teach in Fig. 1A and the related text a conductive interconnect (left UBM) is conductively isolated from conductive pathways (from 108 to UBM) in the substrate 112/118 (Fig. 1A).
Chen et al. and Chun et al. are analogous art because they both are directed Fan et al. and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Chun et al. in order to
As for claim 25, Chen et al. disclose the microelectronic assembly of claim 24, further comprising: a die 21/22 in the first layer 76”, wherein the die 21/22 is coupled with the first RDL and the second RDL (fig. 3N).
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached Monday-Thursday (9am-4pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRANG Q TRAN/ Primary Examiner, Art Unit 2811