DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/24/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Masuda et al. [U.S. Pub. No. 2016/0233845].
Regarding Claim 1, Masuda et al. shows a multilayer electronic component (Figs. 1A-2A) comprising:
a first port (14a);
a second port (14b) that passes a signal input to the first port (see Fig. 1A, Paragraph [0006], [0082]);
a first inductor (L1) and a second inductor (L2) that are provided between the first port (14a) and the second port (14b) in a circuit configuration (see Fig. 1A); and
a stack (see Fig. 2A) that includes a plurality of dielectric layers (16a-16h, Paragraph [0025]) and a plurality of conductors (18a-18f, 22b-22d) stacked together (see Fig. 2A), the stack being intended to integrate the first port (14a), the second port (14b), the first inductor (L1), and the second inductor (L2), wherein:
the first inductor (L1) has a first end (left end) closest to the first port (14a) in the circuit configuration (see Fig. 1A), and a second end (right end) opposite to the first end (see Fig. 1A);
the second end (right end) of the first inductor (L1) is directly connected to one end (left end) of the second inductor (L2) in the circuit configuration (see Fig. 1A, right end of element L1 is directly connected to left end of element L2);
the stack includes a first inductor conductor (18a-18f) constituting the first inductor (L1, Paragraph [0026]), and a second inductor conductor (22b-22d, v4-v6) constituting the second inductor (L2, Paragraph [0039]);
the first inductor conductor (18a-18f) is wound about an axis extending in a first direction (top-bottom direction) and the first direction is parallel to a stacking direction of the plurality of dielectric layers (see Fig. 2A, elements 18-18f is wound about an axis extending in a top-bottom direction and the top-bottom direction is parallel to a stacking direction of elements 16a-16h);
the second inductor conductor (22b-22d, v4-v6) is wound about an axis extending in a second direction (front-rear direction) intersecting the first direction and the stacking direction (see Fig. 2A, elements 22b-22d, v4-v6 is wound about an axis extending in a front-rear direction intersecting the top-bottom direction and the stacking direction);
the first inductor conductor includes a plurality of first conductor layers (18a-18f) that are arranged at different positions with each other in the stacking direction (see Fig. 2A, elements 18a-18f are arranged at different positions with each other in the stacking direction); and
a number of the plurality of first conductor layers is three or more (see Fig. 2A, a number of elements 18a-18f is three or more).
Regarding Claim 2, Masuda et al. shows the first direction and the second direction are orthogonal to each other (see Fig. 2A, top-bottom direction and front-rear direction are orthogonal to each other).
Regarding Claim 4, Masuda et al. shows (Figs. 1A-2A) the first inductor (L1) and the second inductor (L2) are provided in series (see Figs. 1A-2A, Paragraphs [0020], [0060]) in a path connecting the first port (14a) and the second port (14b, see Figs. 1A-2A).
Regarding Claim 5, Masuda et al. shows a first resonator (LC1, LC2 combined) provided between the first port (14a) and the second port (14b) in the circuit configuration, wherein the first inductor (L1) and the second inductor (L2) are included in the first resonator (see Fig. 1A).
Regarding Claim 12, Masuda et al. shows the second inductor conductor (22b, 22d) includes a second conductor layer (conductor layer having elements 22b, 22d) and a plurality of inductor through holes (v4, v5, v6, v7); and the stack further includes a connection conductor layer (22a) connected to at least one of the plurality of inductor through holes (v4), and a connection through hole (v3) connecting the connection conductor layer (22a) and the plurality of first conductor layers (18e, 18f, see Figs. 1A-2A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. in view of Sakata [JP 2005-191256].
Regarding Claim 4, Masuda et al. shows the claimed invention as applied above.
In addition, Sakata shows (Fig. 4) the first inductor (2) and the second inductor (3) are provided in series (see Fig. 4, Paragraph [0050]) in a path connecting the first port (right end) and the second port (left end, see Fig. 4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the first inductor and the second inductor are provided in series in a path connecting the first port and the second port as taught by Sakata for the electronic component as disclosed by Masuda et al. to achieve desirable coupling, inductance, and impedance characteristics suitable for signal waveform shaping and signal noise removal and reduced stray capacitance (Paragraphs [0038]-[0039]).
Regarding Claim 12, Masuda et al. shows the claimed invention as applied above.
In addition, Sakata shows the second inductor conductor (12) includes a second conductor layer (conductor layer having element 12) and a plurality of inductor through holes (13); and the stack further includes a connection conductor layer (21) connected to at least one of the plurality of inductor through holes (13), and a connection through hole (top element 7) connecting the connection conductor layer (21) and the plurality of first conductor layers (6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the second inductor conductor includes a second conductor layer and a plurality of inductor through holes; and the stack further includes a connection conductor layer connected to at least one of the plurality of inductor through holes, and a connection through hole connecting the connection conductor layer and the plurality of first conductor layers as taught by Sakata for the electronic component as disclosed by Masuda et al. to achieve desirable coupling, inductance, and impedance characteristics suitable for signal waveform shaping and signal noise removal and reduced stray capacitance (Paragraphs [0038]-[0039]).
Claim(s) 5-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. in view of Tanaka [U.S. Pub. No. 2023/0238936].
Regarding Claim 5, Masuda et al. shows the claimed invention as applied above.
In addition, Tanaka shows a first resonator (HB or FLT2) provided between the first port and the second port in the circuit configuration (see Fig. 2), wherein the first inductor (L23 or L21) and the second inductor (L24) are included in the first resonator (see Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a first resonator provided between the first port and the second port in the circuit configuration, wherein the first inductor and the second inductor are included in the first resonator as taught by Tanaka for the electronic component as disclosed by Masuda et al. to achieve desirable coupling, inductance, and impedance characteristics such as to improve bandpass characteristics (Paragraphs [0002]) and improvement of the Q factor (Paragraph [0074]).
Regarding Claim 6, Tanaka shows a third port (T1); and
a second resonator (LB or FLT1) provided between the first port and the third port in the circuit configuration (see Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a third port; and a second resonator provided between the first port and the third port in the circuit configuration as taught by Tanaka for the electronic component as disclosed by Masuda et al. to achieve desirable coupling, inductance, and impedance characteristics such as to obtain desirable bandpass characteristics (Paragraphs [0002]), improvement of insertion loss for Q factor (Paragraph [0074]), and reducing or preventing deterioration in filter characteristic (Paragraph [0079]).
Regarding Claim 7, Tanaka shows either one of the second (T2) and third ports is a first signal port that selectively passes a first signal of a frequency within a first passband (Paragraph [0038], 1427 MHz to 2690 MHz); and the other of the second and third (T1) ports is a second signal port that selectively passes a second signal of a frequency within a second passband (Paragraph [0038], 0 to 960 MHz) lower than the first passband (Paragraph [0038]).
Regarding Claim 8, Tanaka shows the second port (T2) is the first signal port (element T2 can be considered as the first signal port), and the third port (T1) is the second signal port (element T1 can be considered as the second signal port).
Regarding Claim 9, Tanaka shows the stack further includes a second resonator conductor (L12, C12 combined) constituting the second resonator (LB or FLT1),
the first inductor conductor (L23 or L21) is a horizontal inductor conductor (see Figs. 1-5) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-5, element L23 or L21 is a horizontal inductor conductor wound about an axis extending in a direction parallel to the stacking direction);
the second inductor conductor (L24) is a vertical inductor conductor (see Figs. 1-5) wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-5, element L24 is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction); and
the vertical inductor conductor (L24) is located farther from the second resonator conductor (LB or FLT1) than is the horizontal inductor conductor (L23 or L21, see Fig. 5, element L24 is located farther from element L12 than is element L23).
Regarding Claim 10, Masuda et al. shows the stack has a bottom surface (bottom surface, see Figs. 1B-2A) and a top surface (top surface) located at both ends of the plurality of dielectric layers in the stacking direction (see Figs. 1B-2A), and four side surfaces (front, rear, right, and left surfaces, see Figs. 1B-2A) connecting the bottom surface and the top surface (see Figs. 1B-2A);
the bottom surface and the top surface each have a rectangular shape extending in one direction (see Figs. 1B-2A, bottom surface and top surface each have a rectangular shape extending in one direction, Paragraphs [0024]-[0025]);
the four side surfaces include a first side surface (rear surface according to the front-rear direction, see Figs. 1B-2A) and a second side surface (front surface according to the front-rear direction, see Figs. 1B-2A) located at both longitudinal ends of the rectangular shape (see Figs. 1B-2A);
the first inductor conductor (18-18f) is a horizontal inductor conductor (L1) wound about an axis extending in a direction parallel to the stacking direction (see Fig. 2A, element L1 is a horizontal inductor conductor wound about an axis extending in a top-bottom direction parallel to the stacking direction);
the second inductor conductor (22b-22d, v4-v6) is a vertical inductor conductor (L2) wound about an axis extending in a direction orthogonal to the stacking direction (see Fig. 2A, element L2 is a vertical inductor conductor wound about an axis extending in a front-rear direction orthogonal to the stacking direction);
the vertical inductor conductor (L2) is located closer to the first side surface than to the second side surface (see Fig. 2A, element 22d of element L2 is located closer to the rear surface than to the front surface); and
a distance from the vertical inductor conductor to the first side surface is smaller than a distance from the horizontal inductor conductor to the first side surface (see Fig. 2A, a distance from element L2 to the rear surface is smaller than a distance from element L1 to the rear surface).
In addition, Tanaka shows the stack has a bottom surface (bottom surface, see Fig. 3) and a top surface (top surface, see Fig. 3) located at both ends of the plurality of dielectric layers in the stacking direction (see Fig. 3), and four side surfaces (see Fig. 3, left, right, front, and back surfaces) connecting the bottom surface and the top surface (see Fig. 3);
the bottom surface and the top surface each have a rectangular shape extending in one direction (see Fig. 3, bottom surface and top surface each have a rectangular shape extending in one direction, Paragraph [0040]);
the four side surfaces include a first side surface (right surface on the X-direction, see Figs. 3 and 5) and a second side surface (left surface on the X-direction, see Figs. 3 and 5) located at both longitudinal ends of the rectangular shape (see Figs. 3 and 5);
the first inductor conductor (L23 or L21) is a horizontal inductor conductor (see Figs. 1-5) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-5, element L23 or L21 is a horizontal inductor conductor wound about an axis extending in a direction parallel to a stacking direction);
the second inductor conductor (L24) is a vertical inductor conductor (see Figs. 1-5) wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-5, element L24 is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction);
the vertical inductor conductor (L24) is located closer to the first side surface than to the second side surface (see Figs. 3 and 5, element L24 is located closer to the right surface than the left); and
a distance from the vertical inductor conductor (L24) to the first side surface is smaller than a distance from the horizontal inductor conductor (L23 or L21) to the first side surface (see Figs. 3 and 5, a distance from element L24 to the right surface is smaller than a distance from element L23 or L21 to the right surface).
Regarding Claim 11, Masuda et al. shows the claimed invention as applied above but does not show the second inductor conductor includes at least one second conductor layer and a plurality of through holes; a number of the plurality of first conductor layers is equal to or more than a number of the at least one second conductor layer; the plurality of dielectric layers include a plurality of first dielectric layers including the plurality of first conductor layers respectively formed thereon, and a plurality of second dielectric layers not including the plurality of first conductor layers formed thereon; the plurality of through holes include a plurality of first through holes formed in the plurality of first dielectric layers respectively, and a plurality of second through holes formed in the plurality of second dielectric layers respectively.
Tanaka shows the second inductor conductor (PL6A, PL6B, PL6C) includes at least one second conductor layer (one conductor layer having elements PL6A, PL6C and another conductor layer having element PL6B) and a plurality of through holes (VL6A, VL6B, VL6C);
a number of the plurality of first conductor layers is equal to or more than a number of the at least one second conductor layer (a number of conductor layers having elements PL5A, PL5B, PL5C or PL3, PL3A, PL3B is equal to or more than a number of one conductor layer having elements PL6A, PL6C and another conductor layer having element PL6B);
the plurality of dielectric layers (LY1-LY17) include a plurality of first dielectric layers (LY3-LY5 or LY2-LY4) including the plurality of first conductor layers respectively (conductor layers having elements PL5A, PL5B, PL5C or PL3, PL3A, PL3B, respectively) formed thereon (see Figs. 3-5), and a plurality of second dielectric layers (LY6-LY16 or LY5, LY7) not including the plurality of first conductor layers formed thereon (see Figs. 3-5);
the plurality of through holes (VL6A, VL6B) include a plurality of first through holes formed in the plurality of first dielectric layers respectively (see Figs. 3-5, there are a portion of elements VL6A, VL6B formed in elements LY3-LY5 or LY2-LY4), and a plurality of second through holes formed in the plurality of second dielectric layers respectively (see Figs. 3-5, there are another portion of elements VL6A, VL6B and element VL6C formed in elements LY6-LY16 or LY5, LY7).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the second inductor conductor includes at least one second conductor layer and a plurality of through holes; a number of the plurality of first conductor layers is equal to or more than a number of the at least one second conductor layer; the plurality of dielectric layers include a plurality of first dielectric layers including the plurality of first conductor layers respectively formed thereon, and a plurality of second dielectric layers not including the plurality of first conductor layers formed thereon; the plurality of through holes include a plurality of first through holes formed in the plurality of first dielectric layers respectively, and a plurality of second through holes formed in the plurality of second dielectric layers respectively as taught by Tanaka for the electronic component as disclosed by Masuda et al. to achieve desirable coupling, inductance, and impedance characteristics such as to obtain desirable bandpass characteristics (Paragraphs [0002]), improvement of insertion loss for Q factor (Paragraph [0074]), and reducing or preventing deterioration in filter characteristic (Paragraph [0079]).
Regarding Claim 12, Masuda et al. shows the claimed invention as applied above.
In addition, Tanaka shows the second inductor conductor (PL6A, PL6B, PL6C) includes a second conductor layer (conductor layer having element PL6B) and a plurality of inductor through holes (VL6A, VL6B, VL6); and
the stack further includes a connection conductor layer (PL5, PL6 combined) connected to at least one of the plurality of inductor through holes (VL6), and a connection through hole (VL5B) connecting the connection conductor layer (PL5, PL6 combined) and the plurality of first conductor layers (conductor layers having elements PL5A, PL5B, PL5C).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the second inductor conductor includes a second conductor layer and a plurality of inductor through holes; and the stack further includes a connection conductor layer connected to at least one of the plurality of inductor through holes, and a connection through hole connecting the connection conductor layer and the plurality of first conductor layers as taught by Tanaka for the electronic component as disclosed by Masuda et al. to achieve desirable coupling, inductance, and impedance characteristics such as to obtain desirable bandpass characteristics (Paragraphs [0002]), improvement of insertion loss for Q factor (Paragraph [0074]), and reducing or preventing deterioration in filter characteristic (Paragraph [0079]).
Claim(s) 5-8 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. in view of Kaminishi [U.S. Pub. No. 2018/0006625].
Regarding Claim 5, Masuda et al. shows the claimed invention as applied above.
In addition, Kaminishi shows a first resonator (HB) provided between the first port (14a) and the second port (14b) in the circuit configuration (see Fig. 1), wherein the first inductor (L2) and the second inductor (L1 or L5) are included in the first resonator (HB, see Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a first resonator provided between the first port and the second port in the circuit configuration, wherein the first inductor and the second inductor are included in the first resonator as taught by Kaminishi for the electronic component as disclosed by Masuda et al. to achieve desirable coupling, inductance, and impedance characteristics.
Regarding Claim 6, Kaminishi shows a third port (14c); and
a second resonator (LB) provided between the first port (14a) and the third port (14c) in the circuit configuration (see Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a third port; and a second resonator provided between the first port and the third port in the circuit configuration as taught by Kaminishi for the electronic component as disclosed by Masuda et al. to achieve desirable operating characteristics and excellent in being able to significantly reduce or prevent a situation in which the routing of conductors becomes complex (Paragraphs [0040], [0107]).
Regarding Claim 7, Kaminishi shows either one of the second (14b) and third ports is a first signal port that selectively passes a first signal of a frequency within a first passband (Paragraph [0033], 5 GHz); and the other of the second and third (14c) ports is a second signal port that selectively passes a second signal of a frequency within a second passband (Paragraph [0038], 2 GHz) lower than the first passband (Paragraphs [0033], [0038], [0040]).
Regarding Claim 8, Kaminishi shows the second port (14b) is the first signal port (element 14b can be considered as the first signal port), and the third port (14c) is the second signal port (element 14c can be considered as the second signal port).
Regarding Claim 10, Masuda et al. shows the stack has a bottom surface (bottom surface, see Figs. 1B-2A) and a top surface (top surface) located at both ends of the plurality of dielectric layers in the stacking direction (see Figs. 1B-2A), and four side surfaces (front, rear, right, and left surfaces, see Figs. 1B-2A) connecting the bottom surface and the top surface (see Figs. 1B-2A);
the bottom surface and the top surface each have a rectangular shape extending in one direction (see Figs. 1B-2A, bottom surface and top surface each have a rectangular shape extending in one direction, Paragraphs [0024]-[0025]);
the four side surfaces include a first side surface (rear surface according to the front-rear direction, see Figs. 1B-2A) and a second side surface (front surface according to the front-rear direction, see Figs. 1B-2A) located at both longitudinal ends of the rectangular shape (see Figs. 1B-2A);
the first inductor conductor (18-18f) is a horizontal inductor conductor (L1) wound about an axis extending in a direction parallel to the stacking direction (see Fig. 2A, element L1 is a horizontal inductor conductor wound about an axis extending in a top-bottom direction parallel to the stacking direction);
the second inductor conductor (22b-22d, v4-v6) is a vertical inductor conductor (L2) wound about an axis extending in a direction orthogonal to the stacking direction (see Fig. 2A, element L2 is a vertical inductor conductor wound about an axis extending in a front-rear direction orthogonal to the stacking direction);
the vertical inductor conductor (L2) is located closer to the first side surface than to the second side surface (see Fig. 2A, element 22d of element L2 is located closer to the rear surface than to the front surface); and
a distance from the vertical inductor conductor to the first side surface is smaller than a distance from the horizontal inductor conductor to the first side surface (see Fig. 2A, a distance from element L2 to the rear surface is smaller than a distance from element L1 to the rear surface).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. in view of Kaminishi as applied to claims 5-6 above, and further in view of Tanaka [U.S. Pub. No. 2023/0238936].
Regarding Claim 9, Masuda et al. in view of Kaminishi shows the claimed invention as applied above but does not show the stack further includes a second resonator conductor constituting the second resonator; the first inductor conductor is a horizontal inductor conductor wound about an axis extending in a direction parallel to the stacking direction; the second inductor conductor is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction; and the vertical inductor conductor is located farther from the second resonator conductor than is the horizontal inductor conductor.
Tanaka shows the stack further includes a second resonator conductor (L12, C12 combined) constituting the second resonator (LB or FLT1),
the first inductor conductor (L23 or L21) is a horizontal inductor conductor (see Figs. 1-5) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-5, element L23 or L21 is a horizontal inductor conductor wound about an axis extending in a direction parallel to the stacking direction);
the second inductor conductor (L24) is a vertical inductor conductor (see Figs. 1-5) wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-5, element L24 is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction); and
the vertical inductor conductor (L24) is located farther from the second resonator conductor (LB or FLT1) than is the horizontal inductor conductor (L23 or L21, see Fig. 5, element L24 is located farther from element L12 than is element L23).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the stack further includes a second resonator conductor constituting the second resonator; the first inductor conductor is a horizontal inductor conductor wound about an axis extending in a direction parallel to the stacking direction; the second inductor conductor is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction; and the vertical inductor conductor is located farther from the second resonator conductor than is the horizontal inductor conductor as taught by Tanaka for the electronic component as disclosed by Masuda et al. in view of Kaminishi to achieve desirable coupling, inductance, and impedance characteristics such as to obtain desirable bandpass characteristics (Paragraphs [0002]), improvement of insertion loss for Q factor (Paragraph [0074]), and reducing or preventing deterioration in filter characteristic (Paragraph [0079]).
Regarding Claim 10, Masuda et al. in view of Kaminishi shows the claimed invention as applied above.
In addition, Tanaka shows the stack has a bottom surface (bottom surface, see Fig. 3) and a top surface (top surface, see Fig. 3) located at both ends of the plurality of dielectric layers in the stacking direction (see Fig. 3), and four side surfaces (see Fig. 3, left, right, front, and back surfaces) connecting the bottom surface and the top surface (see Fig. 3);
the bottom surface and the top surface each have a rectangular shape extending in one direction (see Fig. 3, bottom surface and top surface each have a rectangular shape extending in one direction, Paragraph [0040]);
the four side surfaces include a first side surface (right surface on the X-direction, see Figs. 3 and 5) and a second side surface (left surface on the X-direction, see Figs. 3 and 5) located at both longitudinal ends of the rectangular shape (see Figs. 3 and 5);
the first inductor conductor (L23 or L21) is a horizontal inductor conductor (see Figs. 1-5) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-5, element L23 or L21 is a horizontal inductor conductor wound about an axis extending in a direction parallel to a stacking direction);
the second inductor conductor (L24) is a vertical inductor conductor (see Figs. 1-5) wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-5, element L24 is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction);
the vertical inductor conductor (L24) is located closer to the first side surface than to the second side surface (see Figs. 3 and 5, element L24 is located closer to the right surface than the left); and
a distance from the vertical inductor conductor (L24) to the first side surface is smaller than a distance from the horizontal inductor conductor (L23 or L21) to the first side surface (see Figs. 3 and 5, a distance from element L24 to the right surface is smaller than a distance from element L23 or L21 to the right surface).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the stack has a bottom surface and a top surface located at both ends of the plurality of dielectric layers in the stacking direction, and four side surfaces connecting the bottom surface and the top surface; the bottom surface and the top surface each have a rectangular shape extending in one direction; the four side surfaces include a first side surface and a second side surface located at both longitudinal ends of the rectangular shape; the first inductor conductor is a horizontal inductor conductor wound about an axis extending in a direction parallel to the stacking direction; the second inductor conductor is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction; the vertical inductor conductor is located closer to the first side surface than to the second side surface; and a distance from the vertical inductor conductor to the first side surface is smaller than a distance from the horizontal inductor conductor to the first side surface as taught by Tanaka for the electronic component as disclosed by Masuda et al. in view of Kaminishi to achieve desirable coupling, inductance, and impedance characteristics such as to obtain desirable bandpass characteristics (Paragraphs [0002]), improvement of insertion loss for Q factor (Paragraph [0074]), and reducing or preventing deterioration in filter characteristic (Paragraph [0079]).
Kaminishi clearly shows the bottom surface and the top surface each have a rectangular shape extending in one direction (see Fig. 2A, bottom surface and top surface each have a rectangular shape extending in one direction, Paragraph [0043]); the four side surfaces include a first side surface (left or right surface, see Fig. 2A) and a second side surface (right or left surface, see Fig. 2A) located at both longitudinal ends of the rectangular shape (see Fig. 2A, Paragraph [0043]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masuda et al. in view of Tanaka [U.S. Pub. No. 2021/0036676] (hereinafter as “Tanka ‘676”).
Regarding Claim 12, Masuda et al. shows the claimed invention as applied above.
In addition, Tanka ‘676 shows the second inductor conductor (L24) includes a second conductor layer (bottom conductor layer having element L24) and a plurality of inductor through holes (through holes of element L24); and the stack further includes a connection conductor layer (PB2) connected to at least one of the plurality of inductor through holes (one through hole of element L24), and a connection through hole (one through hole of element L23) connecting the connection conductor layer (PB2) and the plurality of first conductor layers (conductor layers having element L23, see Figs. 1-5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the second inductor conductor includes a second conductor layer and a plurality of inductor through holes; and the stack further includes a connection conductor layer connected to at least one of the plurality of inductor through holes, and a connection through hole connecting the connection conductor layer and the plurality of first conductor layers as taught by Tanka ‘676 for the electronic component as disclosed by Masuda et al. to significantly improve attenuation characteristics while significantly reducing or preventing an increase in loss of each filter (Paragraph [0007]).
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Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2 and 4-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/TSZFUNG J CHAN/Primary Examiner, Art Unit 2837
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