DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the plurality of first conductor layers" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the plurality of first conductor layers" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 and 4-12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tanaka [U.S. Pub. No. 2023/0238936].
Regarding Claim 1, Tanaka shows a multilayer electronic component (Figs. 1-5) comprising:
a first port (TA);
a second port (T2) that passes a signal input to the first port (see Figs. 1-2, Paragraphs [0031], [0042], [0068]);
a first inductor (L23 or L21) and a second inductor (L24) that are provided between the first port (TA) and the second port (T2) in a circuit configuration (see Figs. 1-2); and
a stack (see Figs. 3-4) that includes a plurality of dielectric layers (LY1-LY17) and a plurality of conductors (conductors at elements LY2-LY8) stacked together (see Figs. 3-4), the stack being intended to integrate the first port (TA), the second port (T2), the first inductor (L23 or L21), and the second inductor (L24, see Figs. 1-5), wherein:
the first inductor (L23 or L21) has a first end (bottom end of element L23 or left end of element L21) closest to the first port (TA) in the circuit configuration (see Figs. 1-2, bottom end of element L23 or left end of element L21 closest to element TA than right end of element L24), and a second end (upper end of element L23 or right end of element L21) opposite to the first end (see Figs. 1-2);
the second end (upper end of element L23 or right end of element L21) of the first inductor is connected to one end (left end of element L24) of the second inductor (see Figs. 1-2);
the stack includes a first inductor conductor (PL5A, PL5B, PL5C or PL3, PL3A, PL3B) constituting the first inductor (L23 or L21, see Figs. 3-5), and a second inductor conductor (PL6A, PL6B, PL6C) constituting the second inductor (L24, see Figs. 3-5);
the first inductor conductor (PL5A, PL5B, PL5C or PL3, PL3A, PL3B) is wound about an axis extending in a first direction (Z-direction) and the first direction is parallel to a stacking direction of the plurality of dielectric layers (see Figs. 3-5, elements PL5A, PL5B, PL5C or PL3, PL3A, PL3B is wound about an axis extending in a Z-direction and the Z-direction is parallel to a stacking direction of elements LY1-LY17); and
the second inductor conductor (PL6A, PL6B, PL6C) is wound about an axis extending in a second direction (X-direction) intersecting the first direction and the stacking direction (see Figs. 3-5, elements PL6A, PL6B, PL6C is wound about an axis extending in a X-direction intersecting the Z-direction and the stacking direction); and
the first inductor conductor (PL5A, PL5B, PL5C or PL3, PL3A, PL3B) includes three or more conductor layers (conductor layers having elements PL5A, PL5B, PL5C or PL3, PL3A, PL3B) that are arranged at different positions with each other in the stacking direction (see Figs. 3-5, elements PL5A, PL5B, PL5C or PL3, PL3A, PL3B are arranged at different positions with each other in the stacking direction).
Regarding Claim 2, Tanaka shows the first direction and the second direction are orthogonal to each other (see Figs. 1-5, the Z-direction and the X-direction are orthogonal to each other).
Regarding Claim 4, Tanaka shows the first inductor (L23 or L21) and the second inductor (L24) are provided in series in a path connecting the first port and the second port (see Figs. 1-5, element L23 or L21 and element L24 are provided in series in a path connecting element TA and element T2).
Regarding Claim 5, Tanaka shows a first resonator (HB or FLT2) provided between the first port and the second port in the circuit configuration (see Fig. 2), wherein the first inductor (L23 or L21) and the second inductor (L24) are included in the first resonator (see Fig. 2).
Regarding Claim 6, Tanaka shows a third port (T1); and
a second resonator (LB or FLT1) provided between the first port and the third port in the circuit configuration (see Fig. 1).
Regarding Claim 7, Tanaka shows either one of the second (T2) and third ports is a first signal port that selectively passes a first signal of a frequency within a first passband (Paragraph [0038], 1427 MHz to 2690 MHz); and the other of the second and third (T1) ports is a second signal port that selectively passes a second signal of a frequency within a second passband (Paragraph [0038], 0 to 960 MHz) lower than the first passband (Paragraph [0038]).
Regarding Claim 8, Tanaka shows the second port (T2) is the first signal port (element T2 can be considered as the first signal port), and the third port (T1) is the second signal port (element T1 can be considered as the second signal port).
Regarding Claim 9, Tanaka shows the stack further includes a second resonator conductor (L12, C12 combined) constituting the second resonator (LB or FLT1),
the first inductor conductor (L23 or L21) is a horizontal inductor conductor (see Figs. 1-5) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-5, element L23 or L21 is a horizontal inductor conductor wound about an axis extending in a direction parallel to the stacking direction);
the second inductor conductor (L24) is a vertical inductor conductor (see Figs. 1-5) wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-5, element L24 is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction); and
the vertical inductor conductor (L24) is located farther from the second resonator conductor (LB or FLT1) than is the horizontal inductor conductor (L23 or L21, see Fig. 5, element L24 is located farther from element L12 than is element L23).
Regarding Claim 10, Tanaka shows the stack has a bottom surface (bottom surface, see Fig. 3) and a top surface (top surface, see Fig. 3) located at both ends of the plurality of dielectric layers in the stacking direction (see Fig. 3), and four side surfaces (see Fig. 3, left, right, front, and back surfaces) connecting the bottom surface and the top surface (see Fig. 3);
the bottom surface and the top surface each have a rectangular shape extending in one direction (see Fig. 3, bottom surface and top surface each have a rectangular shape extending in one direction, Paragraph [0040]);
the four side surfaces include a first side surface (right surface on the X-direction, see Figs. 3 and 5) and a second side surface (left surface on the X-direction, see Figs. 3 and 5) located at both longitudinal ends of the rectangular shape (see Figs. 3 and 5);
the first inductor conductor (L23 or L21) is a horizontal inductor conductor (see Figs. 1-5) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-5, element L23 or L21 is a horizontal inductor conductor wound about an axis extending in a direction parallel to a stacking direction);
the second inductor conductor (L24) is a vertical inductor conductor (see Figs. 1-5) wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-5, element L24 is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction);
the vertical inductor conductor (L24) is located closer to the first side surface than to the second side surface (see Figs. 3 and 5, element L24 is located closer to the right surface than the left); and
a distance from the vertical inductor conductor (L24) to the first side surface is smaller than a distance from the horizontal inductor conductor (L23 or L21) to the first side surface (see Figs. 3 and 5, a distance from element L24 to the right surface is smaller than a distance from element L23 or L21 to the right surface).
Regarding Claim 11, Tanaka shows the second inductor conductor (PL6A, PL6B, PL6C) includes at least one second conductor layer (one conductor layer having elements PL6A, PL6C and another conductor layer having element PL6B) and a plurality of through holes (VL6A, VL6B, VL6C);
a number of the plurality of first conductor layers is equal to or more than a number of the at least one second conductor layer (a number of conductor layers having elements PL5A, PL5B, PL5C or PL3, PL3A, PL3B is equal to or more than a number of one conductor layer having elements PL6A, PL6C and another conductor layer having element PL6B);
the plurality of dielectric layers (LY1-LY17) include a plurality of first dielectric layers (LY3-LY5 or LY2-LY4) including the plurality of first conductor layers respectively (conductor layers having elements PL5A, PL5B, PL5C or PL3, PL3A, PL3B, respectively) formed thereon (see Figs. 3-5), and a plurality of second dielectric layers (LY6-LY16 or LY5, LY7) not including the plurality of first conductor layers formed thereon (see Figs. 3-5);
the plurality of through holes (VL6A, VL6B) include a plurality of first through holes formed in the plurality of first dielectric layers respectively (see Figs. 3-5, there are a portion of elements VL6A, VL6B formed in elements LY3-LY5 or LY2-LY4), and a plurality of second through holes formed in the plurality of second dielectric layers respectively (see Figs. 3-5, there are another portion of elements VL6A, VL6B and element VL6C formed in elements LY6-LY16 or LY5, LY7).
Regarding Claim 12, Tanaka shows the second inductor conductor (PL6A, PL6B, PL6C) includes a second conductor layer (conductor layer having element PL6B) and a plurality of inductor through holes (VL6A, VL6B, VL6); and
the stack further includes a connection conductor layer (PL5, PL6 combined) connected to at least one of the plurality of inductor through holes (VL6), and a connection through hole (VL5B) connecting the connection conductor layer (PL5, PL6 combined) and the plurality of first conductor layers (conductor layers having elements PL5A, PL5B, PL5C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Sakata [JP 2005-191256].
Regarding Claim 4, Tanaka shows the claimed invention as applied above.
In addition, Sakata shows (Fig. 4) the first inductor (2) and the second inductor (3) are provided in series (see Fig. 4, Paragraph [0050]) in a path connecting the first port (right end) and the second port (left end, see Fig. 4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the first inductor and the second inductor are provided in series in a path connecting the first port and the second port as taught by Sakata for the electronic component as disclosed by Tanaka to achieve desirable coupling, inductance, and impedance characteristics suitable for signal waveform shaping and signal noise removal and reduced stray capacitance (Paragraphs [0038]-[0039]).
Regarding Claim 12, Tanaka shows the claimed invention as applied above.
In addition, Sakata shows the second inductor conductor (12) includes a second conductor layer (conductor layer having element 12) and a plurality of inductor through holes (13); and the stack further includes a connection conductor layer (21) connected to at least one of the plurality of inductor through holes (13), and a connection through hole (top element 7) connecting the connection conductor layer (21) and the plurality of first conductor layers (6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the second inductor conductor includes a second conductor layer and a plurality of inductor through holes; and the stack further includes a connection conductor layer connected to at least one of the plurality of inductor through holes, and a connection through hole connecting the connection conductor layer and the plurality of first conductor layers as taught by Sakata for the electronic component as disclosed by Tanaka to achieve desirable coupling, inductance, and impedance characteristics suitable for signal waveform shaping and signal noise removal and reduced stray capacitance (Paragraphs [0038]-[0039]).
Claim(s) 4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Masuda et al. [U.S. Pub. No. 2016/0233845].
Regarding Claim 4, Tanaka shows the claimed invention as applied above.
In addition, Masuda et al. shows (Figs. 1A-2A) the first inductor (L1) and the second inductor (L2) are provided in series (see Figs. 1A-2A, Paragraphs [0020], [0060]) in a path connecting the first port (14a) and the second port (14b, see Figs. 1A-2A).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the first inductor and the second inductor are provided in series in a path connecting the first port and the second port as taught by Masuda et al. for the electronic component as disclosed by Tanaka to achieve desirable coupling and inductance where sufficient attenuation is obtained while insertion loss is reduced (Paragraph [0007]).
Regarding Claim 12, Tanaka shows the claimed invention as applied above.
In addition, Masuda et al. shows the second inductor conductor (22b, 22d) includes a second conductor layer (conductor layer having elements 22b, 22d) and a plurality of inductor through holes (v4, v5, v6, v7); and the stack further includes a connection conductor layer (22a) connected to at least one of the plurality of inductor through holes (v4), and a connection through hole (v3) connecting the connection conductor layer (22a) and the plurality of first conductor layers (18e, 18f, see Figs. 1A-2A).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the second inductor conductor includes a second conductor layer and a plurality of inductor through holes; and the stack further includes a connection conductor layer connected to at least one of the plurality of inductor through holes, and a connection through hole connecting the connection conductor layer and the plurality of first conductor layers as taught by Masuda et al. for the electronic component as disclosed by Tanaka to achieve desirable coupling and inductance where sufficient attenuation is obtained while insertion loss is reduced (Paragraph [0007]).
Claim(s) 5-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Kaminishi [U.S. Pub. No. 2018/0006625].
Regarding Claim 5, Tanaka shows the claimed invention as applied above.
In addition, Kaminishi shows a first resonator (HB) provided between the first port (14a) and the second port (14b) in the circuit configuration (see Fig. 1), wherein the first inductor (L2) and the second inductor (L1 or L5) are included in the first resonator (HB, see Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a first resonator provided between the first port and the second port in the circuit configuration, wherein the first inductor and the second inductor are included in the first resonator as taught by Kaminishi for the electronic component as disclosed by Tanaka to achieve desirable coupling, inductance, and impedance characteristics.
Regarding Claim 6, Kaminishi shows a third port (14c); and
a second resonator (LB) provided between the first port (14a) and the third port (14c) in the circuit configuration (see Fig. 1).
Regarding Claim 7, Kaminishi shows either one of the second (14b) and third ports is a first signal port that selectively passes a first signal of a frequency within a first passband (Paragraph [0033], 5 GHz); and the other of the second and third (14c) ports is a second signal port that selectively passes a second signal of a frequency within a second passband (Paragraph [0038], 2 GHz) lower than the first passband (Paragraphs [0033], [0038], [0040]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have either one of the second and third ports is a first signal port that selectively passes a first signal of a frequency within a first passband; and the other of the second and third ports is a second signal port that selectively passes a second signal of a frequency within a second passband lower than the first passband as taught by Kaminishi for the electronic component as disclosed by Tanaka to achieve desirable operating characteristics and excellent in being able to significantly reduce or prevent a situation in which the routing of conductors becomes complex (Paragraphs [0040], [0107]).
Regarding Claim 8, Kaminishi shows the second port (14b) is the first signal port (element 14b can be considered as the first signal port), and the third port (14c) is the second signal port (element 14c can be considered as the second signal port).
Regarding Claim 9, Tanaka shows the stack further includes a second resonator conductor (L12, C12 combined) constituting the second resonator (LB or FLT1),
the first inductor conductor (L23 or L21) is a horizontal inductor conductor (see Figs. 1-5) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-5, element L23 or L21 is a horizontal inductor conductor wound about an axis extending in a direction parallel to the stacking direction);
the second inductor conductor (L24) is a vertical inductor conductor (see Figs. 1-5) wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-5, element L24 is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction); and
the vertical inductor conductor (L24) is located farther from the second resonator conductor (LB or FLT1) than is the horizontal inductor conductor (L23 or L21, see Fig. 5, element L24 is located farther from element L12 than is element L23).
Regarding Claim 10, Tanaka shows the stack has a bottom surface (bottom surface, see Fig. 3) and a top surface (top surface, see Fig. 3) located at both ends of the plurality of dielectric layers in the stacking direction (see Fig. 3), and four side surfaces (see Fig. 3, left, right, front, and back surfaces) connecting the bottom surface and the top surface (see Fig. 3);
the bottom surface and the top surface each have a rectangular shape extending in one direction (see Fig. 3, bottom surface and top surface each have a rectangular shape extending in one direction, Paragraph [0040]);
the four side surfaces include a first side surface (right surface on the X-direction, see Figs. 3 and 5) and a second side surface (left surface on the X-direction, see Figs. 3 and 5) located at both longitudinal ends of the rectangular shape (see Figs. 3 and 5);
the first inductor conductor (L23 or L21) is a horizontal inductor conductor (see Figs. 1-5) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-5, element L23 or L21 is a horizontal inductor conductor wound about an axis extending in a direction parallel to a stacking direction);
the second inductor conductor (L24) is a vertical inductor conductor (see Figs. 1-5) wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-5, element L24 is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction);
the vertical inductor conductor (L24) is located closer to the first side surface than to the second side surface (see Figs. 3 and 5, element L24 is located closer to the right surface than the left); and
a distance from the vertical inductor conductor (L24) to the first side surface is smaller than a distance from the horizontal inductor conductor (L23 or L21) to the first side surface (see Figs. 3 and 5, a distance from element L24 to the right surface is smaller than a distance from element L23 or L21 to the right surface).
Kaminishi clearly shows the bottom surface and the top surface each have a rectangular shape extending in one direction (see Fig. 2A, bottom surface and top surface each have a rectangular shape extending in one direction, Paragraph [0043]); the four side surfaces include a first side surface (left or right surface, see Fig. 2A) and a second side surface (right or left surface, see Fig. 2A) located at both longitudinal ends of the rectangular shape (see Fig. 2A, Paragraph [0043]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Tanaka [U.S. Pub. No. 2021/0036676] (hereinafter as “Tanka ‘676”).
Regarding Claim 12, Tanaka shows the claimed invention as applied above.
In addition, Tanka ‘676 shows the second inductor conductor (L24) includes a second conductor layer (bottom conductor layer having element L24) and a plurality of inductor through holes (through holes of element L24); and the stack further includes a connection conductor layer (PB2) connected to at least one of the plurality of inductor through holes (one through hole of element L24), and a connection through hole (one through hole of element L23) connecting the connection conductor layer (PB2) and the plurality of first conductor layers (conductor layers having element L23, see Figs. 1-5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the second inductor conductor includes a second conductor layer and a plurality of inductor through holes; and the stack further includes a connection conductor layer connected to at least one of the plurality of inductor through holes, and a connection through hole connecting the connection conductor layer and the plurality of first conductor layers as taught by Tanka ‘676 for the electronic component as disclosed by Tanaka to significantly improve attenuation characteristics while significantly reducing or preventing an increase in loss of each filter (Paragraph [0007]).
Claim(s) 1-2, 4-6, and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe et al. [JP 2004-281847] in view of Tanaka [U.S. Pub. No. 2023/0238936].
Regarding Claim 1, Abe et al. shows a multilayer electronic component (Figs. 1-4) comprising:
a first port (upper center terminal connected to element L9a and element L8a in element 5h, see Fig. 4, see also Fig. 4, terminal between elements L8, L9);
a second port (GSM Rx, see Fig. 1) that passes a signal input to the first port (Paragraphs [0012]-[0019], see Fig. 1);
a first inductor (L8) and a second inductor (L3) that are provided between the first port and the second port in a circuit configuration (see Fig. 1); and
a stack that includes a plurality of dielectric layers (3a-3k) and a plurality of conductors (5a-5j) stacked together (see Figs. 1-4), the stack being intended to integrate the first port, the second port, the first inductor, and the second inductor (see Figs. 1-4), wherein:
the first inductor (L8) has a first end (first end of element L8a of Fig. 4 or right end of element L8 of Fig. 1) closest to the first port in the circuit configuration (see Figs. 1 and 4), and a second end (second end of element L8b of Fig. 4 or left end of element L8 of Fig. 1) opposite to the first end (see Figs. 1 and 4);
the second end (left end of element L8) of the first inductor (L8) is connected to one end (left end of element L3) of the second inductor (L3, see Fig. 1);
the stack includes a first inductor conductor (L8a, L8b) constituting the first inductor (L8, see Figs. 1-4), and a second inductor conductor (L3a, L3b) constituting the second inductor (L3, see Figs. 1-4);
the first inductor conductor (L8a, L8b) is wound about an axis extending in a first direction and the first direction is parallel to a stacking direction of the plurality of dielectric layers (see Figs. 1-4, elements L8a, L8b combined is wound about an axis extending in a first direction and the first direction is parallel to a stacking direction of elements 3a-3k); and
the second inductor conductor (L3a, L3b) is wound about an axis extending in a second direction intersecting the first direction and the stacking direction (see Figs. 1-4, elements L3a, L3b combined is wound about an axis extending in a second direction intersecting the first direction and the stacking direction).
Abe et al. does not explicitly show the first inductor conductor includes three or more conductor layers that are arranged at different positions with each other in the stacking direction.
Tanaka shows a device (Figs. 1-5) teaching and suggesting the first inductor conductor (PL5A, PL5B, PL5C or PL3, PL3A, PL3B) includes three or more conductor layers (conductor layers having elements PL5A, PL5B, PL5C or PL3, PL3A, PL3B) that are arranged at different positions with each other in the stacking direction (see Figs. 3-5, elements PL5A, PL5B, PL5C or PL3, PL3A, PL3B are arranged at different positions with each other in the stacking direction).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the first inductor conductor includes three or more conductor layers that are arranged at different positions with each other in the stacking direction as taught by Tanaka for the electronic component as disclosed by Abe et al. to achieve desirable coupling and inductance with improvement in Q factor and insertion loss (Paragraph [0074]).
Regarding Claim 2, Abe et al. shows the first direction and the second direction are orthogonal to each other (see Figs. 1-4, the first direction and the second direction are orthogonal to each other).
Regarding Claim 4, Abe et al. shows the first inductor (L8) and the second inductor (L3) are provided in series in a path connecting the first port and the second port (see Fig. 1, element L8 and element L3 are provided in series).
Regarding Claim 5, Abe et al. shows a first resonator (first resonator R1, see Drawing 1 below) provided between the first port and the second port in the circuit configuration (see Drawing 1 below), wherein the first inductor (L8) and the second inductor (L3) are included in the first resonator (first resonator R1, see Drawing 1 below).
Regarding Claim 6, Abe et al. shows a third port (GSM Tx, DCS Tx, or DCS Rx); and
a second resonator (F1, F2, or S2) provided between the first port and the third port in the circuit configuration (see Fig. 1).
Regarding Claim 9, Abe et al. shows the stack further includes a second resonator conductor (element L4 having elements L4a, L4b OR element L1 having elements L1a, L1b) constituting the second resonator (F2 OR F1);
the first inductor conductor (element L8 having elements L8a, L8b) is a horizontal inductor conductor (see Figs. 1-4) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-4, element L8 having elements L8a, L8b is a horizontal inductor conductor wound about an axis extending in a direction parallel to a stacking direction);
the second inductor conductor (element L3 having elements L3a, L3b) is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-4, element L3 having elements L3a, L3b is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction); and
the vertical inductor conductor (L3) is located farther from the second resonator conductor (L4 OR L1) than is the horizontal inductor conductor (L8, see Fig. 4, element L3a is located farther from element L4a than is element L8a OR element L3b is located farther from element L4b than is element L8b OR see Drawing 2 below, element L3a is located farther from element L1a than is element L8a OR element L3b is located farther from element L1b than is element L8b).
Regarding Claim 10, Abe et al. shows the stack has a bottom surface (bottom surface, see Fig. 2) and a top surface (top surface, see Fig. 2) located at both ends of the plurality of dielectric layers in a stacking direction (see Fig. 2), and four side surfaces (see Figs. 3-4, left, right, upper, and lower surfaces) connecting the bottom surface and the top surface (see Figs. 1-4);
the bottom surface and the top surface each have a rectangular shape extending in one direction (see Figs. 1-4, bottom surface and top surface each have a rectangular shape extending in one direction);
the four side surfaces include a first side surface (right surface, see Figs. 2 and 4) and a second side surface (left surface, see Figs. 2 and 4) located at both longitudinal ends of the rectangular shape (see Figs. 2 and 4);
the first inductor conductor (element L8 having elements L8a, L8b) is a horizontal inductor conductor (see Figs. 1-4) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-4, element L8 having elements L8a, L8b is a horizontal inductor conductor wound about an axis extending in a direction parallel to the stacking direction);
the second inductor conductor (element L3 having elements L3a, L3b) is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-4, element L3 having elements L3a, L3b is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction);
the vertical inductor conductor (L3) is located closer to the first side surface than to the second side surface (see Figs. 2 and 4, element L3a is located closer to the right surface than the left surface OR element L3b is located closer to the right surface than the left surface); and
a distance from the vertical inductor conductor (L3) to the first side surface is smaller than a distance from the horizontal inductor conductor (L8) to the first side surface (see Fig. 4, a distance from element L3a or L3b to the right surface is smaller than a distance from element L8a or L8b to the right surface).
Regarding Claim 11, Tanaka shows the second inductor conductor (PL6A, PL6B, PL6C) includes at least one second conductor layer (one conductor layer having elements PL6A, PL6C and another conductor layer having element PL6B) and a plurality of through holes (VL6A, VL6B, VL6C);
a number of the plurality of first conductor layers is equal to or more than a number of the at least one second conductor layer (a number of conductor layers having elements PL5A, PL5B, PL5C or PL3, PL3A, PL3B is equal to or more than a number of one conductor layer having elements PL6A, PL6C and another conductor layer having element PL6B);
the plurality of dielectric layers (LY1-LY17) include a plurality of first dielectric layers (LY3-LY5 or LY2-LY4) including the plurality of first conductor layers respectively (conductor layers having elements PL5A, PL5B, PL5C or PL3, PL3A, PL3B, respectively) formed thereon (see Figs. 3-5), and a plurality of second dielectric layers (LY6-LY16 or LY5, LY7) not including the plurality of first conductor layers formed thereon (see Figs. 3-5);
the plurality of through holes (VL6A, VL6B) include a plurality of first through holes formed in the plurality of first dielectric layers respectively (see Figs. 3-5, there are a portion of elements VL6A, VL6B formed in elements LY3-LY5 or LY2-LY4), and a plurality of second through holes formed in the plurality of second dielectric layers respectively (see Figs. 3-5, there are another portion of elements VL6A, VL6B and element VL6C formed in elements LY6-LY16 or LY5, LY7).
Regarding Claim 12, Tanaka shows the second inductor conductor (PL6A, PL6B, PL6C) includes a second conductor layer (conductor layer having element PL6B) and a plurality of inductor through holes (VL6A, VL6B, VL6); and
the stack further includes a connection conductor layer (PL5, PL6 combined) connected to at least one of the plurality of inductor through holes (VL6), and a connection through hole (VL5B) connecting the connection conductor layer (PL5, PL6 combined) and the plurality of first conductor layers (conductor layers having elements PL5A, PL5B, PL5C).
Claim(s) 4-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe et al. in view of Tanaka as applied to claim 1 above, and further in view of Kaminishi [U.S. Pub. No. 2018/0006625].
Regarding Claim 4, Abe et al. in view of Tanaka shows the claimed invention as applied above.
In addition, Kaminishi shows the first inductor (L3 or L2) and the second inductor (L4 or L5) are provided in series (see Fig. 1, Paragraph [0035]) in a path connecting the first port (14a) and the second port (14c or 14b, see Fig. 1, Paragraph [0035]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the first inductor and the second inductor are provided in series in a path connecting the first port and the second port as taught by Kaminishi for the electronic component as disclosed by Abe et al. in view of Tanaka to achieve desirable coupling, inductance, and impedance characteristics.
Regarding Claim 5, Abe et al. in view of Tanaka shows the claimed invention as applied above.
In addition, Kaminishi shows a first resonator (HB) provided between the first port (14a) and the second port (14b) in the circuit configuration (see Fig. 1), wherein the first inductor (L2) and the second inductor (L1 or L5) are included in the first resonator (HB, see Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a first resonator provided between the first port and the second port in the circuit configuration, wherein the first inductor and the second inductor are included in the first resonator as taught by Kaminishi for the electronic component as disclosed by Abe et al. in view of Tanaka to achieve desirable coupling, inductance, and impedance characteristics.
Regarding Claim 6, Kaminishi shows a third port (14c); and
a second resonator (LB) provided between the first port (14a) and the third port (14c) in the circuit configuration (see Fig. 1).
Regarding Claim 7, Kaminishi shows either one of the second (14b) and third ports is a first signal port that selectively passes a first signal of a frequency within a first passband (Paragraph [0033], 5 GHz); and the other of the second and third (14c) ports is a second signal port that selectively passes a second signal of a frequency within a second passband (Paragraph [0038], 2 GHz) lower than the first passband (Paragraphs [0033], [0038], [0040]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have either one of the second and third ports is a first signal port that selectively passes a first signal of a frequency within a first passband; and the other of the second and third ports is a second signal port that selectively passes a second signal of a frequency within a second passband lower than the first passband as taught by Kaminishi for the electronic component as disclosed by Abe et al. in view of Tanaka to achieve desirable operating characteristics and excellent in being able to significantly reduce or prevent a situation in which the routing of conductors becomes complex (Paragraphs [0040], [0107]).
Regarding Claim 8, Kaminishi shows the second port (14b) is the first signal port (element 14b can be considered as the first signal port), and the third port (14c) is the second signal port (element 14c can be considered as the second signal port).
Regarding Claim 9, Abe et al. shows the stack further includes a second resonator conductor (element L4 having elements L4a, L4b OR element L1 having elements L1a, L1b) constituting the second resonator (F2 OR F1);
the first inductor conductor (element L8 having elements L8a, L8b) is a horizontal inductor conductor (see Figs. 1-4) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-4, element L8 having elements L8a, L8b is a horizontal inductor conductor wound about an axis extending in a direction parallel to a stacking direction);
the second inductor conductor (element L3 having elements L3a, L3b) is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-4, element L3 having elements L3a, L3b is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction); and
the vertical inductor conductor (L3) is located farther from the second resonator conductor (L4 OR L1) than is the horizontal inductor conductor (L8, see Fig. 4, element L3a is located farther from element L4a than is element L8a OR element L3b is located farther from element L4b than is element L8b OR see Drawing 2 below, element L3a is located farther from element L1a than is element L8a OR element L3b is located farther from element L1b than is element L8b).
Regarding Claim 10, Abe et al. shows the stack has a bottom surface (bottom surface, see Fig. 2) and a top surface (top surface, see Fig. 2) located at both ends of the plurality of dielectric layers in a stacking direction (see Fig. 2), and four side surfaces (see Figs. 3-4, left, right, upper, and lower surfaces) connecting the bottom surface and the top surface (see Figs. 1-4);
the bottom surface and the top surface each have a rectangular shape extending in one direction (see Figs. 1-4, bottom surface and top surface each have a rectangular shape extending in one direction);
the four side surfaces include a first side surface (right surface, see Figs. 2 and 4) and a second side surface (left surface, see Figs. 2 and 4) located at both longitudinal ends of the rectangular shape (see Figs. 2 and 4);
the first inductor conductor (element L8 having elements L8a, L8b) is a horizontal inductor conductor (see Figs. 1-4) wound about an axis extending in a direction parallel to the stacking direction (see Figs. 1-4, element L8 having elements L8a, L8b is a horizontal inductor conductor wound about an axis extending in a direction parallel to the stacking direction);
the second inductor conductor (element L3 having elements L3a, L3b) is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction (see Figs. 1-4, element L3 having elements L3a, L3b is a vertical inductor conductor wound about an axis extending in a direction orthogonal to the stacking direction);
the vertical inductor conductor (L3) is located closer to the first side surface than to the second side surface (see Figs. 2 and 4, element L3a is located closer to the right surface than the left surface OR element L3b is located closer to the right surface than the left surface); and
a distance from the vertical inductor conductor (L3) to the first side surface is smaller than a distance from the horizontal inductor conductor (L8) to the first side surface (see Fig. 4, a distance from element L3a or L3b to the right surface is smaller than a distance from element L8a or L8b to the right surface).
Kaminishi clearly shows the bottom surface and the top surface each have a rectangular shape extending in one direction (see Fig. 2A, bottom surface and top surface each have a rectangular shape extending in one direction, Paragraph [0043]); the four side surfaces include a first side surface (left or right surface, see Fig. 2A) and a second side surface (right or left surface, see Fig. 2A) located at both longitudinal ends of the rectangular shape (see Fig. 2A, Paragraph [0043]).
Claim(s) 4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe et al. in view of Tanaka as applied to claim 1 above, and further in view of Sakata [JP 2005-191256].
Regarding Claim 4, Abe et al. in view of Tanaka shows the claimed invention as applied above.
In addition, Sakata shows (Fig. 4) the first inductor (2) and the second inductor (3) are provided in series (see Fig. 4, Paragraph [0050]) in a path connecting the first port (right end) and the second port (left end, see Fig. 4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the first inductor and the second inductor are provided in series in a path connecting the first port and the second port as taught by Sakata for the electronic component as disclosed by Abe et al. in view of Tanaka to achieve desirable coupling, inductance, and impedance characteristics suitable for signal waveform shaping and signal noise removal and reduced stray capacitance (Paragraphs [0038]-[0039]).
Regarding Claim 12, Abe et al. in view of Tanaka shows the claimed invention as applied above.
In addition, Sakata shows the second inductor conductor (12) includes a second conductor layer (conductor layer having element 12) and a plurality of inductor through holes (13); and the stack further includes a connection conductor layer (21) connected to at least one of the plurality of inductor through holes (13), and a connection through hole (top element 7) connecting the connection conductor layer (21) and the plurality of first conductor layers (6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the second inductor conductor includes a second conductor layer and a plurality of inductor through holes; and the stack further includes a connection conductor layer connected to at least one of the plurality of inductor through holes, and a connection through hole connecting the connection conductor layer and the plurality of first conductor layers as taught by Sakata for the electronic component as disclosed by Abe et al. in view of Tanaka to achieve desirable coupling, inductance, and impedance characteristics suitable for signal waveform shaping and signal noise removal and reduced stray capacitance (Paragraphs [0038]-[0039]).
Claim(s) 4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe et al. in view of Tanaka as applied to claim 1 above, and further in view of Masuda et al. [U.S. Pub. No. 2016/0233845].
Regarding Claim 4, Abe et al. in view of Tanaka shows the claimed invention as applied above.
In addition, Masuda et al. shows (Figs. 1A-2A) the first inductor (L1) and the second inductor (L2) are provided in series (see Figs. 1A-2A, Paragraphs [0020], [0060]) in a path connecting the first port (14a) and the second port (14b, see Figs. 1A-2A).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the first inductor and the second inductor are provided in series in a path connecting the first port and the second port as taught by Masuda et al. for the electronic component as disclosed by Abe et al. in view of Tanaka to achieve desirable coupling and inductance where sufficient attenuation is obtained while insertion loss is reduced (Paragraph [0007]).
Regarding Claim 12, Abe et al. in view of Tanaka shows the claimed invention as applied above.
In addition, Masuda et al. shows the second inductor conductor (22b, 22d) includes a second conductor layer (conductor layer having elements 22b, 22d) and a plurality of inductor through holes (v4, v5, v6, v7); and the stack further includes a connection conductor layer (22a) connected to at least one of the plurality of inductor through holes (v4), and a connection through hole (v3) connecting the connection conductor layer (22a) and the plurality of first conductor layers (18e, 18f, see Figs. 1A-2A).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the second inductor conductor includes a second conductor layer and a plurality of inductor through holes; and the stack further includes a connection conductor layer connected to at least one of the plurality of inductor through holes, and a connection through hole connecting the connection conductor layer and the plurality of first conductor layers as taught by Masuda et al. for the electronic component as disclosed by Abe et al. in view of Tanaka to achieve desirable coupling and inductance where sufficient attenuation is obtained while insertion loss is reduced (Paragraph [0007]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe et al. in view of Tanaka as applied to claim 1 above, and further in view of Tanaka [U.S. Pub. No. 2021/0036676] (hereinafter as “Tanka ‘676”).
Regarding Claim 12, Abe et al. in view of Tanaka shows the claimed invention as applied above.
In addition, Tanka ‘676 shows the second inductor conductor (L24) includes a second conductor layer (bottom conductor layer having element L24) and a plurality of inductor through holes (through holes of element L24); and the stack further includes a connection conductor layer (PB2) connected to at least one of the plurality of inductor through holes (one through hole of element L24), and a connection through hole (one through hole of element L23) connecting the connection conductor layer (PB2) and the plurality of first conductor layers (conductor layers having element L23, see Figs. 1-5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the second inductor conductor includes a second conductor layer and a plurality of inductor through holes; and the stack further includes a connection conductor layer connected to at least one of the plurality of inductor through holes, and a connection through hole connecting the connection conductor layer and the plurality of first conductor layers as taught by Tanka ‘676 for the electronic component as disclosed by Abe et al. in view of Tanaka to significantly improve attenuation characteristics while significantly reducing or preventing an increase in loss of each filter (Paragraph [0007]).
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Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2 and 4-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZFUNG J CHAN whose telephone number is (571)270-7981. The examiner can normally be reached M-TH 8:00AM-6:00PM.
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/TSZFUNG J CHAN/Primary Examiner, Art Unit 2837