Prosecution Insights
Last updated: April 19, 2026
Application No. 17/584,070

FLIP-CHIP ON LEADFRAME HAVING PARTIALLY ETCHED LANDING SITES

Final Rejection §103§112
Filed
Jan 25, 2022
Examiner
NGUYEN, DUY T V
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
6 (Final)
79%
Grant Probability
Favorable
7-8
OA Rounds
2y 10m
To Grant
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
828 granted / 1052 resolved
+10.7% vs TC avg
Strong +17% interview lift
Without
With
+17.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
57 currently pending
Career history
1109
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
51.5%
+11.5% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
14.2%
-25.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1052 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Application 1. Acknowledgement is made of the amendment received on 2/23/2026. Claims 1 & 3-13 are pending in this application. Claim 2 is canceled. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 2. Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In particular, claim 6 cites “the landing site includes a layer of metal alloy on copper” is not clear when reading into claims 1 & 5. Claim 1 require “the plurality of bumps including solder that physically contacts the side walls and the recess plane”, claim 6 requires a present of a layer of metal alloy on copper which separates the solder from being physically contacting the side walls and the recess plane. Difference shown in Figs. 2F & 3 of the application. Applicant is suggested to revise and clarify the claim(s) to avoid any further confusions. For best understanding and examination purpose, the claim(s) will be best considered based on drawings, disclosure, and/or any applicable prior arts. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 3. Claims 1, 3, 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2002/0074634) Re claims 1 & 3, Choi teaches, under BRI, Figs. 9A-C, [0055, 0075-0078], an integrated circuit (IC) package, comprising: -a semiconductor die (100); and -a leadframe (lead frame) including a plurality of leads (720), each of the plurality of leads (720) including a recessed portion (seating groove 721b), the recessed portion (721b) including a recess plane (bottom portion) and a sidewalls (of 721b) at an obtuse angle (more than 90o) with respect to the recess plane (bottom portion), each of the plurality of leads (720) electrically coupled to the semiconductor die (100) via a plurality of bumps (510, 750), the plurality of bumps (510, 750) including solder (of 510) that physically contacts the sidewalls and the recess plane (of 721b), wherein each of the plurality of bumps (510, 750) touches the recessed portion (of 721b). Note: 750 can be considered as part of recessed portion. PNG media_image1.png 325 674 media_image1.png Greyscale PNG media_image2.png 454 455 media_image2.png Greyscale Choi does not explicitly teach the recess plane parallel to a plane of the lead. Choi’s Fig. 8C teaches, [0068, 0071], a recess plane (of 621) parallel to a plane of the lead (620). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Choi’s Fig. 8C to obtain the recess plane parallel to a plane of the lead as claimed, because it aids in achieving desired shaped grooves within the leads. Further, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Re claim 5, Choi teaches, Figs. 9A-B, each of the plurality of leads (720) includes a landing site having the recessed portion (721). Re claim 7, Choi teaches, Fig. 9A, [0075] a mold material (105) covering portions of the semiconductor die (100) and at least a portion of the plurality of leads (720). 4. Claims 1, 3-5, 7-10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2002/0074634) in view of Park et al. (US 2006/0049517). Re claims 1 & 3, Choi teaches, under BRI, Figs. 9A-C, [0055, 0075-0078], an integrated circuit (IC) package, comprising: -a semiconductor die (100); and -a leadframe (lead frame) including a plurality of leads (720), each of the plurality of leads (720) including a recessed portion (groove 721), the recessed portion (721) including a recess plane (flat portion) parallel to a plane of the lead (720) and a sidewalls (of 721) at an obtuse angle (more than 90o) with respect to the recess plane (flat portion), each of the plurality of leads (720) electrically coupled to the semiconductor die (100) via a plurality of bumps (510, 750), the plurality of bumps (510, 750) including solder (of 510) that contacts the sidewalls and the recess plane. wherein each of the plurality of bumps (510, 750) touches the recessed portion (721). PNG media_image1.png 325 674 media_image1.png Greyscale PNG media_image3.png 479 441 media_image3.png Greyscale Choi does not explicitly teach the plurality of bumps including solder that physically contacts the sidewalls and the recess plane. Park teaches, Figs. 5 & 8-9, [0037-0039], the plurality of bumps including solder (113) that physically contacts the sidewalls and the recess plane (of groove 112). As taught by Park, one of ordinary skill in the art would utilize & modify the above teaching to obtain the plurality of bumps including solder that physically contacts the sidewalls and the recess plane as claimed, because it aids in improving electrical contact/connection between a chip and leads. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Park in combination with Choi due to above reason. Re claim 4, in combination cited above, Park teaches, Fig. 8, the solder (113) contacts an entirety of the recessed portion (112) including a portion along the recess plane (of 112). Re claim 5, Choi teaches, Figs. 9A-B, each of the plurality of leads (720) includes a landing site having the recessed portion (721). Re claim 7, Choi teaches, Fig. 9A, [0075], a mold material (105) covering portions of the semiconductor die (100) and at least a portion of the plurality of leads (720). Re claim 8, Choi teaches, under BRI, Figs. 9A-B, claim 19, [0055, 0075-0078], an integrated circuit (IC) package, comprising: -a semiconductor die (100); and -a lead frame (lead frame) including a plurality of leads (720), each of the plurality of leads (720) including a concave portion (groove 721) with a semi-circular cross-sectional shape (721b); -a metal alloy (metal layer 750, e.g., an alloy of Ni and Sn, claim 19) on the concave portion (721b); -a solder (510) in the concave portion and contacting the metal alloy (750); -mold material (105) covering portions of the semiconductor die (100) and the plurality of leads (720); wherein each of the plurality of leads (720) include a first portion with a first thickness (indicated) and a second portion with a second thickness (indicated), a surface of the second portion (bottommost surface) coplanar with a surface of the mold compound (105), the first thickness being (indicated) lesser than the second thickness (indicated). PNG media_image4.png 623 604 media_image4.png Greyscale Choi does not teach a solder cap in the concave portion, a metal pillar on the solder cap and electrically connected to the semiconductor die. Park teaches, Fig. 8, [0034-0036], a solder cap (113) in the concave portion (112), a metal pillar (a post formed of 124, 125) on the solder cap (113) and electrically connected to the semiconductor die (121). PNG media_image5.png 393 425 media_image5.png Greyscale As taught by Park, one of ordinary skill in the art would utilize & modify the above teaching into Cho to obtain a solder cap in the concave portion, a metal pillar on the solder cap and electrically connected to the semiconductor die as claimed, because it aids in achieving a flip chip semiconductor device having an improved structure, which allows the semiconductor chip to be securely coupled to the lead frame while preventing defective contacts between them. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Park in combination with Choi due to above reason. Re claim 9, Choi teaches, Fig. 9B, the concave portion (721b) is in the first portion. Re claim 10, Choi teaches, Fig. 9A, each of the plurality of leads (720) include a landing site having the concave portion (721). Re claim 13, Choi teaches, Figs. 9A-B, the semiconductor die (100) include an active surface (bottom of 100) with functional circuit including bond pads (101) thereon, and wherein the active surface faces the concave portion (721). 5. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Do as modified Choi as modified by Park as applied to claims 1 & 5 above, and further in view of Miyazaki (US 2002/0195720). The teachings of Choi/Park have been discussed above. Re claim 6, Choi teaches, Figs. 9A-B, claim 19, [0078], the landing site include a layer of metal alloy (750). Choi/Park does not explicitly teach a layer of metal alloy on copper. Miyazaki teaches, Figs. 5E-G, claim 9, [0051], a metal alloy (6) on copper (7). As taught by Miyazaki, one of ordinary skill in the art would utilize & modify the above teaching to obtain a layer of metal alloy on copper as claimed, because it aids in securing and improving stability/mounting reliability of the package. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Miyazaki in combination with Choi/Park due to above reason. 6. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Choi as modified by Park as applied to claim 8 above, and further in view of Do et al. (2012/0126429. The teachings of Chen/Park have been discussed above. Re claim 12, Choi/Park does not explicitly teach the lead frame is of a copper or a copper alloy. Do teaches the lead frame is of a copper or a copper alloy [0042]. As taught by Do, one of ordinary skill in the art would utilize & modify the above teaching to obtain the lead frame is of a copper or a copper alloy as claimed, because copper is known material & widely used in the art as material of a lead frame. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Do in combination with Choi/Park due to above reason. 7. Claims 8, 10 and 11 are, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2002/0074634) in view of Park et al. (US 2006/0049517) and Miyazaki (US 2002/0195720). Re claim 8, Choi teaches, under BRI, Figs. 9A-B, claim 19, [0055, 0075-0078], an integrated circuit (IC) package, comprising: -a semiconductor die (100); and -a lead frame (lead frame) including a plurality of leads (720), each of the plurality of leads (720) including a concave portion (groove 721) with a semi-circular cross-sectional shape (721b); -a metal alloy (metal layer 750, e.g., an alloy of Ni and Sn, claim 19) on the concave portion (721b); -a solder (510) in the concave portion (721) and contacting the metal alloy (750); -mold material (105) covering portions of the semiconductor die (100) and the plurality of leads (720); wherein each of the plurality of leads (720) include a first portion with a first thickness (indicated) and a second portion with a second thickness (indicated), a surface of the second portion (bottommost surface) coplanar with a surface of the mold compound (105), the first thickness being (indicated) lesser than the second thickness (indicated). PNG media_image4.png 623 604 media_image4.png Greyscale Choi does not teach a solder cap in the concave portion, a metal pillar on the solder cap and electrically connected to the semiconductor die. Park teaches, Fig. 8, [0034-0036], a solder cap (113) in the concave portion (112), a metal bump (formed of 124, 125) on the solder cap (113) and electrically connected to the semiconductor die (121). As taught by Park, one of ordinary skill in the art would utilize & modify the above teaching into Cho to obtain a solder cap in the concave portion, a metal bump on the solder cap and electrically connected to the semiconductor die as claimed, because it aids in achieving a flip chip semiconductor device having an improved structure, which allows the semiconductor chip to be securely coupled to the lead frame while preventing defective contacts between them. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Park in combination with Choi due to above reason. Choi/Park does not explicitly teach a metal pillar. Miyazaki teaches a metal pillar (metallic post 8) (Fig. 5G, [0047]). As taught by Miyazaki, one of ordinary skill in the art would utilize & modify the above teaching into Choi/Park to obtain a metal pillar as claimed, because it aids in improving stability/mounting reliability of the package. Further, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Miyazaki in combination with Choi/Park due to above reason. Re claim 10, Choi teaches, Fig. 9A, each of the plurality of leads (720) include a landing site having the concave portion (721). Re claim 11, in combination cited above, Miyazaki teaches, Figs. 5F-H, the metal pillar (8) is aligned with the landing site (with films 6, 7). Response to Arguments 8. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection. The claims amended with newly added features, rejection & interpretation under the cited priors (e.g., Choi & Miyazaki) are also changed to meet the claims. Details included in the above rejection. The rejection of claims under Do et al. & Hasebe et al. is withdrawn due to claim amendment. Conclusion 9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/9/26
Read full office action

Prosecution Timeline

Jan 25, 2022
Application Filed
Dec 31, 2022
Non-Final Rejection — §103, §112
Apr 10, 2023
Response Filed
Jul 15, 2023
Final Rejection — §103, §112
Nov 21, 2023
Response after Non-Final Action
Nov 21, 2023
Notice of Allowance
Mar 21, 2024
Response after Non-Final Action
Apr 03, 2024
Response after Non-Final Action
Aug 07, 2024
Non-Final Rejection — §103, §112
Dec 01, 2024
Response Filed
Apr 02, 2025
Final Rejection — §103, §112
Jun 09, 2025
Response after Non-Final Action
Jul 07, 2025
Notice of Allowance
Sep 08, 2025
Response after Non-Final Action
Sep 17, 2025
Response after Non-Final Action
Sep 23, 2025
Non-Final Rejection — §103, §112
Feb 23, 2026
Response Filed
Mar 24, 2026
Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+17.1%)
2y 10m
Median Time to Grant
High
PTA Risk
Based on 1052 resolved cases by this examiner. Grant probability derived from career allow rate.

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