DETAILED ACTION
This is the Office action based on the 17586437 application filed January 27, 2022, and in response to applicant’s argument/remark filed on September 15, 2025. Claims 1 and 3-9 are currently pending and have been considered below. Applicant’s cancelation of claims 2 and 10-15 acknowledged.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 1 recites “surface roughness after ion implantation slicing”, but no ion implantation slicing is recited previously. One of skill in the art would not be clear when to perform a ion implantation slicing or when to measure the surface roughness. For the purpose of examining it will be assumed that there is an ion implantation slicing step performed prior to the claimed method of final processing
Claims 3-9 rejected under 35 U.S.C. 112(b) because they are directly or indirectly dependent on claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 3-9 rejected under U.S.C. 103 as being unpatentable over Maleville et al. (U.S. PGPub. No. 20060223283), hereinafter “Maleville”, in view of Frontheiser et al. (U.S. PGPub. No. 20140273423), hereinafter “Frontheiser”, and Akiyama et al. (U.S. PGPub. No. 20110003460), hereinafter “Akiyama”.--Claims 1, 6, 7, 8, 9: Maleville teaches a method for processing an SOI substrate ([0024]), comprisingimplanting species into a donor substrate to define a useful layer, bonding a support substrate to the donor substrate, then detaching the support substrate and the useful layer to form an SOI substrate ([0005, 0014, 0024]);thermally annealing the SOI substrate to reduce surface roughness ([0014]), wherein the thermal anneal comprising a) a rapid thermal annealing (RTA) at 800-1400°C in an atmosphere including argon, or argon and hydrogen for 1-60 seconds ([0016, 0029]); b) a StabOx process comprising successive operations of oxidation and annealing, wherein the annealing comprises heating the substrate at 1100°C for about 2 hours then removing the oxide grown during the oxidation, i.e. deoxidation) ([0017, 0031-0033]). Maleville further teaches that step (a) and (b) may be reversed and/or repeated ([0039]) and that the thickness consumed by the StabOx is controlled to eliminate surface defects and smoothening the surface to improve uniformity ([0034-0037]). Maleville is silent about a temperature ramping rate in the RTA process. Frontheiser, also directed to a method of annealing an substrate having SOI structure ([0024]) by using RTA, teaches that the RTA comprises placing the substrate in a RTA tool, ramping the temperature at a rate 1-100°C/sec, and anneal the substrate at 1050°C for a few to 300 seconds in an atmosphere comprising argon or hydrogen ([0030]). Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to ramp up the temperature at a rate of 1-100°C/sec for the RTA in invention of Maleville because Maleville teaches that the RTA is performed at 800-1400°C in an atmosphere including pure argon, or argon and hydrogen, but is silent about a temperature ramping rate, and Frontheiser teaches that such ramping rate would be effective for such RTA. It is noted that this overlaps on the claimed heating speed of 30-100°C/s and annealing temperature 1100-1300°C recited in claim 1. Maleville further teaches that the annealing in step b) use an argon atmosphere ([0032]). Maleville is silent about the gas composition of the atmosphere comprising H2 and Ar in step a) and the argon atmosphere in step b). Akiyama, also directed to thermal annealing a SOI substrate in the presence of a gas mixture comprising argon and hydrogen at 1250°C, teaches that the hydrogen gas may be present at 4 vol% or less ([0042-0050]). Akiyama further teaches that annealing in such gas mixture would advantageously smooth out the surface while drastically reducing the surface etching. Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to use a gas mixture comprising argon and less than 4 vol% of hydrogen as the annealing atmosphere containing H2 and Ar in the invention of Maleville because Maleville teaches to perform the RTA anneal in an atmosphere including H2 and Ar but is silent about the concentration, and Akiyama teaches that a gas mixture having such concentrations of H2 and Ar would advantageously smooth out the surface while drastically reducing the surface etching. It would also have been obvious to one of ordinary skill in the art at the effective filing date of the invention, in routine experimentations, to use a gas mixture comprising argon and less than 4 vol% of hydrogen as the anneal atmosphere in step b) in the invention of Maleville because Maleville teaches to perform the anneal in an argon atmosphere but is silent about the concentration, and Akiyama teaches that a gas mixture having such gas mixture would smooth out the surface while drastically reducing the surface etching. Using the same gas mixture in both step a) and b) would simplify manufacturing and reduce cost. Maleville further teaches that the method produces a less rough surface and a more uniform surface of the thin layer for the SOI substrate ([0037, 0047-0048]), and that a surface roughness of about 3 Å may be produced (Fig. 2, [0052]). Akiyama teaches that for an SOI substrate an in-plane film thickness profile of the silicon layer is an extremely important factor, and the in-plane uniformity in nanometer-scale is required ([0002]), wherein the silicon surface is required to have a surface roughness of about 3 Å ([0005, 0018]), and highly uniform thickness ([0029, 0035, 0043, 0049]), and teaches that the annealing would improve the film uniformity ([0023, 0043, 0045-0051]). Although Maleville and Akiyama are silent about a numerical value for the film uniformity, it would have been obvious to one of ordinary skill in the art at the time the invention was made to achieve the optimal film uniformity, such as ± 1%, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It is noted that the process taught by Maleville modified by Frontheiser and Akiyama is the same as recited in claim 1; therefore, it would produce the same surface roughness and thickness uniformity as Applicant’s. Maleville further teaches that “The RTA annealing stage in particular reduces the surface roughness of the thin layer, essentially by surface reconstruction and smoothing. And, as mentioned earlier, RTA annealing especially benefits reduction of the roughness at high frequencies. In addition, any crystalline defects present in the thin layer, and generated in particular during implantation and detachment, are at least in part cured by this RTA annealing” ([0029]). Therefore, although Maleville is silent about the RTA anneal removes at least one pit formed on a surface of the SOI wafer, it would have been obvious to one of ordinary skill in the art at the time the invention was made to perform the RTA annealing so that at least one pit formed on a surface of the SOI wafer is removed since it’s established that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A). Akiyama further teaches that a surface roughness of a substrate may be 31 Å ([0061], Fig. 3).--Claim 3: Although Maleville is silent about a number of particles on the amorphous silicon layer, since it is well known in the art that avoiding particles in a semiconductor device is critical to preventing yield loss, it would have been obvious to one of ordinary skill in the art at the time the invention was made to deposit the amorphous silicon layer such that the number of particles is less than 100 at 37 nm detection threshold.--Claim 4: Maleville does not teach the method including any CMP process.--Claim 5: It is noted that pre-processing steps, i.e. implanting species into a donor substrate to define a useful layer, bonding a support substrate to the donor substrate, then detaching the support substrate and the useful layer, are performed to obtain the SOI wafer.
Response to Arguments
Applicant's arguments filed September 15, 2025 have been fully considered as follows:--Regarding Applicant’s argument that the amendment has overcome all rejections under 35 U.S.C. 112(b), this argument is not persuasive. As noted in the previous Office action, Claim 1 recites “surface roughness after ion implantation slicing”, but no ion implantation slicing is recited previously. One of skill in the art would not be clear when to perform a ion implantation slicing or when to measure the surface roughness.--Regarding Applicant’s argument that the “the structure to be annealed with an annealing performed in an argon atmosphere disclosed by Maleville is the SiO2/Si interface, which is formed after a process called StableOX, not a top silicon layer”, this argument is not persuasive. Maleville clearly discloses that “(p)resented is a method for producing a high quality useful layer of semiconductor material on a substrate. The method includes implanting at least two different atomic species into a face of a donor substrate to a controlled mean implantation depth to form a weakened zone therein and to define a useful layer. The implanting step is conducted to minimize low-frequency roughness at the weakened zone. Next, a support substrate is bonded to the face of the donor substrate, and the useful layer is detached from the donor substrate along the weakened zone. A structure is thus formed that includes the useful layer on the support substrate with the useful layer presenting a surface for further processing. The structure is then thermally treated to minimize high-frequency roughness of the surface of the useful layer, to result is a surface having sufficient smoothness so that chemical mechanical polishing of the useful layer surface is not required. “ ([0014], all emphases added) and
“(t)he present process relates to the production of structures that include a thin layer of semiconductor material on a support substrate, wherein the thin layer is by detachment at the level of a donor substrate that has a weakened zone created by implantation of species. The structure can be, in general, any type of structure that includes a thin layer of a semiconductor material on a surface exposed to the external environment (a free surface). Such a thin layer of semiconductor material can be, for example, silicon Si, silicon carbide SiC, germanium Ge, silicon-germanium SiGe, gallium arsenic AsGa, etc. Further, a support substrate can be made of silicon Si, quartz, and the like. A layer of oxide can also be inserted between the support substrate and the thin layer, such that the structure that is formed is a semiconductor-on-insulator structure (such as a SeOI structure), and in particular a silicon-on-insulator (SOI) structure, for example)” ([0024], all emphases added). Thus, the SOI, i.e. silicon-on-insulator, structure that is thermally treated in the invention of Maleville comprises, from top down, a thin layer of semiconductor material, such as silicon, then an oxide layer, then a support substrate; wherein the thermal treatment smoothens the top silicon surface so that a chemical mechanical polishing is not required. Therefore, Applicant’s arguments regarding the annealing performed on an SiO2/Si interface are not applicable. It is noted that Maleville teaches that “The RTA annealing stage in particular reduces the surface roughness of the thin layer, essentially by surface reconstruction and smoothing. And, as mentioned earlier, RTA annealing especially benefits reduction of the roughness at high frequencies. In addition, any crystalline defects present in the thin layer, and generated in particular during implantation and detachment, are at least in part cured by this RTA annealing” ([0029]). Therefore, although Maleville is silent about the RTA anneal removes at least one pit formed on a surface of the SOI wafer, it would have been obvious to one of ordinary skill in the art at the time the invention was made to perform the RTA annealing so that at least one pit formed on a surface of the SOI wafer is removed since it’s established that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”. MPEP 2144.05(II)(A). Since Applicant fails to define the term “pit”; therefore, for a purpose of examining the term “pit” is interpreted as any recess on a surface.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP §706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS PHAM whose telephone number is (571) 270-7670 and fax number is (571) 270-8670. The examiner can normally be reached on MTWThF9to6 PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached on (571) 270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS T PHAM/Primary Examiner, Art Unit 1713