Prosecution Insights
Last updated: July 17, 2026
Application No. 17/587,749

INLINE CONTACTLESS METROLOGY CHAMBER AND ASSOCIATED METHOD

Non-Final OA §103§112
Filed
Jan 28, 2022
Priority
Oct 12, 2021 — provisional 63/254,599
Examiner
CULBERT, CHRISTOPHER A
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
42%
Grant Probability
Moderate
1-2
OA Rounds
0m
Est. Remaining
49%
With Interview

Examiner Intelligence

Grants 42% of resolved cases
42%
Career Allowance Rate
144 granted / 341 resolved
-25.8% vs TC avg
Moderate +7% lift
Without
With
+6.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
43 currently pending
Career history
416
Total Applications
across all art units

Statute-Specific Performance

§103
82.1%
+42.1% vs TC avg
§102
11.3%
-28.7% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 341 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group II and Species, corresponding to claims 14-16, 18, and 19, is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 19 states that the second line scan is performed “after the semiconductor wafer is transferred to a hub” (i.e., when the wafer is no longer in the sensor chamber”) while also requiring the second line scan to commence “as the semiconductor wafer is retracted from the sensor chamber” (i.e., while the wafer is still in the sensor chamber). This limitations conflict with each other and one having ordinary skill in the art would not readily understand how to resolve this conflict. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2016/0035631 A1) in view of Klein (“Non-Contact Metal Layer Thickness and Sheet Resistance Measurement on Process Wafers; SURAGUS GmbH; www.suragus.com; Sept. 24, 2019; reference already of record). Regarding claim 14; Lee discloses a method of fabricating an integrated circuit (IC), the method comprising: processing a semiconductor wafer in a fabrication flow having a sequence of process stages for creating at least one semiconductor die containing the IC (sequence of process stages performed in the various chambers shown in Fig. 3), the semiconductor wafer forming a substrate for the IC, the sequence of process stages including at least one operation performed in a processing chamber of a fabrication tool with respect to a process layer of the semiconductor wafer (“ALD”, ¶ 0086); and performing a sheet resistance measurement of the process layer (¶ 0089). Lee does not disclose using a contactless sensor. Klein, in the same field of endeavor, discloses using a contactless sensor assembly disposed in a sensor chamber integrated into the fabrication tool, the contactless sensor assembly comprising an eddy current sensor assembly including at least one sensor probe operative for sensing sheet resistance of the process layer (Page 13 of Klein). There was a benefit to using such a sensor in that it does not damage the films (Page 13 of Klein). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to use the contactless sensor taught by Klein to perform the sheet resistance measurement of Lee for this benefit. Regarding claim 15, Lee in view of Klein discloses the method as recited in claim 14, as discussed above. Lee further discloses wherein the operation comprises an atomic layer deposition process for forming the process layer (¶ 0086). Regarding claim 16, Lee in view of Klein discloses the method as recited in claim 15, as discussed above. Klein further discloses determining an overall resistance by sequentially measuring the individual resistances of individual layers (Page 23). Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Klein as applied to claim 14, above, and further in view of You et al. (US 2006/0084188 A1) and Moradian et al. (US 2020/0024726 A1). Regarding claim 18, Lee in view of Klein discloses the method as recited in claim 14, as discussed above. Klein does not disclose that performing the sheet resistance comprises performing a first line scan. You, in the same field of endeavor, discloses performing resistance measurements using a line scan (¶ 0027) which terminates at an interior position of the substate (¶ 0027). There was a benefit to using line scans in that it provides a multitude of measurement points along the surface which minimizes the effects local deviations would have on the overall measurement. It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to perform the resistance measurement using a line scan for this benefit. Klein does not disclose that the substrate is moved by means of a blade coupled to a robotic arm. Moradian, in the same field of endeavor, discloses using blade coupled to robotic arms to move substrate (¶ 0045). There was a benefit to using blade coupled to a robotic arm in that it allows for a high degree of control of the positioning of the substrate (¶ 0045). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to use a blade coupled to a robotic arm for this benefit. Further, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to begin the first line scan as the substrate is being introduced into the sensor chamber for the benefit of minimizing the time it takes to perform the scan and to terminate the first line scan after the semiconductor wafer is brought to a halt at a predetermined location (e.g., the last point of measurement) to minimize excessive movement of the substate. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A CULBERT/Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Jan 28, 2022
Application Filed
Mar 05, 2025
Response Filed
Aug 19, 2025
Non-Final Rejection mailed — §103, §112
Feb 19, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
42%
Grant Probability
49%
With Interview (+6.8%)
3y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 341 resolved cases by this examiner. Grant probability derived from career allowance rate.

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