DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 11/26/25.
Applicant’s amendment to claims 1 and 16 is acknowledged.
Claims 3, 11-15 and 18 are canceled.
Claims 1, 2, 4-10, 16, 17, and 19-23 are pending and claims 2, 4-8, 10, 17, 19 and 20 are withdrawn.
Claims 1, 9, 16, and 21-23 are subject to examination at this time.
Response to Arguments
Applicant's arguments filed 11/26/25 have been fully considered but they are not persuasive.
Regarding the reference JP 5185062 B2:
The reference JP 5185062 B2 discloses element (3) is a “wiring board”.
Applicant’s citation to patent family member Osumi, US 20110115081 A1, discloses element (3) is an “interconnect substrate”.
A circuit board is not only comprised of the board material, but also the circuit layers therein. Such circuit layers include metallization layers like “wiring” or “interconnect” layers (4). Because a circuit board can comprise a plurality of layers/elements, the “wiring” or “interconnect” layers (4) are a part of the circuit board. Referring to JP 5185062 fig. 4, the pin (5) is disposed directly on the circuit board (3) that comprises the “wiring” or “interconnect” layers (4).
Regarding the Kim reference:
The combination of Kim and Chen is not impermissible hindsight because Chen provides motivation to one of ordinary skill in the art to modify Kim to expose a side surface of the first pin such that the first pin is electrically connectable to an external device by a part of a side surface.
Specifically, the 35 USC 103 rejection cites to Chen’s disclosure of the advantages at para. [0082]:
“Due to the recessing of molding material 120 and the exposure of the sidewalls of through-vias 122, solder regions 206 are also in contact with the sidewalls of through-vias 122, resulting in the increase in the contact area between through-vias 122 and solder regions 206. Accordingly, the contact resistance is reduced. Furthermore, the bonding strength is improved.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9, 16, 22 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Japanese publication No. JP 5185062 B2 (of record, see attached English machine translation) in view of Wolter et al., US Publication No. 2016/0240492 A1 (of record).
The reference JP 5185062 B2 teaches:
A packaging device, comprising (see fig. 4):
PNG
media_image1.png
538
936
media_image1.png
Greyscale
a circuit board (3, “wiring board”) having a first surface (e.g. top surface);
a first packaging layer (11) covering the first surface, wherein the first plastic packaging layer comprises a first channel (e.g. opening in 11 due to displacement by 5), the first channel penetrates the first plastic packaging layer in a first direction (e.g. vertical direction), and the first direction is a direction perpendicular to the first surface; and
a first pin (5), wherein the first pin is disposed directly on the circuit board (3) and electrically connected to the circuit board (3), the first pin (5) is located in the first channel (e.g. opening in 11 due to displacement by 5), at least a part of the first pin (5) is connected to an inner wall of the first channel, a first conductive surface (e.g. top surface) of the first pin that is away from the circuit board (3) is exposed from the first channel and the first pin (5) extends out of the first channel in the first direction to form an exposed portion of the first pin, and the first pin (5) is electrically connectable to an external device (8) by the first conductive surface and a part of a side surface of the exposed portion of the first pin (e.g. In fig. 4, the top, first conductive surface and side surface of pin 5 is exposed.),
wherein the first channel e.g. opening in 11 due to displacement by 5) is a through hole, the first channel is located in an area enclosed by side surfaces of the first packaging layer (11), and the side surfaces of the first packaging layer (11) intersect the first surface (e.g. top surface of 3). See attached English machine translation pages 1-12, figs. 1-6.
Regarding claim 1:
JP 5185062 B2 teaches the first packaging layer is a mold resin, but does not expressly teach the material is plastic, -i.e. a plastic packaging layer.
In an analogous art, Wolter teaches (see figs. 1 and 5-8) a suitable material for a packaging layer (118, 518, 618, 718) may comprise plastic, polymer or epoxy. See Wolter at para. [0029].
Furthermore, it would have been obvious to one having ordinary skill in the art to form the packing layer from plastic, since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
The reference JP 5185062 B2 further teaches:
9. The packaging device according to claim 1, wherein the packaging device further comprises a first electronic component (1);
the first electronic component (1) is disposed on the first surface (e.g. top surface), and is electrically connected to the circuit board (3); and an upper surface of the first electronic component that is away from the circuit board is flush with the upper surface of the first plastic packaging layer that is away from the circuit board, or
an upper surface of the first electronic component (3) that is away from the circuit board (3) is covered by the first plastic packaging layer (11), fig. 4.
Regarding claim 16:
The reference JP 5185062 B2 teaches the limitations as applied to claim 1 above.
The reference JP 5185062 B2 further teaches the added limitation:
16. An electronic device, comprising:
an external device (8);
…the first pin (5) is electrically connected to the external device (8) by a solder connection (10) that contacts the first conductive surface (e.g. top surface) and a part of a side surface of the exposed portion of the first pin (5), fig. 4.
Regarding claims 22 and 23:
The reference JP 5185062 B2 teaches the limitations as applied to claim 9 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed inventio to modify the teachings of JP 5185062 B2 with the teachings of Wolter because “The mold or molding compound may be formed of any of a variety of different materials, depending on the nature of the package and its intended use. Suitable mold compounds may include…a plastic material… Alternatively, …other material may be used to protect the die.” See Wolter at para. [0029].
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Japanese publication No. JP 5185062 B2 in view of Wolter, as applied to claim 16 above, in further view of Myung et al., US Publication No. 2013/0200531 A1.
Regarding claim 21:
The reference JP 5185062 B2 and Wolter teach all the limitations of claim 16 above, and JP 5185062 B2 further teaches:
21. The electronic device according to claim 16, further comprising a first electronic component (1) disposed on the first surface (e.g. top surface), and electrically connected to the circuit board (3), fig. 4.
The reference JP 5185062 B2 does not expressly teach:
an upper surface of the first electronic component that is away from the circuit board is flush with the upper surface of the first plastic packaging layer that is away from the circuit board.
In an analogous art, Myung teaches:
(see figs. 3 and 5) an upper surface of the first electronic component (200) that is away from the circuit board (100) is flush with the upper surface of the first packaging layer (300) that is away from the circuit board. See Myung at para. [0053].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed inventio to modify the teachings of JP 5185062 B2 with the teachings of Myung to reduce the size of the semiconductor package. See Myung ‘s disclosure of “As the thickness of an electronic device using the semiconductor package is gradually decreasing, the thickness of the semiconductor package is generally also reduced.” at para. [0053].
Claim(s) 1, 9, 16 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, US Publication No. 2012/0139090 A1 in view of Wolter et al., US Publication No. 2016/0240492 A1 (of record) and Chen et al., US Publication No. 2019/0259720 A1 (of record).
Kim teaches:
1. A packaging device, comprising (see fig. 5):
a circuit board (110L) having a first surface (e.g. top surface);
a first packaging layer (130L) covering the first surface, wherein the first plastic packaging layer comprises a first channel (e.g. opening in 130L due to displacement by 151a), the first channel penetrates the first packaging layer (130L) in a first direction (e.g. vertical direction), and the first direction is a direction perpendicular to the first surface (e.g. top surface); and
a first pin (151a), wherein the first pin is disposed directly on the circuit board (110L) and electrically connected to the circuit board (110L), the first pin (151a) is located in the first channel (e.g. opening in 130L due to displacement by 151a), at least a part of the first pin (151a) is connected to an inner wall of the first channel, a first conductive surface (e.g. top surface) of the first pin (151a) that is away from the circuit board (110L) is exposed from the first channel…and the first pin is electrically connectable to an external device (115U) by the first conductive surface (e.g. top surface)…,
wherein the first channel (e.g. opening in 130L due to displacement by 151a) is a through hole, the first channel is located in an area enclosed by side surfaces of the first packaging layer (130L), and the side surfaces of the first packaging layer (130L) intersect the first surface (e.g. top surface). See Kim at para. [0001] – [0126], figs. 1-8.
Regarding claim 1:
Kim teaches the first packaging layer is an epoxy or polyimide, but does not expressly teach the material is plastic, -i.e. a plastic packaging layer.
In an analogous art, Wolter teaches (see figs. 1 and 5-8) a suitable material for a packaging layer (118, 518, 618, 718) may comprise plastic, polymer or epoxy. See Wolter at para. [0029].
Furthermore, it would have been obvious to one having ordinary skill in the art to form the packing layer from plastic, since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Wolter shows that plastic, polymer or epoxy are considered equivalent materials known in the art for a packaging layer. Therefore, because these materials were art-recognized equivalents, one of ordinary skill in the art would have found it obvious to substitute Kim’s epoxy or polyimide material for plastic. Also see MPEP § 2144.06, Art Recognized Equivalence for the Same Purpose.
Kim does not expressly teach:
the first pin extends out of the first channel in the first direction to form an exposed portion of the first pin, and the first pin is electrically connectable to an external device by…a part of a side surface of the exposed portion of the first pin,
In an analogous art, Chen teaches:
(see figs. 23-25) the first pin (122) extends out of the first channel (e.g. opening in 120 due to displacement by 122) in the first direction (e.g. vertical direction) to form an exposed portion of the first pin, and the first pin (122) is electrically connectable to an external device (200) by the first conductive surface (e.g. top surface) and a part of a side surface of the exposed portion of the first pin (122). See Chen at para. [0078] – [0083]
It would have been obvious to one of ordinary skill in the art to modify Kim with Chen to expose a side surface of the first pin such that the first pin is electrically connectable to an external device by a part of a side surface because Chen teaches the following advantage at para. [0082]:
“Due to the recessing of molding material 120 and the exposure of the sidewalls of through-vias 122, solder regions 206 are also in contact with the sidewalls of through-vias 122, resulting in the increase in the contact area between through-vias 122 and solder regions 206. Accordingly, the contact resistance is reduced. Furthermore, the bonding strength is improved.”
Kim further teaches:
9. The packaging device according to claim 1, wherein the packaging device further comprises a first electronic component (115L);
(see fig. 5) the first electronic component (115L) is disposed on the first surface (e.g. top surface), and is electrically connected to the circuit board (110L); and an upper surface of the first electronic component (115L) that is away from the circuit board is flush with the upper surface of the first plastic packaging layer (130L) that is away from the circuit board (110L), or
an upper surface of the first electronic component that is away from the circuit board is covered by the first plastic packaging layer.
Regarding claim 16:
Kim, Wolter and Chen teach the limitations as applied to claim 1 above.
Kim further teaches the added limitation:
an external device (105U);
…the first pin (151a) is electrically connected to the external device (150U) by a solder connection (152a).., fig. 5.
Chen also teaches:
an external device (200);
…the first pin (122) is electrically connected to the external device (200) by a solder connection (206)… fig. 24.
Regarding claim 21:
Kim, Wolter and Chen teach the limitations as applied to claim 9 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed inventio to modify the teachings of Kim with the teachings of Wolter because “The mold or molding compound may be formed of any of a variety of different materials, depending on the nature of the package and its intended use. Suitable mold compounds may include…a plastic material… Alternatively, …other material may be used to protect the die.” See Wolter at para. [0029]. Furthermore, providing more than one material selection for the packaging layer enables greater flexibility in semiconductor manufacturing.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed inventio to modify the teachings of Kim with the teachings of Chen because “Due to the recessing of molding material 120 and the exposure of the sidewalls of through-vias 122, solder regions 206 are also in contact with the sidewalls of through-vias 122, resulting in the increase in the contact area between through-vias 122 and solder regions 206. Accordingly, the contact resistance is reduced. Furthermore, the bonding strength is improved.” See Chen at para. [0082].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michele Fan/
Primary Examiner, Art Unit 2818
29 January 2026