DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/2/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (PG Pub. No. US 2015/0279431 A1) in view of Chen et al. (PG Pub. No. US 2015/0155221 A1) and Hong et al. (PG Pub. No. US 2015/0130078 A1).
Regarding claim 1, Li teaches a semiconductor die assembly (fig. 1: 100), comprising:
a package support substrate (¶ 0015: 120);
a first semiconductor die (¶ 0015: 102a) carried by an upper surface of the package support substrate and having a central region and a lateral region (fig. 1: 102 carried by upper surface of 120 and a includes unlabeled central region and peripheral portion 107);
a die stack (¶ 0015: 105) having one or more second semiconductor dies (¶ 0015: 103) carried by the central region of the first semiconductor die (fig. 1: 105 carried by central portion of 102a);
an adhesive (¶ 0017: 114a and/or 114b) over at least a portion of the lateral region of the first semiconductor die (fig. 1: at least portion 114b over 107) extending continuously from an internal surface facing the die stack to an external surface opposite the internal surface (fig. 1: 114b continuously extends between internal and external surfaces), wherein the adhesive includes a first portion over the lateral region of the first semiconductor die and having a first thickness (fig. 1: 114b includes a portion over lateral region of 102a with a first thickness);
a heat transfer structure (¶ 0030: 113) at least partially carried by the lateral region of the first semiconductor die (fig. 1: 113 carried by 107), wherein an inner-most surface of the heat transfer structure is vertically aligned with the internal surface of the adhesive, and wherein a peripheral-most surface of the heat transfer structure is vertically aligned with the external surface of the adhesive (fig. 1: inner-most surface of 113 vertically aligned with inner surface of 114b, peripheral-most surface of 113 is vertically aligned with external surface of 114b); and
an underfill material (¶ 0019: 116) between the heat transfer structure and one or more outermost surfaces of the die stack (fig. 1: 116 between 113 and outermost surface of 105).
Li does not teach wherein the adhesive includes a vent channel extending from the internal surface to the external surface, or the adhesive comprises a second portion over the upper surface of the package support substrate and having a second thickness greater than the first thickness.
Chen teaches a semiconductor die assembly (¶ 0028: 300) comprising an adhesive (¶ 0028: 302/304), the adhesive including a vent channel (¶ 0028: space 306) extending from an internal surface to an external surface (fig. 3: 306 extends from internal surface of 302/304 to an external surface of 302/304).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the adhesive of Li with vent channels, as a means to vent outgas from an adhesive material (Chen, ¶ 0030).
Li in view of Chen does not teach the adhesive comprises a second portion over the upper surface of the package support substrate and having a second thickness greater than the first thickness.
Hong teaches a semiconductor die assembly (¶ 0043 & fig. 1: 1000) including a dies stack (200) on a semiconductor die (¶ 0043 & fig. 1: 200 disposed on semiconductor chip 110) and carried by a package support substrate (¶ 0044: 10), an adhesive (¶ 0070: 170 and 320) comprising a first portion over a lateral region of the semiconductor die and having a first thickness, and a second portion over the upper surface of the package support substrate and having a second thickness greater than the first thickness (fig. 1: 170/320 includes a first portion over lateral region of 110, and a second portion over an upper surface of 12, the second portion thicker than the first portion).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor die assembly of Li in view of Chen with the adhesive thickness of Hong, as a means to seal the side surfaces of the first semiconductor chip and a portion of the upper surface of the package support substrate (Hong, ¶ 0052), minimizing exposure the environmental effects and improving reliability of the package.
Regarding claim 2, Li in view of Chen and Hong teaches the semiconductor die assembly of claim 1 wherein the heat transfer structure includes a planar lower surface attached to the adhesive (Li, fig. 1: 113 comprises planar lower surface attached to 114b), and wherein the planar lower surface extends from the peripheral-most surface and the inner-most surface (Li, fig. 1: planar lower surface of 113 extends from external surface of 114b to inner-most surface of 114b).
Regarding claim 3, Li in view of Chen and Hong teaches the semiconductor die assembly of claim 1 wherein the die stack has a first longitudinal side and a second longitudinal side (Li, figs. 1, 4: 105 includes at least two longitudinal sides), and wherein the vent channel extends from the external surface of the adhesive to the internal surface adjacent the first longitudinal side (Chen, fig. 3: space 306 extends from external surface of 302/304 to internal surface of 302/304 adjacent side of 102, similar to 105 of Li).
Regarding claim 4, Li in view of Chen and Hong teaches the semiconductor die assembly of claim 3 wherein the inner-most surface of the heat transfer structure has a sidewall is spaced apart from the first longitudinal side and the second longitudinal side of the die stack by a gap (Li, fig. 1: inner-most surface of 113 has sidewall spaced apart from 1st and 2nd longitudinal sides of 105 by a gap).
Regarding claim 5, Li in view of Chen and Hong teaches the semiconductor die assembly of claim 1 further comprising a lid (Li, ¶ 0017: 112) carried by the heat transfer structure above the die stack (Li, fig. 1: 112 carried by 113 above 105).
Regarding claim 6, Li in view of Chen and Hong teaches the semiconductor die assembly of claim 1, wherein:
the heat transfer structure is at least partially carried by the package support substrate (Li, fig. 1: 113 at last indirectly carried by 120).
Regarding claim 7, Li in view of Chen and Hong teaches the semiconductor die assembly of claim 6 wherein the package support substrate includes a lower surface having a plurality of electrical connectors (Li, ¶ 0015: bottom surface of 120/122 includes connectors 125), wherein the first semiconductor die is electrically coupled to the plurality of electrical connectors (Li, ¶ 0015: 102a electrically coupled to 120/122, including 124/125).
Regarding claim 8, Li in view of Chen and Hong teaches the semiconductor die assembly of claim 1 wherein an upper die of the die stack has a top surface area (Li, fig. 1: upper 103 of stack 105 has top surface), and wherein the heat transfer structure has an opening larger than the top surface area of the upper die (Li, fig. 1: 113 has larger opening than surface area of top 103).
Regarding claim 22, Li in view of Chen and Hong teaches the semiconductor die assembly of claim 1, wherein first semiconductor die has a sidewall, and wherein the external surface of the adhesive is spaced laterally apart from the sidewall peripheral to the first semiconductor die (Hong, fig. 1: external surface of 170/320 spaced laterally apart from the sidewall peripheral to 110).
Regarding claim 23, Li in view of Chen and Hong teaches the semiconductor die assembly of claim 1, wherein the second portion of the adhesive is in contact with at least a portion of a sidewall of the first semiconductor die (Hong, fig. 1: second portion of 170/320 in contact with sidewall of 110).
Response to Arguments
Applicant’s arguments, see page 7, section A, filed 6/2/2026, with respect to the formal objection to claim 21 have been fully considered and are persuasive. Accordingly, the formal objection to claim 21 has been withdrawn.
Applicant’s arguments with respect to claims 1-8 and 22-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Vadhavkar et al. (PG Pub. No. US 20160013115 A1) teaches a die stack (122) arranged on a semiconductor die (110), and an adhesive (133/148) including portions over a lateral region of the semiconductor die and an upper surface of a package substrate (102), the first and second portions having different thicknesses (fig. 2C).
Chandolu (PG Pub. No. US 2016/0268235 A1) teaches a die stack (102a) arranged on a semiconductor die (102b), and an adhesive (114b) over a lateral region of the semiconductor die (fig. 1).
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/BRIAN TURNER/Examiner, Art Unit 2818
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