DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 21 is objected to because of the following informalities:
The Examiner suggests the following amendment to correct an apparent typographic error:
“…the first semiconductor die is carried by an upper surface of the package support substrate…”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (PG Pub. No. US 2015/0279431 A1) in view of Chen et al. (PG Pub. No. US 2015/0155221 A1).
Regarding claim 1, Li teaches a semiconductor die assembly (fig. 1: 100), comprising:
a first semiconductor die (¶ 0015: 102a) having a central region and a lateral region (102 a includes unlabeled central region and peripheral portion 107);
a die stack (¶ 0015: 105) having one or more second semiconductor dies (¶ 0015: 103) carried by the central region of the first semiconductor die (fig. 1: 105 carried by central portion of 102a);
an adhesive (¶ 0017: 114a and/or 114b) over at least a portion of the lateral region of the first semiconductor die (fig. 1: at least portion 114b over 107) extending continuously from an internal surface facing the die stack to an external surface opposite the internal surface (fig. 1: 114b continuously extends between internal and external surfaces);
a heat transfer structure (¶ 0030: 113) at least partially carried by the lateral region of the first semiconductor die (fig. 1: 113 carried by 107), wherein an inner-most surface of the heat transfer structure is vertically aligned with the internal surface of the adhesive, and wherein a peripheral-most surface of the heat transfer structure is vertically aligned with the external surface of the adhesive (fig. 1: inner-most surface of 113 vertically aligned with inner surface of 114b, peripheral-most surface of 113 is vertically aligned with external surface of 114b); and
an underfill material (¶ 0019: 116) between the heat transfer structure and one or more outermost surfaces of the die stack (fig. 1: 116 between 113 and outermost surface of 105).
Li does not teach wherein the adhesive includes a vent channel extending from the internal surface to the external surface.
Chen teaches a semiconductor die assembly (¶ 0028: 300) comprising an adhesive (¶ 0028: 302/304), the adhesive including a vent channel (¶ 0028: space 306) extending from an internal surface to an external surface (fig. 3: 306 extends from internal surface of 302/304 to an external surface of 302/304).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the adhesive of Li with vent channels, as a means to vent outgas from an adhesive material (Chen, ¶ 0030).
Regarding claim 2, Li in view of Chen teaches the semiconductor die assembly of claim 1 wherein the heat transfer structure includes a planar lower surface attached to the adhesive (Li, fig. 1: 113 comprises planar lower surface attached to 114b), and wherein the planar lower surface extends from the peripheral-most surface and the inner-most surface (Li, fig. 1: planar lower surface of 113 extends from external surface of 114b to inner-most surface of 114b).
Regarding claim 3, Li in view of Chen teaches the semiconductor die assembly of claim 1 wherein the die stack has a first longitudinal side and a second longitudinal side (Li, figs. 1, 4: 105 includes at least two longitudinal sides), and wherein the vent channel extends from the external surface of the adhesive to the internal surface adjacent the first longitudinal side (Chen, fig. 3: space 306 extends from external surface of 302/304 to internal surface of 302/304 adjacent side of 102, similar to 105 of Li).
Regarding claim 4, Li in view of Chen teaches the semiconductor die assembly of claim 3 wherein the inner-most surface of the heat transfer structure has a sidewall is spaced apart from the first longitudinal side and the second longitudinal side of the die stack by a gap (Li, fig. 1: inner-most surface of 113 has sidewall spaced apart from 1st and 2nd longitudinal sides of 105 by a gap).
Regarding claim 5, Li in view of Chen teaches the semiconductor die assembly of claim 1 further comprising a lid (Li, ¶ 0017: 112) carried by the heat transfer structure above the die stack (Li, fig. 1: 112 carried by 113 above 105).
Regarding claim 6, Li in view of Chen teaches the semiconductor die assembly of claim 1, further comprising a package support substrate (Li, ¶ 0015: 120/122), wherein:
the first semiconductor die is mounted to an upper surface the package support substrate (Li, fig. 1: 102 mounted on upper surface of 120/122);
the adhesive includes a first portion (Li, 114b) over the lateral region of the first semiconductor die (Li, fig. 1: portion 114b disposed over region 107) and a second portion (Li, 114a) over the package support substrate (Li, fig. 1: portion 114a indirectly disposed over 120/122); and
the heat transfer structure is at least partially carried by the package support substrate (Li, fig. 1).
Regarding claim 7, Li in view of Chen teaches the semiconductor die assembly of claim 6 wherein the package support substrate includes a lower surface having a plurality of electrical connectors (Li, ¶ 0015: bottom surface of 120/122 includes connectors 125), wherein the first semiconductor die is electrically coupled to the plurality of electrical connectors (Li, ¶ 0015: 102a electrically coupled to 120/122, including 124/125).
Regarding claim 8, Li in view of Chen teaches the semiconductor die assembly of claim 1 wherein an upper die of the die stack has a top surface area (Li, fig. 1: upper 103 of stack 105 has top surface), and wherein the heat transfer structure has an opening larger than the top surface area of the upper die (Li, fig. 1: 113 has larger opening than surface area of top 103).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Chen as applied to claim 1 above, and further in view of Groothuis et al. (PG Pub. No. US 2013/0119528 A1).
Regarding claim 21, Li in view of Chen teaches the semiconductor die assembly of claim 1 further comprising a package support substrate (Li, ¶ 0015: 120/122), wherein:
the first semiconductor die is carried by an upper surface the package support substrate (Li, fig. 1: 102a carrier by upper surface of 120/122); and
the adhesive includes
a first portion (Li, 114b) over the lateral region of the first semiconductor die and having a first thickness (Li, fig. 1: 114b disposed over region 107 and has a 1st thickness), and
a second portion (Li, 114a) over the upper surface of the package support substrate and having a second thickness (Li, fig. 1: 114a disposed at least indirectly over upper surface of 120/122).
Li in view of Chen does not teach the second thickness greater than the first thickness.
Groothuis teaches a semiconductor die assembly (fig. 4: 400) including a first portion (¶ 0037: 410a) over the lateral region of a first semiconductor die (fig. 4: 410a disposed over lateral region 408 of semiconductor die 406) and a second portion (410b) over an upper surface of a package support substrate (fig. 4: 410b indirectly disposed over upper surface of package substrate 430), wherein the second portion has a different thickness than the first portion (¶ 0037: in at least one embodiment, 410b and 410a have different thicknesses).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the adhesive portions of Li in view of Chen with different thickness, as a means to optimize thermal energy transfer and adhesion of the semiconductor die stack (Groothius, ¶ 0037).
Furthermore, it has been held that “[w]hen there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 550 U.S. at 421, 82 USPQ2d at 1397. In the instant case, providing the different adhesive thicknesses of Groothius has a finite number of identified, predictable solutions (the second thickness greater than the first thickness, the first thickness greater than the second thickness), and a person of ordinary skill has good reason to pursue the known options (optimize thermal energy transfer and adhesion).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Fujishima et al. (PG Pub. No. US 2012/0146242 A1) teaches a semiconductor die package (fig. 1A) including a die stack (3), a package substrate (2) and external connectors (6).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRIAN TURNER/ Examiner, Art Unit 2818