Prosecution Insights
Last updated: October 02, 2026
Application No. 17/588,930

ISOLATION OF SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Jan 31, 2022
Examiner
RAMOS-DIAZ, FERNANDO JOSE
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
3 (Non-Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
14 granted / 17 resolved
+14.4% vs TC avg
Minimal +2% lift
Without
With
+1.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
23 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§103
44.5%
+4.5% vs TC avg
§102
37.9%
-2.1% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 17 resolved cases

Office Action

§102 §103
DETAILED ACTION/EXAMINER’S COMMENT This Office action responds to the amendments filed on 10/23/2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Amendment Status Applicant’s Appeal Brief filed on 5/5/2026 in reply to the final rejection mailed on 12/05/2025, has been entered. The final rejection mailed on 12/05/2025 has been withdrawn, the new grounds of rejection are presented in this Office action after the appeal brief filed on 05/05/2026. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claim(s) 1-21. Claims 7, 13-16, & 18 are canceled. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 21 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu (US 20160163583). Regarding Claim 21, Liu (see, e.g., fig. fig. 1a, fig. 1c) shows a semiconductor device comprising: a drift well 112 disposed in a semiconductor substrate 102, 104 & 106 (see, e.g., para.0012, para.0014) having a top surface, the drift well being doped with a first dopant conductivity type p-type (“The drift well includes the same polarity type dopants as the type of the transistor,” and the device can be an LDPMOS transistor and is elected to be such, see, e.g., para.0015, para.0023); a drain region 134 disposed in the semiconductor substrate, the drain region being disposed within the drift well (see, e.g., fig. 1a), the drain region being doped with the first dopant conductivity type p-type (LDPMOS transistor embodiment and thus the drain region is p-type, see, e.g., para.0018); a first dopant isolation region 108 (formed as a region of epitaxial layer 106, see, e.g., para.0014, para.0035) disposed in the semiconductor substrate and circumscribing the drain region, the first dopant isolation region being an electrically floating node (see, e.g., para.0035) and doped with a second conductivity type n-type (108 is formed of 106 which can be either n-type or p-type “the epitaxial layer [106] is a n-type epitaxial layer grown on the n-type buried layer” see, e.g., para.0014) opposite from the first dopant conductivity type (p-type) including a first well (the current claim language is broad enough such that Examiner can indicate a portion of 108 to be the first well, hereinafter referred to as “108a”) implanted with a first depth below the top surface and second well (the current claim language is broad enough such that Examiner can indicate a portion of 104 to be the second well, hereinafter referred to as “104b”) implanted with a deeper second depth below the top surface (see, e.g., para.0014, annotated figure 1a); and a second dopant isolation region 154 (conducting material including “highly p-type doped polysilicon,” see, e.g., para.0032) disposed in the semiconductor substrate and circumscribing the first dopant isolation region, the second dopant isolation region being doped with the first dopant conductivity type (p-type). PNG media_image1.png 624 1199 media_image1.png Greyscale Allowable Subject Matter Claims 1-6, 8-12, 17, 19, & 20 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding the amended limitation of claim 1, wherein the first dopant isolation region comprises: a first well doped with the second dopant conductivity type: and a second well disposed in the first well, the second well being doped with the second dopant conductivity type, a concentration of a dopant of the second dopant conductivity type in the second well being greater than a concentration of a dopant of the second dopant conductivity type in the first well: and wherein the second dopant isolation region comprises: a third well doped with the first dopant conductivity type; and an isolation surface region disposed in the third well, the isolation surface region being doped with the first dopant conductivity type, a concentration of a dopant of the first dopant conductivity type in the isolation surface region being greater than a concentration of a dopant of the first dopant conductivity type in the third well The subject matter of Claim 7, which was previously indicated as allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, is included in Claim 1. The prior art of record (Liu, Chuang, Kao, & Tanaka) neither anticipates nor renders obvious the claimed limitation and overcomes the rejection. Regarding the amended limitation of claim 17, wherein: the p-doped well region comprises: a first p-doped well disposed in the semiconductor substrate; and a second p-doped well disposed in the semiconductor substrate, the second p- doped well being disposed in the first p-doped well, a concentration of a p-type dopant in the second p-doped well being greater than a concentration of a p-type dopant in the first p-doped well; and the n-doped isolation region comprises: an n-doped well disposed in the semiconductor substrate; and an n-doped isolation surface region disposed in the semiconductor substrate, the n-doped isolation surface region being disposed in the n-doped well, a concentration of an n-type dopant in the n-doped isolation surface region being greater than a concentration of an n-type dopant in the n-doped well The subject matter of Claim 18, which was previously indicated as allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, is included in Claim 17. The prior art of record (Liu, Chuang, Kao, & Tanaka) neither anticipates nor renders obvious the claimed limitation and overcomes the rejection. Response to Arguments Applicant’s arguments, see pages 8-10, filed October 23, 2025, with respect to the prior art rejections under 35 U.S.C. 102(a)(2) and under 35 U.S.C. 103 have been fully considered and are persuasive. the prior art rejections under 35 U.S.C. 102(a)(2) and under 35 U.S.C. 103 have been withdrawn. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818 /STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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Prosecution Timeline

Jan 31, 2022
Application Filed
Jul 23, 2025
Non-Final Rejection mailed — §102, §103
Oct 23, 2025
Response Filed
Dec 05, 2025
Final Rejection mailed — §102, §103
Mar 05, 2026
Notice of Allowance
May 05, 2026
Response after Non-Final Action
May 22, 2026
Response after Non-Final Action
Sep 09, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
84%
With Interview (+1.5%)
3y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 17 resolved cases by this examiner. Grant probability derived from career allowance rate.

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