DETAILED ACTION
Claims 34-57 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
In the IDS submitted on August 6, 2025:
NPL references 2, 12, 13, 18, 19, and 21 have not been considered because they are not in English nor is there an explanation of relevance. See 37 CFR 1.98(b)(3).
NPL references 22-23 have not been considered because the cited titles do not match the titles on the submitted copies.
In the IDS submitted on August 7, 2025:
NPL references 1, 2, and 5 have not been considered because the cited titles do not match the titles on the submitted copies.
Specification
The replacement abstract submitted on August 6, 2025 is objected to because of the following minor informalities:
In the 3rd to last line, “a third source registers” is grammatically incorrect. It appears applicant meant “register”.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections/Recommendations
In claim 34, the examiner recommends rewording line 4 to --…operation, source registers, and a destination register;-- and rewording the last line to --…of the destination register--.
In claim 42, the examiner recommends rewording line 6 to --…operation, source registers, and a destination register;-- and rewording the last line to --…of the destination register--.
In claim 50, the examiner recommends rewording line 4 to --…operation, source registers, and a destination register;-- and rewording the last line to --…of the destination register--.
Claim 50 is objected to because of the following informalities:
The 2nd-3rd to last lines are grammatically incorrect. It appears applicant meant
--store the first, second, third, and fourth final results in specified data element positions in the destination register-- (assuming the recommendation above is accepted).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 42-57 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 42, line 8, “the execution”, since there is execution in line 2 and more execution in line 7.
In claim 50, the last line, “the destination register” as there are at least three potentially different destination registers previously recited. If applicant accepts the examiners proposed amendments above, this issue would be resolved.
Claims 43-49 and 51-57 are rejected for being dependent on an indefinite claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 34-57 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more.
Regarding step 1 of the subject matter eligibility test (see flowchart in MPEP 2106(III)), all claims are directed to a statutory category of invention.
Regarding claim 34 and step 2A (prong 1) of the test (see flowchart in MPEP 2106.04(II)(A), the claim recites executing a Fast Fourier Transform (FFT) butterfly operation, the execution comprising:
multiplying real N-bit data elements with imaginary M-bit data elements and multiplying imaginary N-bit data elements with real M-bit data elements to generate at least four imaginary products;
adding a first selected imaginary product and a second selected imaginary product to generate a first temporary result and adding a third selected imaginary product and a fourth selected imaginary product to generate a second temporary result;
adding the first temporary result to a first N-bit data element to generate a first pre-scaled result, subtracting the first temporary result from the first N-bit data element to generate a second pre-scaled result, adding the second temporary result to a second N-bit data element from the third source register to generate a third pre-scaled result, and subtracting the second temporary result from the second N-bit data element to generate a fourth pre-scaled result;
scaling the first, second, third and fourth pre-scaled results to a specified bit width to generate first, second, third, and fourth final results;
These steps correspond to the abstract idea grouping of mathematical calculations (see
MPEP 2106.04(a)(2)). Of note, the scaling step, per paragraph [00154], is a right shift of binary data by 1 or 2 bits (which carries out a division of that binary data by 2 and 4, respectively). As such, the scaling corresponds to division.
Regarding claim 34 and step 2A (prong 2) of the test, the claim recites additional elements of:
decoding, by a decoder of a processor, a first instruction to generate a decoded instruction, the first instruction having a plurality of fields to indicate the FFT operation and source and destination registers;
executing, by an execution unit of the processor, the decoded instruction to perform the FFT butterfly operation, the execution comprising:
storing a first plurality of packed N-bit real and imaginary data elements in a first source register;
storing a second plurality of packed M-bit real and imaginary data elements in a second source register;
storing a third plurality of packed N-bit real and imaginary data elements in a third source register; and
storing the first, second, third, and fourth final results in specified data element positions of a destination register.
the multiplied data elements are packed elements in a source register; and
the temporary results are added/subtracted to/from packed data elements;
The decoding and executing steps amount to merely including an instruction to
implement the abstract idea using generic computer components (decoder and execution unit of a processor). For instance, the claims are directed to math performed in response to executing a VPCR2BFRSDIMM instruction (paragraphs [00164]+). Any given instruction must be decoded in a processor so as to determine the operations to perform and on which data, and then executed to actually carry out the operations. Thus, the decoding and executing is part of using an instruction to implement the abstract idea. Use such an instruction and generic computer has been determined by the courts to not integrate the abstract idea into a practical application (see MPEP 2106.04(d)(I), 6th bullet).
The steps of storing of the source data and the results is deemed insignificant extra-solution activity that is incidental to the math itself and is merely a nominal or tangential addition to the claim. The courts have similarly determined such activity to not integrate the abstract idea into a practical application (see MPEP 2106.04(d)(I), 7th bullet).
Finally, packed (source and destination) registers to each store multiple data elements (as shown in FIGs.14 and 16), in this day and age, are generic computer components that allow a generic computer to be used as a tool to perform the abstract idea. Using a generic computer as a tool has been determined by the courts to not integrate the abstract idea into a practical application (see MPEP 2106.04(d)(I), 6th bullet).
Thus, the additional elements, alone or in combination, do not integrate the claimed math into a practical application.
Regarding claim 34 and step 2B of the test:
As stated above, the decoding and execution of an instruction using a generic computer and the presence of packed registers with packed data elements used in the math calculations correspond to a mere instruction to implement the math and using a generic computer as a tool to perform the math. The courts have determined that such does not amount to significantly more (see MPEP 2106.05(I)(A), second item (i)).
Additionally, the storing steps are all highly generic and, thus, per the courts, are well-understood, routine, and conventional functions that do not amount to significantly more (see MPEP 2106.05(d)(I) and (II), first items (i) and (iv)).
Thus, the additional elements, alone or in combination do not amount to significantly
more, and claim 34 is patent-ineligible under 35 U.S.C. 101.
Claim 35 essentially recites the additional element of bit values in an immediate of the instruction to control the scaling. This amounts to merely using an instruction to implement the math, which, alone or in combination with the other additional elements, does not integrate the math into a practical application, nor does it amount to significantly more. Thus, claim 35 is patent-ineligible under 35 U.S.C. 101.
Claim 36 essentially recites no division (no shifting) of the pre-scaled results, division by 2 of the pre-scaled results (1-bit shift), and division by 4 of the pre-scaled results (2-bit shift). These are parts of the mathematical calculations. The additional recited element of the bit values indication which of these calculations is to be performed amounts to merely using an instruction to implement the math amounts to a mere instruction to implement the math, which, alone or in combination with the other additional elements, does not integrate the math into a practical application, nor does it amount to significantly more. Thus, claim 36 is patent-ineligible under 35 U.S.C. 101.
Claim 37 recites that the sizes of the binary values to be multiplied. This is part of the math calculations, where a human, can perform binary multiplication of a 16-bit binary number and a 32-bit binary number (with the aid of pen and paper). The additional element of the register size (128 bits), a very well-known register size, still falls into the category of generic computer to be used as a tool to perform the math. Thus this element, alone or in combination with the other additional elements, does not integrate the math into a practical application, nor does it amount to significantly more. Claim 36 is therefore patent-ineligible under 35 U.S.C. 101.
Claim 38 essentially recites that the data elements corresponds to input functions and twiddle factor for a Fast Fourier Transform. This element is therefore part of the mathematical calculations. Claim sets forth no further additional element. Thus, claim 36 is patent-ineligible under 35 U.S.C. 101.
Claims 39-40 set forth sign-extending, which falls into the abstract idea grouping of mental processes (see MPEP 2106.04(a)(2)(III)). Sign-extending binary data to a particular width involves an observation. That is, a human may look at the sign bit of the data (e.g., the leftmost bit) and add additional bits next to the sign bit with the same value as the sign bit. As a simple example, if a human sees a 6-bit value 100110 and wants to sign-extend the value to 8 bits, the human evaluates the leftmost bit to be a ‘1’, and, thus, adds two more ‘1’ bits to the left of the sign bit to realize 11100110. These claims recite no further additional element and therefore they are not patent-ineligible under 35 U.S.C. 101.
Claim 41 recites rounding and/or saturation of the pre-scaled results and/or the final results. Rounding is a known mathematical calculation and/or mental process. Saturation is the same as it involves generating the maximum value for a given bit size if a value is larger than the maximum supported value (e.g. see paragraph [00144]). For instance, from paragraph [00138], if a result is 50 bits, but only 32-bits are to be in the final result, then if the 50-bit value is larger than the maximum 32-bit value, the result will simply be calculated as the maximum 32-bit value. The claim recites no further additional element and therefore it is not patent-ineligible under 35 U.S.C. 101.
Claims 42-57 are similarly not patentable for reasoning that claims 34-41 and 34-41 are not patentable, respectively.
Terminal Disclaimer
The terminal disclaimer filed on August 6, 2025, disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No. 11,243,765 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Allowable Subject Matter
Claims 34-57 are allowed over the prior art.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The reasons for the indication of allowable subject matter from the Office Action mailed on May 6, 2025, are still applicable and not repeated here for brevity.
Response to Arguments
On page 15 of applicant’s response, applicant argues that the claims are not directed to a mathematical calculation, but instead to operations based on decoding and execution of the claimed instruction.
The examiner asserts that applicant’s claims literally recite mathematical calculations, i.e., multiplying, adding, scaling, etc. Thus, the claim recites an abstract idea.
On page 16 of applicant’s response, applicant’s argument regarding the 1st bullet is non-persuasive. Applicant argues that the invention allows a processor to perform an FFT operation. However, this is not improving the processor itself or improving a technology. Instead, applicant is merely invoking a generic computer as a tool to perform the FFT butterfly math in response to an instruction. The courts have stated that including an instruction to implement an abstract idea does not integrate the abstract idea into a practical application, nor does it amount to significantly more. The courts have also indicated that automating a manual process using a generic computer (e.g. which would cover automating calculations for FFT) does not amount to an improvement in computer functionality (MPEP 2106.05(a)(I), 2nd list of examples, item (iii)).
On page 16 of applicant’s response, applicant’s argument regarding the 3rd bullet is non-persuasive. The examiner asserts that applicant is not claiming a particular machine. Applicant is claiming a generic parallel machine with ubiquitous components such as a decoder and execution unit, and packed registers. From MPEP 2106.05(B)(I), the courts deemed a claimed particular type of antenna having a specific shape to be a particular machine. A generic parallel computer is not a particular machine like said specific antenna. In addition, from MPEP 2106.05(b)(III), the decoder and packed registers are only used nominally for decoding and retrieving/storing input data used in the math operations and results of the math operations. Thus, the machine components to not impose meaningful limits on the claim. “Use of a machine that contributes only nominally or insignificantly to the execution of the claimed method (e.g., in a data gathering step or in a field-of-use limitation) would not integrate a judicial exception or provide significantly more.”
On page 16 of applicant’s response, applicant’s argument regarding the 5th bullet is non-persuasive. To be subject-matter eligible, additional elements (not the abstract idea itself) in the claim must provide other meaningful limitations. An FFT butterfly operation is not an additional element. It is a mathematical operation. Thus, FFT butterfly cannot be relied on to provide a meaningful limitation. Additional elements such as a decoder, execution unit, and packed registers are generic and do not provide meaningful limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183