Office Action Predictor
Application No. 17/590,435

INSPECTION DEVICE, INSPECTION METHOD OF SEMICONDUCTOR SUBSTRATE, MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Final Rejection §102§103
Filed
Feb 01, 2022
Examiner
JEFFERSON, QUOVAUNDA
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
2 (Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
3y 0m
To Grant
89%
With Interview

Examiner Intelligence

79%
Career Allow Rate
692 granted / 878 resolved
Without
With
+10.4%
Interview Lift
avg trend
3y 0m
Avg Prosecution
48 pending
926
Total Applications
career history

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
58.1%
+18.1% vs TC avg
§102
26.7%
-13.3% vs TC avg
§112
9.3%
-30.7% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kikuchi, JP 2017-220483A (as cited in previous Office Action) PNG media_image1.png 378 702 media_image1.png Greyscale Regarding claim 1, Kikuchi teaches an inspection device that inspects a semiconductor substrate, comprising: a stage; a first ring 7 (figure 5); and a second ring 11 (figure 2), wherein a first recess 6 is provided on an upper surface of the stage and a side surface of the stage, the first recess has a ring shape in plan view (figures 1 and 7, as stated above), the first ring is elastic ([0028] of Applicant’s translation), the first ring is disposed in the first recess, the second ring presses the first ring in an inward direction of the ring shape so as to press the first ring toward an inner side surface of a side surface of the first recess, the first ring projects toward an upper side further than the upper surface of the stage (as shown in figure 6), in the stage, an exhaust hole 3 is provided, the exhaust hole including an opening in a region of the upper surface of the stage surrounded by the first recess in plan view (such as shown in figure 1)), and the semiconductor substrate placed on the first ring is vacuum-sucked with exhaustion through the exhaust hole (as shown in figure 7). Regarding claim 12, Kikuchi teaches the first ring is an O-ring (figure 6). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi, JP 2017-220483A (as cited in previous Office Action) Regarding claim 10, Kikuchi fails to teach the inner side surface of the side surface of the first recess inclines so that an upper side of the inner side surface is located on an outer side of the stage than a lower side of the inner side surface. However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi as applied to claim above, and further in view of Yamamoto et al, US Patent 7,078,262 (as cited in previous Office Action) Regarding claim 11, Kikuchi teaches a vacuum pump, wherein the exhaustion is performed using the vacuum pump ([0049] of Applicant’s translation). Kikuchi fails to teach a pressure gauge, wherein the pressure gauge measures a pressure of a region surrounded by the semiconductor substrate, the first ring, and the stage. Yamamoto teaches a pressure gauge 10, wherein the pressure gauge measures a pressure of a region surrounded by the semiconductor substrate, the first ring, and the stage (as represented 7/8 in figure 4). The pressure gauge is used with the wafer stage in order to determine whether the wafer is held normally by the pressing plate It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yamamoto with that of Kikuchi because the pressure gauge is generally-used with the wafer stage as a means of correctly holding the wafer to the stage, thereby preventing warping the substrate. Allowable Subject Matter Claims 2-9 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 2, the prior art fails to anticipate or render obvious the claimed invention including “...the first ring toward an inner side surface of a side surface of the first recess, the first ring projects toward an upper side further than the upper surface of the stage, in the stage, an exhaust hole is provided, the exhaust hole including an opening in a region of the upper surface of the stage surrounded by the first recess in plan view, and the semiconductor substrate placed on the first ring is vacuum-sucked with exhaustion through the exhaust hole; a first sheet disposed in a region of the upper surface of the stage surrounded by the first recess in plan view; and a second sheet disposed on the first sheet, wherein the second sheet is a porous sheet....” in combination with the remaining limitations. Claims 3-9 are dependent upon claim 2 and are therefore allowable. With regards to independent claims 2, the cited prior art(s) of record teach all of the limitations presented, but fail to recite the limitation above. Further, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Therefore, claims 2-9 have been found to be allowable. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant's arguments filed 10 September 2025 with regards to 35 USC 102 rejection of claim 1 have been fully considered but they are not persuasive. In response to Applicant’s argument that the cited prior art of Kikuchi fails to teach the amended limitation of “a first recess is provided on an upper surface of the stage and a side surface of the stage”, Kikuchi teaches this limitation, as shown in figure below. Therefore, the refence of Kikuchi meets the limitation of this claim PNG media_image1.png 378 702 media_image1.png Greyscale Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. QVJ /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Feb 01, 2022
Application Filed
Jun 10, 2025
Non-Final Rejection — §102, §103
Sep 10, 2025
Response Filed
Dec 09, 2025
Final Rejection — §102, §103
Mar 16, 2026
Request for Continued Examination
Mar 31, 2026
Response after Non-Final Action

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
89%
With Interview (+10.4%)
3y 0m
Median Time to Grant
Moderate
PTA Risk
Based on 878 resolved cases by this examiner