Prosecution Insights
Last updated: October 22, 2026
Application No. 17/590,697

TEMPERATURE-BASED SEMICONDUCTOR WAFER SINGULATION

Final Rejection §103
Filed
Feb 01, 2022
Examiner
SEHAR, FAKEHA
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
4 (Final)
83%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
86 granted / 104 resolved
+14.7% vs TC avg
Strong +19% interview lift
Without
With
+19.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
37 currently pending
Career history
154
Total Applications
across all art units

Statute-Specific Performance

§103
49.2%
+9.2% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
38.3%
-1.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 104 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment This Office Action is in response to Applicant’s Amendment filed on September 09, 2026. Claim 8 has been amended. No new claims have been added. Claims 3, 10 and 16 have been canceled. Currently, claims 1-2, 4-9, 11-15 and 17-20 are pending. Response to Arguments Applicant's arguments filed on September 09, 2026 have been fully considered but they are not persuasive. The Applicant argues that Hoshino’s crack joining disclosure, including paragraph [0047], cannot be separated from Hoshino’s specific liquid expansion mechanism. According to Applicant, Hoshino first forms openings/cracks extending to a wafer surface, introduces liquid into those openings and then applies an external stimulus such as freezing to increase the liquid volume and thereby propagate or merge the cracks. The Applicant therefore contends that Hoshino does not teach the claimed mechanism in which heating and subsequent cooling of the wafer itself causes contraction and crack joining. Applicant further argues that combining Hoshino with Mihai would require adding surface open cracks, liquid introduction and freezing to Mihai’s dry thermal shock process thereby fundamentally redesigning Mihai and rendering it unsatisfactory for its intended purpose. Applicant also argues that the Examiner’s stated rationale that connected cracks improve separation efficiency is too generic and does not address the different mechanisms. The Examiner respectfully disagrees. The rejection does not propose bodily incorporating Hoshino’s complete liquid introduction and freezing process into Mihai. The test for obviousness is not whether every feature of a secondary reference can be physically incorporated into the primary reference but what the combined teachings would have suggested to one of ordinary skill in the art. MPEP 2145. Hoshino teaches a plurality of modified regions having respective associated cracks arranged along an intended separation path wherein the cracks associated with adjacent modified regions are initially separate. Hoshino further demonstrates that when fracture driving stress is applied to this configuration, the initially separate cracks propagate and connect to form a more continuous separation path. In Hoshino’s particular embodiment the fracture driving stress is generated by expansion of a liquid medium introduced into the crack for example, upon freezing. Thus, Hoshino establishes both the initially separate crack associated modified region configuration and that application of stress to such a configuration can cause the associated cracks to extend and join. Mihai independently teaches another mechanism for generating fracture propagating stress. Specifically, Mihai subjects a wafer having a laser induced modified region to heating followed by cooling thereby generating thermal shock that causes fracture to initiate from the modified region and propagate through the wafer along the intended separation path. Accordingly, although Hoshino and Mihai generate fracture driving stress by different physical mechanisms both references teach the use of stress to propagate fracture from or through laser modified weakened regions to facilitate wafer separation. The proposed combination therefore does not require substituting Hoshino’s liquid expansion process for Mihai’s thermal shock process. Rather, Hoshino provides the known arrangement of a plurality of initially separate crack associated modified regions and demonstrates that application of fracture driving stress to that arrangement causes the cracks to propagate and connect while Mihai provides the thermal shock mechanism for generating the fractured driving stress in the proposed combination. One of ordinary skill in art would have had reason to apply Hoshino’s arrangement of a plurality of aligned modified regions having initially separate associated cracks to Mihai’s thermal shock process because the aligned modified regions and cracks would define a predetermined fracture propagation path along the intended division line. In view of Hoshino’s teaching that fracture driving stress applied to such an arrangement causes the initially separate cracks to propagate and connect together with Mihai’s teaching that thermal shock provides fracture driving stress capable of propagating fracture from a modified region, one of ordinary skill would have reasonably expected that applying Mihai’s thermal shock process to Hoshino’s arrangement would propagate fracture through the intervening material and connect the associated cracks thereby forming a continuous fracture path and facilitating controlled and reliable wafer separation. Accordingly, Applicant’s contention that the combination necessarily requires Hoshino’s liquid introduction and freezing sequence is not persuasive. The proposed combination relies on Hoshino for the crack associated modified region arrangement and the demonstrated response of that arrangement to fracture driving stress and on Mihai for the claimed thermal shock mechanism used to generate that stress. The Applicant argues that Chao is non-analogous art because Chao is directed to accelerate thermal stress reliability testing for detecting defects such as metal film peeling and void formation whereas the claimed invention is directed to wafer singulation and propagation/joining of laser induced cracks. Applicant further argues that Chao’s approximately 30 second timing is merely a fixed apparatus or transfer constraint and is not a result effective variable that could properly be characterized as a matter of routine optimization. The Examiner respectfully disagrees. A reference need not address the identical ultimate purpose of the claimed invention to constitute analogous art. A reference is analogous if it is either within the same field of endeavor or is reasonably pertinent problem addressed by the inventor. MPEP 2141.01(a). Although Chao is directed to reliability testing rather than wafer singulation. Chao specifically concerns a semiconductor wafer subjected to rapid heating followed by rapid cooling to create thermal shock. Chao explicitly teaches rapidly transferring a heated semiconductor wafer to a nearby cooling chamber and cooling it from at least about 350°C to no more than about 70°C in about 30 seconds to achieve thermal shock effect. Thus, Chao is reasonably pertinent to the issue for which it is relied upon in the rejection merely the timing of a rapid transition between a first higher temperature and a second lower temperature applied to a semiconductor wafer to produce a thermal shock condition. The fact that Chao ultimately uses that thermal shock for reliability testing rather than wafer singulation does not make its teaching concerning rapid thermal transition irrelevant to a person of ordinary skill considering the timing of thermal shock in a semiconductor wafer. With respect to Applicant’s argument that the approximately 30 second interval is merely a logistical consequence of robotic transfer, Chao does not describe the rapid transition as an incidental apparatus limitation. Rather, Chao explains that the cooling chamber is positioned nearby so that the heated wafer may be rapidly transported to the cooling chamber for the thermal shock test and further states that to achieve the thermal shock effect the heated wafer should be cooled from at least about 350°C to no greater than 70°C within a short period of 30 seconds. Accordingly, the rapid timing is functionally related to producing the desired thermal shock condition and is not merely an arbitrary consequence of equipment layout. Accordingly, Chao is not relied upon merely for the proposition that the claimed timing could have been obtained through routine optimization. Rather, Chao explicitly teaches rapid heating/cooling of a semiconductor wafer within a short time period of about 30 seconds for the purpose of generating thermal shock. Therefore, Chao provides direct evidence that such a short thermal transition interval was known in the semiconductor wafer art. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2 and 4-5 are rejected under 35 U.S. 103 as being unpatentable over Mihai (KR 20190092926 A) in view of Hoshino et al. (US 2020/0381303 A1; hereafter Hoshino), Shiomi (2019/0088548 A1) and Chao et al. (US 2003/0072350 A1; hereafter Chao). Regarding claim 1, Mihai teaches a method for manufacturing a semiconductor package, comprising: forming … stealth damage locations along a thickness of a semiconductor wafer using a laser (see e.g., a modified layer 17 is formed in the wafer 11 along the division scheduled line 13 by a laser processing apparatus 2. Conditions such as the wavelength of the laser beam L, the power density, the repetition frequency, the moving speed of the holding table 4, and the like are set within a range in which the modified layer 17 suitable for dividing the wafer 11 can be formed; the modified layer 17 along the division line 13 has a column of structurally modified or damaged regions), applying a first temperature to the semiconductor wafer to cause the semiconductor wafer to expand (see e.g., after the formation of the modified layer 17 the wafer 11 is placed on a heating table 12 and a heater 14 heats the surface 11a side of the wafer. The temperature of the heater 14 maybe set to 95 degree C, and the surface 11a side of the wafer 11 is heated to 85 degree C or more. Thus, by heating the surface 11a side of the wafer 11 to 85 degree C or more, it becomes easy to form the temperature difference required for generation of a thermal shock. The wafer is heated immediately after being placed on the heating table 12 hence the time required to divide the wafer can be further shortened to improve the throughput; the heating will cause the wafer to expand); and applying a second temperature less than the first temperature to the semiconductor wafer to cause the semiconductor wafer to contract (see e.g., after the wafer 11 is heated the entire exposed back surface 11b is rapidly cooled to form a large temperature difference inside the wafer 11 (between the surface 11a and 11b). The cooling fluid may be cooled to a temperature of about 0.1 degree C to 10 degree C. The required temperature difference means a temperature difference that can obtain a thermal shock that exceeds the breaking stress of the wafer 11. This temperature difference is determined depending on, for example, the material and thickness of the wafer 11, the state of the modified layer 17, and the like; the cooling will cause the wafer to contract). Mihai does not explicitly teach “forming a column of stealth damage locations… each of the stealth damage locations having a semiconductor wafer crack associated therewith;… join two of the semiconductor wafer cracks with another semiconductor wafer crack that is between the two of the semiconductor wafer cracks” In a similar field of endeavor Hoshino teaches forming a column of stealth damage locations…(see e.g., a laser beam applied to a wafer along a division line 14 so as to form a plurality of hole regions along the division line. Each hole region may be composed of a modified region and a crack. These modified regions along the division line are in a vertical column as shown in Figures 3 and 4), each of the stealth damage locations having a semiconductor wafer crack associated therewith (see e.g., the laser beam maybe applied to a wafer along a division line so as to form a plurality of hole regions along the division line. Each hole region may be composed of a modified region and an opening. Modified regions are the regions where the wafer structure has been modified or damaged by the laser beam and the openings are the cracks originating from the modified regions as a result of the structural modification or damage, Para [0023], [0025], [0029], [0030], [0036], [0045]);… join two of the semiconductor wafer cracks with another semiconductor wafer crack that is between the two of the semiconductor wafer cracks Hoshino teaches an arrangement of initially separate cracks associated with respective modified regions and further teaches that when fracture driving stress is applied to that arrangement, the cracks propagate and connect. In Hoshino the stress is generated by expansion of a liquid medium introduced into the cracks. Thus, Hoshino establishes both the initially separate crack associated modified region configuration and that application of stress to such a configuration can cause cracks to extend and join. Mihai independently teaches generating fracture propagating stress by heating and subsequent cooling of a semiconductor wafer having a laser modified region thereby producing thermal shock that causes fracture to initiate at the modified region and propagate through the wafer. Accordingly, it would have been obvious to one skilled in art to employ Hoshino’s arrangement of initially separate crack associated modified regions in Mihai’s thermal shock process. Hoshino demonstrates that application of fracture driving stress to the aligned crack associated modified regions causes the cracks to propagate and connect while Mihai teaches that thermal shock provides a fracture driving stress capable of propagating fracture from a modified region. Therefore, one of ordinary skill would have reasonably expected Mihai’s thermal shock stress, when applied to Hoshino’s arrangement, to propagate the fractures through the intervening material and thereby join the semiconductor wafer cracks in fluid communication. Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to employ Hoshino’s plurality of aligned crack associated modified regions in Mihai’s thermal shock process because the aligned weakened regions would provide successive fracture propagation locations along the intended division path. Since Mihai teaches that thermal stress propagates fracture from a modified region, a skilled artisan would have reasonably expected the thermally induced fracture to propagate through the successive weakened regions and connect the associated cracks thereby forming a continuous fracture path and facilitating controlled and reliable wafer separation. Mihai does not explicitly teach “wherein a difference between the first and second temperatures is at least 100 degrees Celsius”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). In a similar field of endeavor Shiomi teaches wherein a difference between the first and second temperatures is at least 100 degrees Celsius (see e.g., the groove GV is heated up to 180° C. by laser emission by the heater 20. Following the heating of the groove GV by the heater 20, the cooler 30 cools the groove GV down to −186° C. by spraying liquid nitrogen. This makes the temperature difference 180° C.+186° C.=366° C., which exceeds the thermal shock resistance temperature of 365° C of the groove. This makes it possible to cleave the semiconductor wafer 2 at the groove GV, Paras [0044], [0045], Figure 4) Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement the Shiomi’s teachings of wherein a difference between the first and second temperatures is at least 100 degrees Celsius in the method of Mihai in order to optimize the temperature difference that can obtain a thermal shock that exceeds the breaking stress of the wafer. This temperature difference is determined depending on, for example, the material and thickness of the wafer, the state of the modified layer. Mihai does not explicitly teach “wherein a time between the application of the first temperature and the application of the second temperature is less than 2 minutes”. Mihai teaches that after heating the wafer, a cooling fluid is applied to the back surface 11b of the wafer to cause rapid cooling. This process generates a large temperature difference inside wafer and creating thermal shock that breaks the wafer at the modified layer. While Mihai does not explicitly state the time interval between these heating and cooling steps, the required “large temperature difference” necessitates that cooling begins immediately following the heating step. In a similar field of endeavor Chao teaches generating thermal shock in a pre-processed wafer via rapid thermal process within a defined timeframe. Chao specifically teaches inducing this shock by rapidly heating the wafer to at least 350.degree.C. within a heating chamber, followed by a rapid transfer to a nearby cooling chamber where the wafer is cooled from at least 350.degree.C. to 70.degree.C. or lower within a short time period of about 30 seconds. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chao’s teachings of wherein a time between the application of the first temperature and the application of the second temperature is less than 2 minutes in the method of Mihai to generate an abrupt temperature gradient and resulting thermal stress sufficient to produce the desired thermal shock effect. Regarding claim 2, Mihai, as modified by Hoshino, Shiomi and Chao, teaches the limitations of claim 1 as mentioned above. Mihai does not explicitly teach “further comprising stretching the semiconductor wafer to separate the semiconductor wafer along the two semiconductor wafer cracks”. In a similar field of endeavor Hoshino teaches further comprising stretching the semiconductor wafer to separate the semiconductor wafer along the two semiconductor wafer cracks (see e.g. After the wafer 2 has been fully divided in this manner, the sheeting 15 may be radially expanded, e.g., by using an expansion drum, in order to increase the distance between adjacent dies 24. In this way, any damage to the dies 24 due to unintentionally touching or rubbing against each other can be reliably prevented. Subsequently, the dies 24 may be picked up from the sheeting IS for farther processing, transport or storage thereof, Para [0146]). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Hoshino’s teachings of further comprising stretching the semiconductor wafer to separate the semiconductor wafer along the two semiconductor wafer cracks in the method of Mihai in order to separate the wafer along the cracks. Regarding claim 4, Mihai, as modified by Hoshino, Shiomi and Chao, teaches the limitations of claim 1 as mentioned above. Mihai does not explicitly teach “further comprising applying the first temperature for a duration ranging from 5 minutes to 10 minutes”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). It is noted that Mihai teaches placing the wafer on the heating table 12 and heating the wafer side 11a by the heater 14 to a temperature of 85 degree. C. or more. While Mihai does not explicitly quantify the heating duration, the selection of an appropriate heating time would have been a matter of routine optimization to achieve Mihai’s desired thermal shock sufficient to break the wafer at the modified layer. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize the duration of the heating process disclosed by Mihai by applying the first temperature for a routine duration, such as claimed 5 to 10 minutes, to achieve the expected result of improving throughput and shortening the time required for wafer division. Regarding claim 5, Mihai, as modified by Hoshino, Shiomi and Chao, teaches the limitations of claim 1 as mentioned above. Mihai does not explicitly teach “further comprising applying the second temperature for a duration of less than 2 minutes”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). It is noted that Mihai teaches placing the cooling unit 22 to spray a cooling fluid onto the back surface 11b of the wafer 11 to create a sufficient temperature difference that induces breakage at the modified layer 17 via a thermal shock. While Mihai does not explicitly quantify the cooling duration, the selection of an appropriate cooling time would have been a matter of routine optimization to achieve Mihai’s desired thermal shock sufficient to break the wafer at the modified layer. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize the duration of the cooling operation disclosed by Mihai by applying the second temperature for a routine duration, such as claimed less than 2 minutes, to achieve the expected result of improving throughput and shortening the time required for wafer division. Claim 6 is rejected under 35 U.S. 103 as being unpatentable over Mihai (KR 20190092926 A) in view of Hoshino et al. (US 2020/0381303 A1; hereafter Hoshino), Shiomi (US 2019/0088548 A1) and Chao et al. (US 2003/0072350 A1; hereafter Chao) and further in view of Yodo et al. (JP 6851690 B2; hereafter Yodo). Regarding claim 6, Mihai, as modified by Hoshino, Shiomi and Chao, teaches the limitations of claim 1 as mentioned above. Mihai does not explicitly teach “wherein forming the column of stealth damage locations includes using a power of the laser ranging from 0.2 Watts to 0.4 Watts”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). In a similar field of endeavor Yodo teaches wherein forming the column of stealth damage locations includes using a power of the laser ranging from 0.2 Watts to 0.4 Watts (see e.g., In order to form the modified layer 19 the laser output power, wavelength, laser beam repetition frequency and chuck table moving speed maybe as per the wafer material. For a silicon, gallium arsenide, quartz or sapphire substrate, the laser output may be from 0.1W to 2W. For a gallium nitride substrate, the laser output power maybe from 0.02W to 0.2W. For a silicon carbide substrate, the laser output power maybe typically 0.1W). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Yodo’s teachings of wherein forming the column of stealth damage locations includes using a power of the laser ranging from 0.2 Watts to 0.4 Watts in the method of Mihai in order to optimize the power of the laser according to the wafer material. Claim 7 is rejected under 35 U.S. 103 as being unpatentable over Mihai (KR 20190092926 A) in view of Hoshino et al. (US 2020/0381303 A1; hereafter Hoshino), Shiomi (US 2019/0088548 A1) and Chao et al. (US 2003/0072350 A1; hereafter Chao) and further in view of Morikazu et al. (US 2018/0161921 A1; hereafter Morikazu). Regarding claim 7, Mihai, as modified by Hoshino, Shiomi and Chao, teaches the limitations of claim 1 as mentioned above. Mihai does not explicitly teach “wherein a distance between the stealth damage locations in the column ranges from 25 microns to 80 microns”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). In a similar field of endeavor Morikazu teaches wherein a distance between the stealth damage locations in the column ranges from 25 microns to 80 microns (see e.g., The distance between adjacent rows of modified regions in the width direction of the at least one division line, i.e., between centres of the modified regions of the adjacent rows, may be in the range of 3 μm to 50 μm, preferably 5 μm to 40 μm and more preferably 8 μm to 30 μm. The number of rows may be in the range of 2 to 20, preferably 4 to 18, more preferably 5 to 15 and even more preferably 8 to 12, Para [0071], Figure 9). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Morikazu’s teachings of wherein a distance between the stealth damage locations in the column ranges from 25 microns to 80 microns in the method of Mihai as such modification constitutes more routine experimentation to find optimal, workable ranges for thermal stress management. Claims 8, 11 and 14 are rejected under 35 U.S. 103 as being unpatentable over Mihai (KR 20190092926 A) in view of Hoshino et al. (US 2020/0381303 A1; hereafter Hoshino) and Chao et al. (US 2003/0072350 A1; hereafter Chao). Regarding claim 8, Mihai teaches a method for manufacturing a semiconductor package (see e.g., Figures 1-3), comprising: forming a first stealth damage location in a semiconductor wafer using a laser, (see e.g., a modified layer 17 is formed in the wafer 11 along the division scheduled line 13 by a laser processing apparatus 2. Conditions such as the wavelength of the laser beam L, the power density, the repetition frequency, the moving speed of the holding table 4, and the like are set within a range in which the modified layer 17 suitable for dividing the wafer 11 can be formed), and heating the semiconductor wafer (see e.g., after the formation of the modified layer 17 the wafer 11 is placed on a heating table 12 and a heater 14 heats the surface 11a side of the wafer. Although heating conditions are arbitrary, the temperature of the heater 14 maybe set to 95 degree C, and the surface 11a side of the wafer 11 is heated to 85 degree C or more. Thus, by heating the surface 11a side of the wafer 11 to 85 degree C or more, it becomes easy to form the temperature difference required for generation of a thermal shock. The wafer is heated immediately after being placed on the heating table 12 hence the time required to divide the wafer can be further shortened to improve the throughput) and subsequently cooling the semiconductor wafer (see e.g., after the wafer 11 is heated the entire exposed back surface 11b is rapidly cooled to form a large temperature difference inside the wafer 11 (between the surface 11a and 11b). The cooling fluid may be cooled to a temperature of about 0.1 degree C to 10 degree C. The required temperature difference means a temperature difference that can obtain a thermal shock that exceeds the breaking stress of the wafer 11. This temperature difference is determined depending on, for example, the material and thickness of the wafer 11, the state of the modified layer 17, and the like) Mihai does not explicitly teach “the first stealth damage location in fluid communication with a first semiconductor wafer crack; forming a second stealth damage location in the semiconductor wafer, the second stealth damage location in fluid communication with a second semiconductor wafer crack, wherein after forming the first and second stealth damage locations and before a subsequent heating step, the first semiconductor wafer crack and the second semiconductor wafer crack are not in fluid communication with each other;… form a third semiconductor crack that joins the first and second semiconductor cracks in fluid communication with each other wherein the third semiconductor crack is between the first semiconductor wafer crack and the second wafer crack”; In a similar field of endeavor Hoshino teaches the first stealth damage location in fluid communication with a first semiconductor wafer crack; forming a second stealth damage location in the semiconductor wafer, the second stealth damage location in fluid communication with a second semiconductor wafer crack (see e.g., the laser beam maybe applied to a wafer along a division line to form a plurality of hole regions along the division line. Each hole region may be composed of a modified region and an opening. Modified regions are the regions where the wafer structure has been modified or damaged by the laser beam and the openings are the cracks originating from the modified regions as a result of the structural modification or damage, Para [0023], [0025], [0029], [0030], [0036], [0045]); wherein after forming the first and second stealth damage locations and before a subsequent heating step, the first semiconductor wafer crack and the second semiconductor wafer crack are not in fluid communication with each other;… to form a third semiconductor crack that joins the first and second semiconductor cracks in fluid communication with each other wherein the third semiconductor crack is between the first semiconductor wafer crack and the second wafer crack Hoshino teaches forming a plurality of modified regions having respective associated semiconductor wafer cracks, wherein the cracks associated with adjacent modified regions are initially separate from one another and therefore are not in fluid communication. Hoshino further teaches that upon application of a fracture driving stress to this configuration the cracks propagate and connect. In Hoshino the fracture driving stress is generated by expansion of a liquid medium introduced into the cracks. Thus, Hoshino establishes both the initially separate crack associated modified region configuration and that application of stress to such a configuration can cause the cracks to extend and join. Mihai independently teaches generating fracture propagating stress by heating and subsequently cooling a semiconductor wafer having a modified region thereby producing thermal shock that causes fracture to initiate at the modified region and propagate through the wafer along the intended separation path. Accordingly, it would have been obvious to one skilled in art to employ Hoshino’s arrangement of initially separate cracks associated with first and second modified regions in the thermal shock process of Mihai. After formation of the first and second modified regions and before application of Mihai’s subsequent heating step, the first and second associated cracks would remain separate and not in fluid communication with each other. Hoshino demonstrates that application of fracture driving stress to such an arrangement causes the cracks to propagate and connect while Mihai teaches the thermal shock provides fracture driving stress capable of propagating fracture from a modified region. Therefore, one of ordinary skill would have reasonably expected Mihai’s heating and subsequent cooling steps to propagate fracture through the intervening material between the first and second modified regions thereby forming a third semiconductor wafer crack between the first and second cracks and join the first and second cracks in fluid communication with each other. Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to employ Hoshino’s plurality of aligned crack associated modified regions in Mihai’s thermal shock process because the aligned weakened regions would provide successive fracture propagation locations along the intended division path. Since Mihai teaches that thermal stress propagates fracture from a modified region, a skilled artisan would have reasonably expected the thermally induced fracture to propagate through the successive weakened regions and connect the associated cracks thereby forming a continuous fracture path and facilitating controlled and reliable wafer separation. Mihai does not explicitly teach “wherein a time between application of the first and second temperatures does not exceed 2 minutes.” Mihai teaches that after heating the wafer, a cooling fluid is applied to the back surface 11b of the wafer to cause rapid cooling. This process generates a large temperature difference inside wafer and creating thermal shock that breaks the wafer at the modified layer. While Mihai does not explicitly state the time interval between these heating and cooling steps, the required “large temperature difference” necessitates that cooling begins immediately following the heating step. In a similar field of endeavor Chao teaches generating thermal shock in a pre-processed wafer via rapid thermal process within a defined timeframe. Chao specifically teaches inducing this shock by rapidly heating the wafer to at least 350.degree.C. within a heating chamber, followed by a rapid transfer to a nearby cooling chamber where the wafer is cooled from at least 350.degree.C. to 70.degree.C. or lower within a short time period of about 30 seconds. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chao’s teachings of wherein a time between the application of the first temperature and the application of the second temperature is less than 2 minutes in the method of Mihai to generate an abrupt temperature gradient and resulting thermal stress sufficient to produce the desired thermal shock effect. Regarding claim 11, Mihai, as modified by Hoshino and Chao, teaches the limitations of claim 8 as mentioned above. Mihai does not explicitly teach “wherein heating the semiconductor wafer includes applying the first temperature to the semiconductor wafer for a time ranging from 5 minutes to 10 minutes, and wherein cooling the semiconductor wafer includes applying the second temperature to the semiconductor wafer for another time ranging from 1 minute to 5 minutes”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). It is noted that Mihai teaches placing the wafer on the heating table 12 and heating the wafer side 11a by the heater 14 to a temperature of 85 degree. C. or more followed by placing the cooling unit 22 to spray a cooling fluid onto the back surface 11b of the wafer 11 to create a sufficient temperature difference that induces breakage at the modified layer 17 via a thermal shock. While Mihai does not explicitly quantify the heating and cooling durations, the selection of appropriate heating and cooling times would have been a matter of routine optimization to achieve Mihai’s desired thermal shock sufficient to break the wafer at the modified layer. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize the duration of the heating and cooling process disclosed by Mihai by applying the first and second temperatures for a routine duration, such as claimed 5 to 10 minutes, and 1 minute to 5 minutes respectively, to achieve the expected result of improving throughput and shortening the time required for wafer division. Regarding claim 14, Mihai, as modified by Hoshino and Chao, teaches the limitations of claim 8 as mentioned above. Mihai does not explicitly teach “wherein the first and second stealth damage locations are in a vertical column”. In a similar field of endeavor Hoshino teaches wherein the first and second stealth damage locations are in a vertical column (see e.g., a laser beam applied to a wafer along a division line 14 so as to form a plurality of hole regions along the division line. Each hole region may be composed of a modified region and a crack. These modified regions along the division line are in a vertical column as shown in Figures 3 and 4). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Hoshino’s teachings of wherein the first and second stealth damage locations are in a vertical column in the method of Mihai in order to vertically dice the wafer. Claim 9 is rejected under 35 U.S. 103 as being unpatentable over Mihai (KR 20190092926 A) in view of Hoshino et al. (US 2020/0381303 A1; hereafter Hoshino) and Chao et al. (US 2003/0072350 A1; hereafter Chao) and further in view of Shiomi (US 2019/0088548 A1). Regarding claim 9, Mihai, as modified by Hoshino and Chao, teaches the limitations of claim 8 as mentioned above. Mihai further teaches wherein heating the semiconductor wafer includes applying a first temperature to the semiconductor wafer (see e.g., after the formation of the modification layer 17 the wafer 11 is placed on a heating table 12 and a heater 14 heats the surface 11a side of the wafer. Although heating conditions are arbitrary, the temperature of the heater 14 maybe set to 95 degree C, and the surface 11a side of the wafer 11 is heated to 85 degree C or more) and cooling the semiconductor wafer includes applying a second temperature to the semiconductor wafer (see e.g., after the wafer 11 is heated the entire exposed back surface 11b is rapidly cooled to form a large temperature difference inside the wafer 11 (between the surface 11a and 11b). The cooling fluid may be cooled to a temperature of about 0.1 degree C to 10 degree C), Mihai does not explicitly teach “a difference between the first and second temperatures being at least 100 degrees Celsius”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). In a similar field of endeavor Shiomi teaches wherein a difference between the first and second temperatures is at least 100 degrees Celsius (see e.g., the groove GV is heated up to 180° C. by laser emission by the heater 20. Following the heating of the groove GV by the heater 20, the cooler 30 cools the groove GV down to −186° C. by spraying liquid nitrogen. This makes the temperature difference 180° C.+186° C.=366° C., which exceeds the thermal shock resistance temperature of 365° C of the groove. This makes it possible to cleave the semiconductor wafer 2 at the groove GV, Paras [0044], [0045], Figure 4) Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement the Shiomi’s teachings of wherein a difference between the first and second temperatures is at least 100 degrees Celsius in the method of Mihai in order to optimize the temperature difference that can obtain a thermal shock that exceeds the breaking stress of the wafer. This temperature difference is determined depending on, for example, the material and thickness of the wafer, the state of the modified layer. Claim 12 is rejected under 35 U.S. 103 as being unpatentable over Mihai (KR 20190092926 A) in view of Hoshino et al. (US 2020/0381303 A1; hereafter Hoshino) and Chao et al. (US 2003/0072350 A1; hereafter Chao) and further in view of Yodo et al. (JP 6851690 B2; hereafter Yodo). Regarding claim 12, Mihai, as modified by Hoshino and Chao, teaches the limitations of claim 8 as mentioned above. Mihai does not explicitly teach “wherein forming the first and second stealth damage locations includes using a laser power of ranging from 0.2 Watts to 0.4 Watts”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). In a similar field of endeavor Yodo teaches wherein forming the first and second stealth damage locations includes using a laser power of ranging from 0.2 Watts to 0.4 Watts (see e.g., In order to form the modified layer 19 the laser output power, wavelength, laser beam repetition frequency and chuck table moving speed maybe as per the wafer material. For a silicon, gallium arsenide, quartz or sapphire substrate, the laser output may be from 0.1W to 2W. For a gallium nitride substrate, the laser output power maybe from 0.02W to 0.2W. For a silicon carbide substrate, the laser output power maybe typically 0.1W). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Yodo’s teachings of wherein forming the first and second stealth damage locations includes using a laser power of ranging from 0.2 Watts to 0.4 Watts in the method of Mihai in order to optimize the power of the laser according to the wafer material. Claim 13 is rejected under 35 U.S. 103 as being unpatentable over Mihai (KR 20190092926 A) in view of Hoshino et al. (US 2020/0381303 A1; hereafter Hoshino) and Chao et al. (US 2003/0072350 A1; hereafter Chao) and further in view of Morikazu et al. (US 2018/0161921 A1; hereafter Morikazu). Regarding claim 13, Mihai, as modified by Hoshino and Chao, teaches the limitations of claim 8 as mentioned above. Mihai does not explicitly teach “wherein a distance between the first and second stealth damage locations ranges from 25 microns to 80 microns”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). In a similar field of endeavor Morikazu teaches wherein a distance between the first and second stealth damage locations ranges from 25 microns to 80 microns (see e.g., The distance between adjacent rows of modified regions in the width direction of the at least one division line, i.e., between centres of the modified regions of the adjacent rows, may be in the range of 3 μm to 50 μm, preferably 5 μm to 40 μm and more preferably 8 μm to 30 μm. The number of rows may be in the range of 2 to 20, preferably 4 to 18, more preferably 5 to 15 and even more preferably 8 to 12, Para [0071], Figure 9) Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Morikazu’s teachings of wherein a distance between the first and second stealth damage locations ranges from 25 microns to 80 microns in the method of Mihai as such modification constitutes more routine experimentation to find optimal, workable ranges for thermal stress management. Claims 15, 17 and 20 are rejected under 35 U.S. 103 as being unpatentable over Mihai (KR 20190092926 A) in view of Hoshino et al. (US 2020/0381303 A1; hereafter Hoshino) and Chang et al. (US 2022/0189856 A1; hereafter Chang), Shiomi (US 2019/0088548 A1) and Chao et al. (US 2003/0072350 A1; hereafter Chao). Regarding claims 15, Mihai teaches a method for manufacturing a semiconductor package (see e.g., Figures 1-3), comprising: providing a semiconductor wafer having a first stealth damage location, (see e.g., a modified layer 17 is formed in the wafer 11 along the division scheduled line 13 by a laser processing apparatus 2. Conditions such as the wavelength of the laser beam L, the power density, the repetition frequency, the moving speed of the holding table 4, and the like are set within a range in which the modified layer 17 suitable for dividing the wafer 11 can be formed, Figures 1-3); heating the semiconductor wafer to a first temperature (see e.g., after the formation of the modification layer 17 the wafer 11 is placed on a heating table 12 and a heater 14 heats the surface 11a side of the wafer. Although heating conditions are arbitrary, the temperature of the heater 14 maybe set to 95 degree C, and the surface 11a side of the wafer 11 is heated to 85 degree C or more. Thus, by heating the surface 11a side of the wafer 11 to 85 degree C or more, it becomes easy to form the temperature difference required for generation of a thermal shock. The wafer is heated immediately after being placed on the heating table 12 hence the time required to divide the wafer can be further shortened to improve the throughput); cooling the semiconductor wafer to a second temperature (see e.g., after the wafer 11 is heated the entire exposed back surface 11b is rapidly cooled to form a large temperature difference inside the wafer 11 (between the surface 11a and 11b). The cooling fluid may be cooled to a temperature of about 0.1 degree C to 10 degree C. The required temperature difference means a temperature difference that can obtain a thermal shock that exceeds the breaking stress of the wafer 11. This temperature difference is determined depending on, for example, the material and thickness of the wafer 11, the state of the modified layer 17, and the like) Mihai does not explicitly teach “a first semiconductor wafer crack in fluid communication with the first stealth damage location, the semiconductor wafer having a second stealth damage location and a second semiconductor wafer crack in fluid communication with the second stealth damage location, wherein the first semiconductor wafer crack is directly above the second semiconductor wafer crack in a direction along a thickness of the semiconductor wafer…. thereby joining the first and second semiconductor wafer cracks in fluid communication with each other; stretching the semiconductor wafer to separate the semiconductor wafer along the first and second semiconductor wafer cracks, thereby producing a semiconductor die”; In a similar field of endeavor Hoshino teaches a first semiconductor wafer crack in fluid communication with the first stealth damage location, the semiconductor wafer having a second stealth damage location and a second semiconductor wafer crack in fluid communication with the second stealth damage location, wherein the first semiconductor wafer crack is directly above the second semiconductor wafer crack in a direction along a thickness of the semiconductor wafer (see e.g., the laser beam maybe applied to a wafer along a division line so as to form a plurality of hole regions along the division line. Each hole region may be composed of a modified region and an opening. Modified regions are the regions where the wafer structure has been modified or damaged by the laser beam and the openings are the cracks originating from the modified regions as a result of the structural modification or damage. As shown in Figures 3 and 4 the modified regions are above each other, Para [0023], [0025], [0029], [0030], [0036], [0045])… thereby joining the first and second semiconductor wafer cracks in fluid communication with each other Hoshino teaches an arrangement of initially separate cracks associated with respective modified regions and further teaches that when fracture driving stress is applied to that arrangement, the cracks propagate and connect. In Hoshino the stress is generated by expansion of a liquid medium introduced into the cracks. Thus, Hoshino establishes both the initially separate crack associated modified region configuration and that application of stress to such a configuration can cause cracks to extend and join. Mihai independently teaches generating fracture propagating stress by heating and subsequent cooling of a semiconductor wafer having a laser modified region thereby producing thermal shock that causes fracture to initiate at the modified region and propagate through the wafer. Accordingly, it would have been obvious to one skilled in art to employ Hoshino’s arrangement of initially separate crack associated modified regions in Mihai’s thermal shock process. Hoshino demonstrates that application of fracture driving stress to the aligned crack associated modified regions causes the cracks to propagate and connect while Mihai teaches that thermal shock provides a fracture driving stress capable of propagating fracture from a modified region. Therefore, one of ordinary skill would have reasonably expected Mihai’s thermal shock stress, when applied to Hoshino’s arrangement, to propagate the fractures through the intervening material and thereby join the first and second semiconductor wafer cracks in fluid communication. stretching the semiconductor wafer to separate the semiconductor wafer along the first and second semiconductor wafer cracks, thereby producing a semiconductor die (see e.g. After the wafer 2 has been fully divided in this manner, the sheeting 15 may be radially expanded, e.g., by using an expansion drum, to increase the distance between adjacent dies 24. In this way, any damage to the dies 24 due to unintentionally touching or rubbing against each other can be reliably prevented. Subsequently, the dies 24 may be picked up from the sheeting IS for farther processing, transport or storage thereof, Para [0146]). Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to employ Hoshino’s plurality of aligned crack associated modified regions in Mihai’s thermal shock process because the aligned weakened regions would provide successive fracture propagation locations along the intended division path. Since Mihai teaches that thermal stress propagates fracture from a modified region, a skilled artisan would have reasonably expected the thermally induced fracture to propagate through the successive weakened regions and connect the associated cracks thereby forming a continuous fracture path and facilitating controlled and reliable wafer separation. Mihai does not explicitly teach “second temperature that is at least 100 degrees from the first temperature”, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). In a similar field of endeavor Shiomi teaches wherein a difference between the first and second temperatures is at least 100 degrees Celsius (see e.g., the groove GV is heated up to 180° C. by laser emission by the heater 20. Following the heating of the groove GV by the heater 20, the cooler 30 cools the groove GV down to −186° C. by spraying liquid nitrogen. This makes the temperature difference 180° C.+186° C.=366° C., which exceeds the thermal shock resistance temperature of 365° C of the groove. This makes it possible to cleave the semiconductor wafer 2 at the groove GV, Paras [0044], [0045], Figure 4) Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement the Shiomi’s teachings of wherein a difference between the first and second temperatures is at least 100 degrees Celsius in the method of Mihai in order to optimize the temperature difference that can obtain a thermal shock that exceeds the breaking stress of the wafer. This temperature difference is determined depending on, for example, the material and thickness of the wafer, the state of the modified layer. Mihai does not explicitly teach “coupling the semiconductor die to a die pad and electrically coupling the semiconductor die to a conductive terminal; and covering the semiconductor die with a mold compound, the conductive terminal exposed to an exterior surface of the mold compound”. In a similar field of endeavor Chang teaches coupling the semiconductor die to a die pad and electrically coupling the semiconductor die to a conductive terminal; and covering the semiconductor die with a mold compound, the conductive terminal exposed to an exterior surface of the mold compound (see e.g., semiconductor die 502 is interconnected to the conductive leads 106 by bond wires 602. The encapsulant 802 encapsulating portions of the semiconductor die 502, die paddle 102 and conductive leads 106. The encapsulant 802 may be an epoxy molding compound dispensed during an injection molding encapsulation operation. The exposed portions of the conductive leads 106 are plated with conductive material, Paras [0013], [0015], Figure 8). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chang’s teachings of coupling the semiconductor die to a die pad and electrically coupling the semiconductor die to a conductive terminal; and covering the semiconductor die with a mold compound, the conductive terminal exposed to an exterior surface of the mold compound in the method of Mihai in order to form an IC package with external electrical connections. Mihai does not explicitly teach “wherein a time between the application of the first temperature and the application of the second temperature does not exceed 2 minutes”. Mihai teaches that after heating the wafer, a cooling fluid is applied to the back surface 11b of the wafer to cause rapid cooling. This process generates a large temperature difference inside wafer and creating thermal shock that breaks the wafer at the modified layer. While Mihai does not explicitly state the time interval between these heating and cooling steps, the required “large temperature difference” necessitates that cooling begins immediately following the heating step. In a similar field of endeavor Chao teaches generating thermal shock in a pre-processed wafer via rapid thermal process within a defined timeframe. Chao specifically teaches inducing this shock by rapidly heating the wafer to at least 350.degree.C. within a heating chamber, followed by a rapid transfer to a nearby cooling chamber where the wafer is cooled from at least 350.degree.C. to 70.degree.C. or lower within a short time period of about 30 seconds. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chao’s teachings of wherein a time between the application of the first temperature and the application of the second temperature is less than 2 minutes in the method of Mihai to generate an abrupt temperature gradient and resulting thermal stress sufficient to produce the desired thermal shock effect. Regarding claim 17, Mihai, as modified by Hoshino, Chang, Shiomi and Chao, teaches the limitations of claim 15 as mentioned above. Mihai does not explicitly teach “wherein heating the semiconductor wafer includes applying the first temperature to the semiconductor wafer for a time ranging from 5 minutes to 10 minutes, and wherein cooling the semiconductor wafer includes applying the second temperature to the semiconductor wafer for another time ranging from 1 minute to 5 minutes”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). It is noted that Mihai teaches placing the wafer on the heating table 12 and heating the wafer side 11a by the heater 14 to a temperature of 85 degree. C. or more followed by placing the cooling unit 22 to spray a cooling fluid onto the back surface 11b of the wafer 11 to create a sufficient temperature difference that induces breakage at the modified layer 17 via a thermal shock. While Mihai does not explicitly quantify the heating and cooling durations, the selection of appropriate heating and cooling times would have been a matter of routine optimization to achieve Mihai’s desired thermal shock sufficient to break the wafer at the modified layer. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize the duration of the heating and cooling process disclosed by Mihai by applying the first and second temperatures for a routine duration, such as claimed 5 to 10 minutes, and 1 minute to 5 minutes respectively, to achieve the expected result of improving throughput and shortening the time required for wafer division. Regarding claim 20, Mihai, as modified by Hoshino, Chang, Shiomi and Chao, teaches the limitations of claim 15 as mentioned above. Mihai does not explicitly teach “wherein the first and second stealth damage locations are vertically aligned”. In a similar field of endeavor Hoshino teaches wherein the first and second stealth damage locations are vertically aligned (see e.g., a laser beam applied to a wafer along a division line 14 so as to form a plurality of hole regions along the division line. Each hole region may be composed of a modified region and a crack. These modified regions along the division line are in a vertical column as shown in Figures 3 and 4). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Hoshino’s teachings of wherein the first and second stealth damage locations are vertically aligned in the method of Mihai in order to vertically dice the wafer. Claim 18 is rejected under 35 U.S. 103 as being unpatentable over Mihai (KR 20190092926 A) in view of Hoshino et al. (US 2020/0381303 A1; hereafter Hoshino) and Chang et al. (US 2022/0189856 A1; hereafter Chang), Shiomi (US 2019/0088548 A1) and Chao et al. (US 2003/0072350 A1; hereafter Chao) and further in view of Yodo et al. (JP 6851690 B2; hereafter Yodo). Regarding claim 18, Mihai, as modified by Hoshino, Chang, Shiomi and Chao, teaches the limitations of claim 15 as mentioned above. Mihai does not explicitly teach “wherein forming the first and second stealth damage locations includes using a laser power ranging from 0.2 Watts to 0.4 Watts”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). In a similar field of endeavor Yodo teaches wherein forming the first and second stealth damage locations includes using a laser power ranging from 0.2 Watts to 0.4 Watts (see e.g., In order to form the modified layer 19 the laser output power, wavelength, laser beam repetition frequency and chuck table moving speed maybe as per the wafer material. For a silicon, gallium arsenide, quartz or sapphire substrate, the laser output may be from 0.1W to 2W. For a gallium nitride substrate, the laser output power maybe from 0.02W to 0.2W. For a silicon carbide substrate, the laser output power maybe typically 0.1W). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Yodo’s teachings of wherein forming the first and second stealth damage locations includes using a laser power ranging from 0.2 Watts to 0.4 Watts in the method of Mihai in order to optimize the power of the laser according to the wafer material. Claim 19 is rejected under 35 U.S. 103 as being unpatentable over Mihai (KR 20190092926 A) in view of Hoshino et al. (US 2020/0381303 A1; hereafter Hoshino) and Chang et al. (US 2022/0189856 A1; hereafter Chang), Shiomi (US 2019/0088548 A1) and Chao et al. (US 2003/0072350 A1; hereafter Chao) and further in view of Morikazu et al. (US 2018/0161921 A1; hereafter Morikazu). Regarding claim 19, Mihai, as modified by Hoshino, Chang, Shiomi and Chao, teaches the limitations of claim 15 as mentioned above. Mihai does not explicitly teach “wherein a distance between the first and second stealth damage locations ranges from 25 microns to 80 microns”. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929). In a similar field of endeavor Morikazu teaches wherein a distance between the first and second stealth damage locations ranges from 25 microns to 80 microns (see e.g., The distance between adjacent rows of modified regions in the width direction of the at least one division line, i.e., between centres of the modified regions of the adjacent rows, may be in the range of 3 μm to 50 μm, preferably 5 μm to 40 μm and more preferably 8 μm to 30 μm. The number of rows may be in the range of 2 to 20, preferably 4 to 18, more preferably 5 to 15 and even more preferably 8 to 12, Para [0071], Figure 9) Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Morikazu’s teachings of wherein a distance between the first and second stealth damage locations ranges from 25 microns to 80 microns in the method of Mihai as such modification constitutes more routine experimentation to find optimal, workable ranges for thermal stress management. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAKEHA SEHAR whose telephone number is (571)272-4033. The examiner can normally be reached Monday-Thursday 7:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAKEHA SEHAR/Examiner, Art Unit 2893 /YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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Prosecution Timeline

Show 11 earlier events
Jul 17, 2025
Response after Non-Final Action
Jul 17, 2025
Response after Non-Final Action
Feb 09, 2026
Response after Non-Final Action
Apr 10, 2026
Request for Continued Examination
Apr 20, 2026
Response after Non-Final Action
Jun 09, 2026
Non-Final Rejection mailed — §103
Sep 09, 2026
Response Filed
Oct 13, 2026
Final Rejection mailed — §103 (current)

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