DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR
1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 03/03/2026 has been entered.
Claim Objections
Claim 1 is objected to because of the following informalities: “…wherein at least some of the
plurality layers…”. It should be read “…wherein at least some of the plurality of layers…”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1-7 and 9-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, it recites the limitation “…forming a plurality of layers of semiconductor material including an upper semiconductor layer… … a dielectric mask layer over the plurality of layers… … wherein at least some of the plurality layers form…” is not explained. The limitation is not clear if this refers to the “plurality of layers” mentioned with respect to “the dielectric mask” or “of semiconductor material” for that reason this limitation has multiple interpretations, in addition, it has an antecedent issue of “the plurality of layers” if this refers to “a plurality of layers of semiconductor material”. Therefore, it is indefinite. For the examination purpose and according to claim 1, the limitation “…forming a plurality of layers of semiconductor material including an upper semiconductor layer… … a dielectric mask layer over the plurality of layers… … wherein at least some of the plurality layers form” is interpreted as “…forming a plurality of layers of semiconductor material including an upper semiconductor layer… … a dielectric mask layer over the plurality of layers of semiconductor material … …wherein at least some of the plurality of layers of semiconductor material form…”.
Regarding claims 2-7, those are rejected under 35 U.S.C. 112 (b), because of their dependency status from claim 1.
Regarding claim 2, it recites the limitation “…wherein at least one of said plurality of layers form…” is not explained. The limitation is not clear if this refers to the “plurality of layers” mentioned with respect to “the dielectric mask” or “of semiconductor material” for that reason this limitation has multiple interpretations, in addition, it has an antecedent issue of “the plurality of layers” if this refers to “a plurality of layers of semiconductor material”. Therefore, it is indefinite. For the examination purpose and according to claim 1, the limitation “…wherein at least one of said plurality of layers form…” is interpreted as “…wherein at least one of said plurality of layers of semiconductor material forms…”.
Regarding claim 9, it recites the limitation “…wherein at least one of the layers of the plurality of layers forms…” is not explained. The limitation has an antecedent issue of “the plurality of layers”. Therefore, it is indefinite. For the examination purpose and according to claim 8, the limitation “…wherein at least one of the layers of the plurality of layers forms…” is interpreted as “…wherein at least one of the layers of the plurality of semiconductor layers forms…”.
Regarding claims 10-12, those are rejected under 35 U.S.C. 112 (b), because of their dependency status from claim 9.
Allowable Subject Matter
Claims 8 and 13-20 are allowed.
Claims 1 -7 would be allowable if rewritten or amended to overcome the rejection(s) under 35
U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 9 - 12 would be allowable if rewritten to overcome the rejection(s) under 35
U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The closest prior arts to the present invention are US 2019/0355868 A1 to Fimland, US
2017/0237234 A1 to Han, US 2019/0355703 A1 to Hikmet.
Fimland discloses a device, such as a light-emitting device, comprising: a plurality of group III-V semiconductor NWs grown on one side of a graphitic substrate, preferably through the holes of an optional hole-patterned mask on said graphitic substrate; a first distributed Bragg reflector or metal mirror positioned substantially parallel to said graphitic substrate and positioned on the opposite side of said graphitic substrate to said NWs; optionally a second distributed Bragg reflector or metal mirror in contact with the top of at least a portion of said NWs; and wherein said NWs comprise aim-type doped region and a p-type doped region and optionally an intrinsic region there between.
Han discloses structures and methods for forming highly uniform and high-porosity gallium-nitride layers with sub-100-nm pore sizes are described. Electrochemical etching of heavily-doped gallium nitride at low bias voltages in concentrated nitric acid is used to form the porous gallium nitride. The porous layers may be used in reflective structures for integrated optical devices such as VCSELs and LEDs.
Hikmet discloses a lighting device comprising a plurality of light emitting diodes, LEDs. The plurality of LEDs is disposed on a substrate for emitting visible light from at least one first light output surface in an outgoing light direction. The lighting device includes also at least one ultra violet light emitting diode, UV LED, for emitting UV light from a second light output surface in the outgoing light direction. A phosphor layer is disposed on at least the plurality of LEDs such that the LEDs are covered by the phosphor layer. The second light output surface for emitting UV light from the at least one UV LED is mounted at a higher level than the at least first light output surface relative to the substrate in the outgoing light direction. The present invention also relates to a method for manufacturing the lighting device.
Re: Independent Claim 1 (and dependent claim(s) 2-7), there is no teaching or suggestion in the prior art of record to provide:
“each of the LED structures comprising an active region that does not extend above an upper surface of the dielectric mask layer”.
Re: Independent Claim 8 (and dependent claim(s) 9-20), there is no teaching or suggestion in the prior art of record to provide:
“each of the LED structures comprising an active region that does not extend above an upper surface of the dielectric layer”.
Missing elements in the closest art gives rise to the innovation in the current invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA MILENA RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898