DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-7, 10, 14-18, & 21 are pending and claims 11-13 are withdrawn.
Election/Restrictions
As put forth in the restriction requirement mailed on 2/26/24:
This application contains a group of inventions which are not so linked as to form a single general inventive concept under PCT Rule 13.1.
In accordance with 37 CFR 1.499, applicant was required to elect a single invention to which the claims must be restricted.
Group I, claim(s) 1-10 & 16-20, drawn to a method of using the stencil.
Group II, claim(s) 11-13, drawn to the stencil and an apparatus comprising the stencil.
Group III, claim(s) 14-15, drawn to a method of manufacturing the stencil.
Applicant elected Group I, directed towards a method of using a stencil in a reply filed on 4/8/24.
Subsequently applicant has added claim 21 (which is also grouped with Group I) and amended claim 14 (which is now properly grouped with Group I because of claim 21).
Claims 1-7, 10-18, & 21 are currently pending.
Thus, the grouping of claims is:
Group I, claim(s) 1-7, 10, 14-18, & 21, drawn to a method of making and using the stencil.
Group II, claim(s) 11-13, drawn to the stencil and an apparatus comprising the stencil.
The groups of inventions listed above do not relate to a single general inventive concept under PCT Rule 13.1 because, under PCT Rule 13.2, they lack the same or corresponding special technical features for the following reasons:
As put forth below, claims 1, 11, & 21 are anticipated by, or obvious in view of, Grantham et al. (US PG Pub 2004/0086639) and thus the technical features of claims 1, 11, & 21 are not a special technical feature and the groups lack unity of invention.
Therefore, claims 1-7, 10, 14-18, & 21 are pending and claims 11-13 are withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, & 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Grantham et al. (US PG Pub 2004/0086639; hereafter ‘639).
Claim 1: ‘639 is directed towards a method for collimating a beam of material being deposited on a substrate at a deposition area of the substrate (see title & abstract), the method comprising:
masking the substrate with a stencil mask located at a mask distance from the substrate (see Figs. 6A & 6B and ¶s 41, 42, & 61-65), the mask distance being the distance between a top face of the substrate and an outer face of the mask facing the substrate (see Figs. 6A & 6B); and
projecting the beam from a source cell located at a source distance from the stencil mask, the source distance being a distance between the source cell and an outer face of the stencil mask facing the source well (see Figs. 6A & 6B and ¶s 41, 42, & 61-65), wherein the stencil mask comprises:
a first mask layer defining a first slit, the first mask layer formed on a first surface of a first semiconductor wafer, wherein the first semiconductor wafer defines a first void situated at the first slit and extending through the first semiconductor wafer (see #s 22 & 23, Figs. 6A & 6B and ¶s 41, 42, & 61-65; note that the openings can be slots and Merriam-Webster defines slots as slit; see also annotated Fig. 6 below),
a second mask layer defining a second slit, the second mask layer formed on a first surface of a second semiconductor wafer, wherein the second semiconductor wafer defines a second void, the second void situated at the second slit and extending through the second semiconductor wafer (see #s 22 & 23, Figs. 6A & 6B and ¶s 41, 42, & 61-65; note that the openings can be slots and Merriam-Webster defines slots as slit; see also annotated Fig. 6 below),
wherein a second surface of the first semiconductor wafer, opposite the first surface of the first semiconductor wafer contacts a second surface of the second semiconductor wafer, opposite the first surface of the second semiconductor wafer so that the first slit and the second slit are aligned, the first semiconductor wafer and the second semiconductor wafer defining a mask layer separation distance between the first mask layer and the second mask layer (see #s 22 & 23, Figs. 6A & 6B and ¶s 41, 42, & 61-65; note that the openings can be slots and Merriam-Webster defines slots as slit; see also annotated Fig. 6 below).
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Claim 2: The first opening angle is a function of the source distance and a width of the slit in a first of the two mask layers, and the slit in the second of the two mask layers reduces the opening angle to a second opening angle which is a function of the layer separation distance and the width of the slit in the second of the two mask layers, wherein the deposition area is a function of the second opening angle (note dotted lines in Fig. 6B depicting the beam collimation with deposition area).
Claim 10: The source cell comprises a deposition material and the beam is a beam of the deposition material, wherein the deposition material is deposited at the deposition area of the substrate (Figs. 6A & 6B and ¶s 41, 42, & 61-65).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-7, 10, 14-18. & 21 are rejected under 35 U.S.C. 103 as being unpatentable over ‘639.
Claim 3: The spacing between masks is chosen to eliminate diagonal passage through periodic set of apertures (¶ 27) and the spacing can be 1 mm (¶ 70).
Although the taught 1 mm does not fall within the claimed range of between 100 µm and 1 mm, it is mathematically close. Therefore it would have been obvious to one of ordinary skill in the art at the time of invention to have incorporated a value within the claimed range since in the case where the claimed ranges “so mathematically close that the difference between the claimed ranges was virtually negligible absent any showing of unexpected results or criticality”. See MPEP §2144.04(I).
Additionally, ‘639 teaches that spacing is chosen to eliminate diagonal passage through periodic sets of apertures. Thus, the spacing is a result effective variable based on the desired control of passage of deposition material between diagonal apertures and it is obvious to optimize the spacing to obtain the amount of passage between diagonal apertures. "Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." See MPEP 2144.05(II)(B).
Claim 4: ‘639 does not teach a source width.
However, source width is a result effective variable based on the desired width of coating and it is obvious to optimize source width to obtain the desired deposition width.
"Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." See MPEP 2144.05(II)(B).
Additionally, changes in shape and size are prima facie obvious without a showing of unexpected results. MPEP § 2144.04 (IV)(A) & (B).
Claim 5: ‘639 does not teach that the mask distance is between 1 and 10 µm.
‘639 does teach that width of deposit is dependent on mask distance (see ¶ 53).
Thus, the mask distance is a result effective variable based on the desired width of deposit and it is obvious to optimize the mask distance to obtain the desired width of the deposit. "Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." See MPEP 2144.05(II)(B).
Claim 6: ‘639 does not teach a source distance.
However, changes in size is prima facie obvious without a showing of unexpected results. MPEP § 2144.04 (IV)(A) & (B).
Claim 7: The mask layers are 25µm thick (¶ 51).
However, changes in size is prima facie obvious without a showing of unexpected results. MPEP § 2144.04 (IV)(A) & (B).
Claims 14 & 21: ‘639 is directed towards a method of collimating a beam of material (see title, abstract, Figs. 6A & 6B and ¶s 41, 42, & 61-65), comprising:
forming a first mask layer on a first semiconductor wafer (a glass layer is formed on a first semiconductor wafer, Figs. 6A & 6B and ¶s 41, 42, & 61-65);
patterning said first mask layer to form a first slit (Figs. 6A & 6B and ¶s 41, 42, & 61-65);
forming a second mask layer on a second semiconductor wafer (a second glass layer is formed on a second semiconductor wafer; Figs. 6A & 6B and ¶s 41, 42, & 61-65);
patterning said second mask layer to form a second slit (Figs. 6A & 6B and ¶s 41, 42, & 61-65);
affixing the first semiconductor wafer and the second semiconductor wafer together to form a stencil mask, such that the first mask layer and the second mask layer are separated by a mask layer separation distance corresponding to a combined thickness of the first semiconductor wafer and the second semiconductor wafer and so that the first slit and the second slit are aligned (see #s 22 & 23, Figs. 6A & 6B and ¶s 41, 42, & 61-65; note that the openings can be slots and Merriam-Webster defines slots as slit; see also annotated Fig. 6 below);
situating the stencil mask at a mask distance from a substrate, the mask distance being a distance between a to face of the substrate and an outer face of the stencil mask facing the substrate (see Fig. 6B); and
projecting a beam from a source cell located at a source distance from the stencil mask, the source distance being a distance between the source cell and an outer face of the stencil mask facing the source cell (see #s 22 & 23, Figs. 6A & 6B and ¶s 41, 42, & 61-65; note that the openings can be slots and Merriam-Webster defines slots as slit; see also annotated Fig. 6 below).
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‘639 does not teach growing the glass layer on the semiconductor wafers.
However, it is well known in the art that a glass layer can be formed by growing glass on the semiconductor surface.
It would have been obvious to one of ordinary skill in the art at the time of filing to form the glass layers of ‘639 by growing them because it is an well-known art recognized method of forming glass layers on semiconductor and would have predictably provided the desired layers.
‘639 does not teach the specific order of the claimed process.
It would have been obvious to one of ordinary skill in the art at the time of filing to perform the process of ‘639 in the claimed order of steps because selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. MPEP §2144.04(IV)(C).
Claim 15: The first mask layer and the second mask layer are patterned using a lithographic technique (the glass is patterned by selective removal through the Si openings, ¶ 61; ‘639 teaches that patterning can be performed by lithography, ¶ 3).
Claim 16: The spacing between masks is chosen to eliminate diagonal passage through periodic set of apertures (¶ 27) and the spacing can be 1 mm (¶ 70).
Although the taught 1 mm does not fall within the claimed range of between 100 µm and 1 mm, it is mathematically close. Therefore it would have been obvious to one of ordinary skill in the art at the time of invention to have incorporated a value within the claimed range since in the case where the claimed ranges “so mathematically close that the difference between the claimed ranges was virtually negligible absent any showing of unexpected results or criticality”. See MPEP §2144.04(I).
Additionally, ‘639 teaches that spacing is chosen to eliminate diagonal passage through periodic sets of apertures. Thus, the spacing is a result effective variable based on the desired control of passage of deposition material between diagonal apertures and it is obvious to optimize the spacing to obtain the amount of passage between diagonal apertures. "Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." See MPEP 2144.05(II)(B).
Claim 17: ‘639 does not teach a source width.
However, source width is a result effective variable based on the desired width of coating and it is obvious to optimize source width to obtain the desired deposition width.
"Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." See MPEP 2144.05(II)(B).
Additionally, changes in shape and size are prima facie obvious without a showing of unexpected results. MPEP § 2144.04 (IV)(A) & (B).
Claim 18: ‘639 does not teach that the mask distance is between 1 and 10 µm.
‘639 does teach that width of deposit is dependent on mask distance (see ¶ 53).
Thus, the mask distance is a result effective variable based on the desired width of deposit and it is obvious to optimize the mask distance to obtain the desired width of the deposit. "Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." See MPEP 2144.05(II)(B).
Response to Arguments
Applicant's arguments filed 9/23/25 have been fully considered but they are not persuasive.
In regards to applicant’s argument that ‘639 “fails to show any semiconductor wafers that are in contact and thus fails to disclose at least that “a second surface of the first semiconductor wafer, opposite the first surface of the first semiconductor wafer contacts a second surface of the second semiconductor wafer”, as recited in claim 1”; the Office does not find this argument convincing because the silicon wafers (semiconductor wafers) of ‘639 are in indirect contact and applicant does not claim that the semiconductor wafers are in direct contact without intervening layers.
In regards to applicant’s argument that ‘639 fails to teach affixing the first semiconductor wafer and the second semiconductor wafer to each because they are bonded to each other by a glass; the Office does not find this argument convincing because the three layers are bonded together and thus it is apparent that the first and second semiconductor wafers are affixed to each other by way a binding material (the glass sheet).
In response to the Official Notice applicant has not stated why the noticed fact is not considered to be common knowledge or well known in the art and thus the noticed fact is admitted prior art because applicant has not adequately traversed the noticed fact.
In regards to applicant’s argument that the claims do not recite “form glass on a semiconductor surface”; applicant is advised that the teaching of forming a glass layer on a semiconductor layer reads on the claimed growing a mask layer on a semiconductor wafer as put forth above.
In regards to applicant’s argument that “by growing glass on a semiconductor surface, it becomes impossible to affix the semiconductor wafers to each other as claimed”; the Office does not find this argument convincing because ‘639 teaches affixing the semiconductor wafers to each other by the use of a glass as a binder.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES M MELLOTT whose telephone number is (571)270-3593. The examiner can normally be reached 8:30AM-4:30PM CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Curtis Mayes can be reached at 571-272-1234. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/James M Mellott/ Primary Examiner, Art Unit 1759
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