The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-13, 17, 23-24, 32 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2004/0109118).
Regarding claim 9, Kim et al. teach in figures 1-3 and related text a display panel, comprising:
a first metal layer 1a comprising at least one first metal line, wherein the first metal line is a gate line; and
a second metal layer 3a covering the first metal layer and comprising at least one second metal line overlapping the at least one first metal line, wherein the second metal line is a data line overlapping the gate line; and
an insulating layer 4 disposed between the first metal layer and the second metal layer;
wherein the gate line 1a comprises a planarization part not overlapping the data line and an overlapping part overlapping the data line, and
wherein in a cross-sectional view (see figure 3) of a structure composed of the gate line, the insulating layer, and the data line,
a thickness of the overlapping part (located in the middle of element 1a) is less than a thickness of the planarization part (located in the edge of element 1a as clearly depicted in figure 2), an upper surface of the overlapping part is connected to a side surface of the planarization part, the upper surface of the overlapping part and the side surface of the planarization part together define a groove, the upper surface of the overlapping part serves as a bottom surface of the groove, the side surface of the planarization part serves as an inner sidewall of the groove, and a portion of the data line overlapping the overlapping part is disposed directly above the groove
Kim et al. do not explicitly state that in a cross-sectional view, as depicted in figure 3 of a structure composed of the gate line, the insulating layer, and the data line, groove 8 is provided in the gate line.
Kim et al. teach in figure 2 that in the structure composed of the gate line, the insulating layer, and the data line, groove 8 is provided in the gate line.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to provide in a cross-sectional view a groove in the gate line in Kim et al.’s devices, in order to reduce the parasitic capacitance of the device.
Regarding claims 10, 12, Kim et al. teach substantially the entire claimed structure, as applied to claim 9 above, including having an area of a cross-section of the overlapping part is equal to an area of a cross- section of the planarization part, but does not explicitly state that a distance between an edge of the overlapping part and an edge of the data line is greater than or equal to 3 microns in an extension direction of the gate line.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form an area of a cross-section of the overlapping part is equal to an area of a cross- section of the planarization part, and wherein a distance between an edge of the overlapping part and an edge of the data line is greater than or equal to 3 microns in an extension direction of the gate line, in prior art’s device, in order to adjust the capacitor characteristics in the device.
Regarding claim 11, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a ratio between the thickness of the planarization part and the thickness of the overlapping part to range from 1.5 to 2 in prior art’s device, in order to adjust the capacitor characteristics in the device.
Regarding claim 13, Kim et al. teach that the first metal layer comprises a plurality of gate lines parallel to each other; the second metal layer comprises a plurality of data lines parallel to each other; and the gate lines are perpendicular to the data lines; wherein the display panel further comprises an insulating layer covering the first metal layer.
Regarding claim 17, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first metal layer and the second metal layer comprise one or at least two of Mo, Al, Cu, or W in prior art’s device, in order to improve the conductivity of the device.
Regarding claims 23 and 24, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a width of the overlapping part is greater than a width of the planarization part along an extension direction of the second metal line and wherein a length of the overlapping part along an extension direction of the first metal line is greater than a width of the second metal line, in prior art’s device, in order to obtain the advantages of the disclosed display panel by building the structure, respectively.
Regarding claim 32, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the thickness of the overlapping part being 50% to 80% of the thickness of the planarization part in prior art’s device, in order to optimize the value of the parasitic capacitance of the device.
Regarding claim 37, Kim et al. teach in figure 3 that in the cross-sectional view of a structure composed of the gate line, the insulating layer, and the data line, the insulating layer 4 comprises a recessed portion but does not teach that said recessed portion is aligned with the groove, and the overlapping portion is disposed within the recessed portion.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form said recessed portion aligned with the groove and the overlapping portion is disposed within the recessed portion in prior art’s device, in order to optimize the value of the parasitic capacitance of the device.
Claims 26-31 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2004/0109118) in view of Choi et al. (6,320,221), Park et al. (2017/0077208), Li et al. (9,897,863) and Sun et al. (2016/0043116).
Regarding claim 26, Kim et al. teach in figures 1-3 and related text a display panel, comprising:
a first metal layer 1a comprising at least one first metal line, wherein the first metal line is a gate line; and
a second metal layer 3a covering the first metal layer and comprising at least one second metal line overlapping the at least one first metal line, wherein the second metal line is a data line overlapping the gate line; and
an insulating layer 4 disposed between the first metal layer and the second metal layer;
wherein the gate line comprises a planarization part not overlapping the data line and an overlapping part overlapping the data line, and
wherein in a cross-sectional view (see figure 3) of a structure composed of the gate line, the insulating layer, and the data line,
a thickness of the overlapping part (located in the middle of element 1a) is less than a thickness of the planarization part (located in the edge of element 1a as clearly depicted in figure 2), an upper surface of the overlapping part is connected to a side surface of the planarization part, the upper surface of the overlapping part and the side surface of the planarization part together define a groove, the upper surface of the overlapping part serves as a bottom surface of the groove, the side surface of the planarization part serves as an inner sidewall of the groove, and a portion of the data line overlapping the overlapping part is disposed directly above the groove.
Kim et al. do not explicitly state that a part of the data line is disposed in the groove and do not teach that a groove is provided in the data line.
Choi et al. teach in figure 3 and related text that a part of the data line (extension 114a) is disposed in the groove T in gate line 12.
Li et al. teach in related text (see e.g. title and abstract) that a groove can be formed in either the data line or the gate line.
Park et al. teach in figure 4B and related text that a groove 40 is formed in data line DLb.
Sun et al. teach in paragraph [015] that the data lines and the gate lines have embedded grooves.
Park et al., Choi et al., Kim et al., Sun et al. and Li et al. are analogous art because they are directed to semiconductor devices comprising metal lines and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to dispose part of the data line in the groove, as taught by Choi et al. and to form a groove in the data line, as taught by Sun et al. and Li et al., in prior art’s devices, in order to reduce the parasitic capacitance of the device.
Regarding claims 27 and 29, prior art teaches substantially the entire claimed structure, as applied to claim 26 above, including having an area of a cross-section of the overlapping part is equal to an area of a cross- section of the planarization part, but does not explicitly state that a distance between an edge of the overlapping part and an edge of the data line is greater than or equal to 3 microns in an extension direction of the gate line.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form an area of a cross-section of the overlapping part is equal to an area of a cross- section of the planarization part, and wherein a distance between an edge of the overlapping part and an edge of the data line is greater than or equal to 3 microns in an extension direction of the gate line, in prior art’s device, in order to adjust the capacitor characteristics in the device.
Regarding claim 28, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a ratio between the thickness of the planarization part and the thickness of the overlapping part to range from 1.5 to 2 in prior art’s device, in order to adjust the capacitor characteristics in the device.
Regarding claims 30-32, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a width of the overlapping part is greater than a width of the planarization part in an extension direction of the gate line, and a length of the overlapping part in an extension direction of the data line is greater than a width of the gate line and to form the thickness of the overlapping part being 50% to 80% of the thickness of the planarization part in prior art’s device, in order to optimize the value of the parasitic capacitance of the device.
Regarding claim 38, Kim et al. teach in figure 3 that in the cross-sectional view of a structure composed of the gate line, the insulating layer, and the data line, the insulating layer 4 comprises a recessed portion but does not teach that said recessed portion is aligned with the groove, and the overlapping portion is disposed within the recessed portion.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form said recessed portion aligned with the groove and the overlapping portion is disposed within the recessed portion in prior art’s device, in order to optimize the value of the parasitic capacitance of the device.
Response to Arguments
1. Applicants argue that Kim does not teach a groove.
1. Kim recites the term “groove” 38 times. In one instant Kim states a predetermined groove is formed on the gate bus lines 1a and 1b at a boundary area where the gate bus lines 1a and 1b overlap the data bus lines 3a and 3b”.
2. A claimed limitation wherein a bottom surface of the insulating layer in the overlapping part is located at higher elevation then an upper surface of the gate line located outside the overlapping part, will overcome the rejectoin as recited in previous office action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
7/7/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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