Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 (and dependent claims 10-11 dependent therefrom) is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, “a first semiconductor layer disposed on and directly contacting the first semiconductor layer” in lines 13-14 is unclear. For the sake of compact prosecution, claim 9 is interpreted in the instant Office action as follows: “a first semiconductor layer disposed on and directly contacting the first semiconductor layer” in lines 13-14 is equivalent to “a first semiconductor layer disposed on and directly contacting the gate insulating layer”. This interpretation is based at least upon Figs. 2, 3, and 7 of Applicant’s originally filed disclosure; and upon Applicant's remarks filed 9/27/2026: pg. 2. This interpretation is to be confirmed by applicant in next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lv (US 20170162707 A1).
Regarding claim 1, Lv discloses a semiconductor device (Fig. 2), comprising:
a substrate (1);
a first gate (2) disposed on the substrate;
a gate insulating layer (3) disposed on the first gate and covering the first gate;
a first active component (collection of 4 with 6 and 7; [0034]: “thin-film transistor”) disposed on the gate insulating layer, wherein the first active component has a channel region (46, which is a portion of sub-layer 41) and doped regions (sub-layer 43, directly on 41; [0035]: “lightly-doped amorphous silicon layers”) located respectively on opposite sides of the channel region;
a first source (6; [0035]: “source electrode”) disposed on the first active component and electrically connected (series “connected” is illustrated) to one of the doped regions of the first active component; and
a first drain (7; [0035]: “drain electrode”) disposed on the first active component and electrically connected (series “connected” is illustrated) to another one of the doped regions of the first active component;
wherein the first active component comprises:
a first semiconductor layer (a layer composed of sub-layers 41 and 43; [0035]: “amorphous silicon”) disposed on and directly contacting the gate insulating layer (sub-layer 41 is directly contacting 3); and
a contact layer stack (44/43/45/42) disposed on the first semiconductor layer and disposed in the doped regions;
wherein the contact layer stack comprises:
a first doped layer (a layer composed of sub-layers 43 and 44, directly on 43; [0035]: “lightly-doped amorphous silicon layers”) disposed on and directly contacting the first semiconductor layer (sub-layer 44 is directly contacting sub-layer 43);
a second semiconductor layer (45) disposed on and directly contacting the first doped layer (45 is “directly contacting” 43), wherein the second semiconductor layer is a single undoped amorphous silicon layer (only one sub-layer is relied upon, thus “single layer”; [0038]: “pure amorphous silicon”); and
a second doped layer (42; [0038]: “heavily-doped amorphous silicon layer”) disposed on and directly contacting the second semiconductor layer (42 is “directly contacting” 45); and
wherein the first source and the first drain are disposed on and are in direct contact with the second doped layer, respectively (6/7 are “directly contacting” 42); and
wherein an entirety of orthographic projections of the first semiconductor layer, the first doped layer, the second semiconductor layer, and the second doped layer on the substrate are located within an orthographic projection (See dashed reference lines in annotated figure) of the first gate on the substrate.
Illustrated below is a marked and annotated figure of Fig. 2 of Lv.
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Regarding claim 2, Lv discloses the semiconductor device according to claim 1 (Fig. 2), wherein the first semiconductor layer is an amorphous silicon layer ([0035]: “amorphous silicon layer”).
Regarding claim 3, Lv discloses the semiconductor device according to claim 1 (Fig. 2), wherein the first doped layer is an N-type doped amorphous silicon layer (sub-layer 43 reads on this limitation; [0035]: “N-type lightly-doped amorphous silicon layers 43”).
Regarding claim 5, Lv discloses the semiconductor device according to claim 1 (Fig. 2), wherein the second doped layer is an N-type doped amorphous silicon layer ([0038]: “N-type heavily-doped amorphous silicon layer 42”).
Regarding independent claim 9 as noted in the 112(b) rejection, Lv discloses a method of manufacturing a semiconductor device (Fig. 2), comprising:
forming a first gate (2), wherein a metal layer is deposited ([0039]: “materials that comprise one of molybdenum (Mo)…”) on a substrate (1) and patterned to form the first gate (at least some kind of patterning is required to produce a final shape, which may reasonably include direct patterning or subtractive patterning; [0034]: “formed on the base plate”);
forming a gate insulating layer (3) on the first gate ([0034]: “set on and covering the gate electrode”), wherein the gate insulating layer covers the first gate (3 is formed directly on 2, therefore completely and directly covering);
forming a first active component (collection of 4 with 6 and 7; [0034]: “thin-film transistor”) on the gate insulating layer ([0034]: “formed on the gate insulation layer”), wherein the first active component has a channel region (46, which is a portion of sub-layer 41) and doped regions (sub-layer 43, directly on 41; [0035]: “lightly-doped amorphous silicon layers”) located respectively on opposite sides of the channel region; and
forming a first source (6; [0035]: “source electrode”) and a first drain (7; [0035]: “drain electrode”), wherein a metal layer ([0039]: “materials that comprise one of molybdenum (Mo)…”) is deposited on ([0034]: “formed on”) the first active component and patterned (at least some kind of patterning is required to produce a final shape, which may reasonably include direct patterning or subtractive patterning; [0034]: “formed on the base plate”) to form the first source and the first drain respectively opposite to the doped regions, and the first source and the first drain are respectively electrically connected (series “connected” is illustrated) to the doped regions of the first active component,
wherein the first active component comprises:
a first semiconductor layer (a layer composed of sub-layers 41 and 43; [0035]: “amorphous silicon”) disposed on and directly contacting the gate insulating layer; and
a contact layer stack (44/43/45/42) disposed on the first semiconductor layer and disposed in the doped regions;
wherein the contact layer stack comprises:
a first doped layer (a layer composed of sub-layers 43 and 44, directly on 43; [0035]: “lightly-doped amorphous silicon layers”) disposed on and directly contacting the first semiconductor layer (sub-layer 44 is directly contacting sub-layer 43);
a second semiconductor layer (45) disposed on and directly contacting the first doped layer (45 is “directly contacting” 43), wherein the second semiconductor layer is a single undoped amorphous silicon layer (only one sub-layer is relied upon, thus “single layer”; [0038]: “pure amorphous silicon”); and
a second doped layer (42; [0038]: “heavily-doped amorphous silicon layer”) disposed on and directly contacting the second semiconductor layer (42 is “directly contacting” 45);
wherein the first source and the first drain are formed on and are in direct contact with the second doped layer, respectively (6/7 are “directly contacting” 42); and
wherein an entirety of orthographic projections of the first semiconductor layer, the first doped layer, the second semiconductor layer, and the second doped layer on the substrate are located within an orthographic projection (See dashed reference lines in annotated figure) of the first gate on the substrate.
Regarding claim 10, Lv discloses the method according to claim 9 (Fig. 2), wherein the forming of the first active component comprises:
forming the first semiconductor layer, wherein an amorphous layer ([0035]: “amorphous silicon layer”) is deposited on the gate insulating layer by chemical vapor deposition ([0038]: “chemical vapor deposition”) and the amorphous layer is patterned ([0038]: “etching is applied”) to form the first semiconductor layer opposite to the first gate;
forming the first doped layer on the doped regions of the first semiconductor layer by chemical vapor deposition ([0038]: “chemical vapor deposition”);
forming the second semiconductor layer on the first doped layer by chemical vapor deposition ([0038]: “chemical vapor deposition”);
and forming the second doped layer on the second semiconductor layer by chemical vapor deposition ([0038]: “chemical vapor deposition”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-3 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ohta (US 20210296505 A1) in view of Yamazaki (US 20090140438 A1).
Regarding claim 1, Ohta discloses a semiconductor device (Fig. 1), comprising:
a substrate (1; [0070]: “substrate”);
a first gate (2; [0070]: “gate electrode”) disposed on the substrate;
a gate insulating layer (3; [0070]: “gate insulating layer”) disposed on the first gate and covering the first gate (directly “covering”);
a first active component (collection of 4 with Cs and Cd; [0071]: “an active layer”) disposed on the gate insulating layer, wherein the first active component has a channel region (Rc; [0072]: “channel region”) and doped regions (Rs, Rd; [0072]: “first region…second region”; [0108]: “may contain an n type impurity at a relatively low concentration”) located respectively on opposite sides of the channel region;
a first source (a composite of sub-layers 8s, 71, 73(1), and 72(1); [0070]: “source electrode”) disposed on the first active component and electrically connected to one of the doped regions of the first active component ([0070]: “electrically connected”); and
a first drain (a composite of sub-layers 8d, 71, 73(1), and 72(1); [0070]: “drain electrode”) disposed on the first active component and electrically connected to another one of the doped regions of the first active component ([0070]: “electrically connected”);
wherein the first active component comprises:
a first semiconductor layer (a layer composed of sub-layers 4, 74, and 72(3); [0078]: “amorphous silicon layer”) disposed on and directly contacting the gate insulating layer (sub-layer 4 is “directly contacting” 3); and
a contact layer stack (a stack composed of 73(3), 72(2), 73(2) directly stacked sub-layers) disposed on the first semiconductor layer and disposed in the doped regions (directly “on” and “in”);
wherein the contact layer stack comprises:
a first doped layer (73(3); [0078]: “n type impurity”) disposed on and directly contacting the first semiconductor layer (73(3) is “directly contacting” 72(3));
a second semiconductor layer (72(2)) disposed on and directly contacting the first doped layer, wherein the second semiconductor layer is a single undoped amorphous silicon layer (only one sub-layer is relied upon, thus “single layer”; [0078]: “an intrinsic a-Si layer that substantially contains no n type impurity”); and
a second doped layer (73(2); [0078]: “n type impurity”) disposed on and directly contacting the second semiconductor layer (73(2) is “directly contacting” 72(2)); and
wherein the first source and the first drain are disposed on and are in direct contact with the second doped layer, respectively (sub-layer 72(1) is “directly contacting” 73(2)); and
wherein an entirety of orthographic projections of the first semiconductor layer, the first doped layer, the second semiconductor layer, and the second doped layer on the substrate (See annotated figure) are located within an orthographic projection of the first gate on the substrate (See annotated figure. Partially within.).
Illustrated below is a marked and annotated figure of Fig. 1 of Ohta.
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Ohta fails to teach “an entirety of orthographic projections of the first semiconductor layer, the first doped layer, the second semiconductor layer, and the second doped layer on the substrate are located within an orthographic projection of the first gate on the substrate” because Ohta teaches the structures of the first active component have a shape where only a portion of orthographic projections of these structures of the first active component on the substrate is within an orthographic projection of the first gate on the substrate (as cited above).
Yamazaki teaches an entirety of orthographic projections (See annotated figure demarking the projection) of all structures of the first active component (the collection of 87, 88, 92a, 92b, 92c) on the substrate (50) are located within an orthographic projection (See annotated figure demarking the projection) of the first gate (51) on the substrate. Modifying the shape of the structures of the first active component (of Ohta) by incorporating the patterning method and resultant shape of Yamazaki when patterning the structures of the first active component of Ohta (See patterning step of Ohta: Fig. 3(e)), would arrive at the claimed orthographic projections configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Yamazaki teaches incorporating this patterning method and resultant shape is an improvement over a patterning method and resultant shape substantially similar to the shape disclosed by Ohta (Yamazaki: Fig. 1D is substantially the same shape as Ohta: Fig. 1). Yamazaki provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the claimed patterning method and resultant shape of the structures of the first active component in that it would reduce manufacturing complexity by reducing the number of photomasks required for patterning ([0265]: “a display device can be formed in which a multi-tone mask is used to reduce the number of masks”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed orthographic projections configuration because it would reduce manufacturing complexity. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 18B of Yamazaki.
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Regarding claim 2, Ohta in view of Yamazaki discloses the semiconductor device according to claim 1 (Ohta: Fig. 1), wherein the first semiconductor layer is an amorphous silicon layer ([0078]: “amorphous silicon layer”).
Regarding claim 3, Ohta in view of Yamazaki discloses the semiconductor device according to claim 1 (Ohta: Fig. 1), wherein the first doped layer is an N-type doped amorphous silicon layer ([0078]: “amorphous silicon layer…n type impurity”).
Regarding claim 5, Ohta in view of Yamazaki discloses the semiconductor device according to claim 1 (Ohta: Fig. 1), wherein the second doped layer is an N-type doped amorphous silicon layer ([0078]: “amorphous silicon layer…n type impurity”).
Regarding claim 6, Ohta in view of Yamazaki discloses the semiconductor device according to claim 1 (Ohta: Fig. 1), wherein a thickness of the first doped layer ranges from 5 nm to 10 nm ([0088]: “greater than 0 nm but not greater than 20 nm”).
Regarding claim 7, Ohta in view of Yamazaki discloses the semiconductor device according to claim 1 (Ohta: Fig. 1), wherein a thickness of the second semiconductor layer ranges from 10 nm to 12 nm (the prior art discloses ranges overlapping the claimed ranges; [0088]: “73(n) may be e.g. greater than 0 nm but not greater than 20 nm…72(n) may be equal to or greater than the thickness of the third a-Si layer 73(n)”).
Regarding claim 8, Ohta in view of Yamazaki discloses the semiconductor device according to claim 1 (Ohta: Fig. 1), wherein a thickness of the second doped layer ranges from 5 nm to 10 nm ([0088]: “greater than 0 nm but not greater than 20 nm”).
Regarding independent claim 9 as noted in the 112(b) rejection, Ohta discloses a method of manufacturing a semiconductor device (Fig. 1), comprising:
forming a first gate (2; [0070]: “gate electrode”), wherein a metal layer is deposited ([0105]: “sputtering…metal film”) on a substrate (1) and patterned ([0105]: “patterned”) to form the first gate;
forming a gate insulating layer (3; [0070]: “gate insulating layer”) on the first gate, wherein the gate insulating layer covers the first gate (directly “covers”);
forming a first active component (collection of 4 with Cs and Cd; [0071]: “an active layer”) on the gate insulating layer, wherein the first active component has a channel region (Rc; [0072]: “channel region”) and doped regions (Rs, Rd; [0072]: “first region…second region”; [0108]: “may contain an n type impurity at a relatively low concentration”) located respectively on opposite sides of the channel region; and
forming a first source (a composite of sub-layers 8s, 71, 73(1), and 72(1); [0070]: “source electrode”) and a first drain (a composite of sub-layers 8d, 71, 73(1), and 72(1); [0070]: “drain electrode”), wherein a metal layer ([0117]: “a material similar to…the gate”) is deposited ([0117]: “by a method similar to…the gate”) on the first active component and patterned ([0117]: “by a method similar to…the gate”) to form the first source and the first drain respectively opposite to the doped regions, and the first source and the first drain are respectively electrically connected ([0070]: “source electrode…drain electrode…electrically connected”) to the doped regions of the first active component,
wherein the first active component comprises:
a first semiconductor layer (a layer composed of sub-layers 4, 74, and 72(3); [0078]: “amorphous silicon layer”) disposed on and directly contacting the gate insulating layer (sub-layer 4 is “directly contacting” 3); and
a contact layer stack (a stack composed of 73(3), 72(2), 73(2) directly stacked sub-layers) disposed on the first semiconductor layer and disposed in the doped regions (directly “on” and “in”);
wherein the contact layer stack comprises:
a first doped layer (73(3); [0078]: “n type impurity”) disposed on and directly contacting the first semiconductor layer (73(3) is “directly contacting” 72(3));
a second semiconductor layer (72(2)) disposed on and directly contacting the first doped layer, wherein the second semiconductor layer is a single undoped amorphous silicon layer (only one sub-layer is relied upon, thus “single layer”; [0078]: “an intrinsic a-Si layer that substantially contains no n type impurity”); and
a second doped layer (73(2); [0078]: “n type impurity”) disposed on and directly contacting the second semiconductor layer (73(2) is “directly contacting” 72(2));
wherein the first source and the first drain are formed on and are in direct contact with the second doped layer, respectively (sub-layer 72(1) is “directly contacting” 73(2)); and
wherein an entirety of orthographic projections of the first semiconductor layer, the first doped layer, the second semiconductor layer, and the second doped layer on the substrate (See annotated figure) are located within an orthographic projection of the first gate on the substrate (See annotated figure).
Ohta fails to teach “an entirety of orthographic projections of the first semiconductor layer, the first doped layer, the second semiconductor layer, and the second doped layer on the substrate are located within an orthographic projection of the first gate on the substrate” because Ohta teaches the method of forming the structures of the first active component forms a shape where only a portion of orthographic projections of the structures of the first active component on the substrate is within an orthographic projection of the first gate on the substrate (as cited above).
Yamazaki teaches a method wherein an entirety of orthographic projections (See annotated figure demarking the projection) of all structures of the first active component (the collection of 87, 88, 92a, 92b, 92c) on the substrate (50) are located within an orthographic projection (See annotated figure demarking the projection) of the first gate (51) on the substrate. Modifying the shape of the structures of the first active component (of Ohta) by incorporating the patterning method and resultant shape of Yamazaki when patterning the structures of the first active component of Ohta (See patterning step of Ohta: Fig. 3(e)), would arrive at the claimed orthographic projections configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Yamazaki teaches incorporating this patterning method and resultant shape is an improvement over a patterning method and resultant shape substantially similar to the shape disclosed by Ohta (Yamazaki: Fig. 1D is substantially the same shape as Ohta: Fig. 1). Yamazaki provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the claimed patterning method and resultant shape of the structures of the first active component in that it would reduce manufacturing complexity by reducing the number of photomasks required for patterning ([0265]: “a display device can be formed in which a multi-tone mask is used to reduce the number of masks”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed orthographic projections configuration in the method because it would reduce manufacturing complexity. MPEP 2143 (I)(G).
Regarding claim 10, Ohta in view of Yamazaki discloses the method according to claim 9 (Ohta: Fig. 1), wherein the forming of the first active component comprises:
forming the first semiconductor layer, wherein an amorphous layer ([0115]: “a-Si film…720”) is deposited on the gate insulating layer by chemical vapor deposition ([0115]: “plasma CVD technique”) and the amorphous layer is patterned ([0118]: “patterned”) to form the first semiconductor layer opposite to the first gate;
forming the first doped layer ([0115]: “formed…730”) on the doped regions of the first semiconductor layer by chemical vapor deposition ([0115]: “plasma CVD technique”);
forming the second semiconductor layer ([0115]: “formed…720”) on the first doped layer by chemical vapor deposition ([0115]: “plasma CVD technique”);
and forming the second doped layer ([0115]: “formed…730”) on the second semiconductor layer by chemical vapor deposition ([0115]: “plasma CVD technique”).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ohta in view of Yamazaki as applied to claim 10 above, and further in view of Yang (CN 109713044 A, from IDS).
Regarding claim 11, Ohta in view of Yamazaki discloses the manufacturing method according to claim 10 (Ohta: Fig. 1), wherein the forming of the first doped layer comprises:
depositing an amorphous layer on the first semiconductor layer ([0115]: “a-Si”) by using H2 and SiH4 as reaction gases, using PH3 as a doping gas ([0115]: “a gaseous mixture of silane, hydrogen, and phosphine”), and controlling a flow ratio of PH3 to SiH4 (“(the ratio of flow rate of phosphine relative to silane) is adjusted as appropriate” [0115], thus controlling) to be 0.3 to 0.7, to form the first doped layer (730; corresponding to 73(3) of Fig. 1);
the forming of the second semiconductor layer comprises: depositing an amorphous layer ([0115]: “a-Si”) on the first doped layer by using H2 and SiH4, as reaction gases ([0115]: “a gaseous mixture that contains silane and hydrogen”), to form the second semiconductor layer (720; corresponding to 72(2) of Fig. 1); and
the forming of the second doped layer comprises: depositing an amorphous layer ([0115]: “a-Si”) on the second semiconductor layer by using H2 and SiH4, as reaction gases, using PH3 as a doping gas ([0115]: “a gaseous mixture of silane, hydrogen, and phosphine”), and controlling a flow ratio of PH3 to SiH4 (“(the ratio of flow rate of phosphine relative to silane) is adjusted as appropriate” [0115], thus controlling) to be 2 to 3, to form the second doped layer (710; corresponding to 71 of Fig. 1).
Ohta fails to teach the claimed flow ratios. Thus, Ohta in view of Yamazaki fails to teach “the forming of the first doped layer comprises:
depositing an amorphous layer on the first semiconductor layer by using H2 and SiH4 as reaction gases, using PH3 as a doping gas, and controlling a flow ratio of PH3 to SiH4 to be 0.3 to 0.7” and
“the forming of the second doped layer comprises: depositing an amorphous layer on the second semiconductor layer by using H2 and SiH4, as reaction gases, using PH3 as a doping gas, and controlling a flow ratio of PH3 to SiH4 to be 2 to 3”.
Yang discloses forming a doped layer in the same filed of endeavor comprising using SiH4 and PH3 as reaction and doping gases, and further discloses flow ratios between these gases substantially overlapping the claimed flow ratios (pg. 5 of translation: 0.32-4.1). Additionally, Yang teaches flow ratios may be varied according to desired dopant concentration (pg. 5 of translation: “larger doping concentration”).
One of ordinary skill in the art before the effective filing date could have substituted the flow ratios of Yang in place of the comparable known flow ratios of Ohta in view of Yamazaki, and the results would have been predictable, because the flow ratios (of both Ohta in view of Yamazaki, and Yang) would have functioned in the same way to form N-type doped layers of deliberately chosen concentrations (Yang: pg. 5 of translation: “larger doping concentration”; Ohta: Tables 2 and 3; Ohta: [0090]: “n type impurity”; Ohta: [0098]: “concentration”; Ohta: [0087]: “concentration…n type impurity”; Ohta: [0078]: “n type impurity”; Ohta: [0088]: “concentration”; Ohta: [0115]: “(the ratio of flow rate of phosphine relative to silane) is adjusted as appropriate”). Therefore, having the claimed flow ratios would have been obvious to one of ordinary skill in the art before the effective filing date because these known flow ratios would have been used in the same way with the same predictable results. MPEP 2143 (I)(B).
Claims 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ohta in view of Yamazaki and Wu (US 20160291714 A1).
Regarding independent claim 12, Ohta discloses a display panel ([0168]: “display apparatuses”), comprising:
a substrate (Fig. 1: 1; [0070]: “substrate”);
a light sensor (Ohta is relied upon here to teach a generic component different from a light sensor) comprising:
a first gate (2; [0070]: “gate electrode”) disposed on the substrate;
a gate insulating layer (3; [0070]: “gate insulating layer”) disposed on the first gate and covering the first gate;
a first active component (collection of 4 with Cs and Cd; [0071]: “an active layer”) disposed on the gate insulating layer, wherein the first active component has a channel region (Rc; [0072]: “channel region”) and doped regions (Rs, Rd; [0072]: “first region…second region”; [0108]: “may contain an n type impurity at a relatively low concentration”) located respectively on opposite sides of the channel region;
a first source (a composite of sub-layers 8s, 71, 73(1), and 72(1); [0070]: “source electrode”) disposed on the first active component and electrically connected to one of the doped regions of the first active component ([0070]: “electrically connected”); and
a first drain (a composite of sub-layers 8d, 71, 73(1), and 72(1); [0070]: “drain electrode”) disposed on the first active component and electrically connected to another one of the doped regions of the first active component ([0070]: “electrically connected”);
wherein the first active component comprises:
a first semiconductor layer (a layer composed of sub-layers 4, 74, and 72(3); [0078]: “amorphous silicon layer”) disposed on and directly contacting the gate insulating layer (sub-layer 4 is “directly contacting” 3); and
a contact layer stack (a stack composed of 73(3), 72(2), 73(2) directly stacked sub-layers) disposed on the first semiconductor layer and disposed in the doped regions (directly “on” and “in”); and
wherein the contact layer stack comprises:
a first doped layer (73(3); [0078]: “n type impurity”) disposed on and directly contacting the first semiconductor layer (73(3) is “directly contacting” 72(3));
a second semiconductor layer (72(2)) disposed on and directly contacting the first doped layer, wherein the second semiconductor layer is a single undoped amorphous silicon layer (only one sub-layer is relied upon, thus “single layer”; [0078]: “an intrinsic a-Si layer that substantially contains no n type impurity”); and
a second doped layer (73(2); [0078]: “n type impurity”) disposed on and directly contacting the second semiconductor layer (73(2) is “directly contacting” 72(2)),
wherein the first source and the first drain are disposed on and are in direct contact with the second doped layer, respectively (sub-layer 72(1) is “directly contacting” 73(2));
a switching transistor (another Fig. 1; [0165]: “a plurality of pixels…For each pixel, a pixel TFT is provided as a switching element”. Thus, Fig. 1 may be replicated within the display panel and configured as a switching transistor) comprising:
a second gate (2) disposed between the substrate and the gate insulating layer;
a second active component (collection of 4 with Cs and Cd; [0071]: “an active layer”) disposed on the gate insulating layer and opposite to the second gate;
a second source (a composite of sub-layers 8s, 71, 73(1), and 72(1); [0070]: “source electrode”) disposed on the second active component; and
a second drain (a composite of sub-layers 8d, 71, 73(1), and 72(1); [0070]: “drain electrode”) disposed on the second active component;
a protective layer (Fig. 3: 12) disposed on the gate insulating layer and covering the first source, the first drain, the second source, and the second drain; and
a wiring layer (13) disposed on the protective layer, wherein a portion of the wiring layer is electrically connected to one of the first source and the first drain ([0124]: “Each pixel electrode 13 is in contact with the drain electrode 8d of the corresponding TFT within the contact hole”) through a first via hole of the protective layer ([0122]: “contact hole CH that reaches the drain electrode 8d”), and another portion of the wiring layer is electrically connected to one of the second source and the second drain ([0124]: “Each pixel electrode 13 is in contact with the drain electrode 8d of the corresponding TFT within the contact hole”) through a second via hole of the protective layer ([0122]: “contact hole CH that reaches the drain electrode 8d”);
wherein an entirety of orthographic projections of the first semiconductor layer, the first doped layer, the second semiconductor layer, and the second doped layer on the substrate (See annotated figure) are located within an orthographic projection of the first gate on the substrate (See annotated figure. Partially within.).
Illustrated below is Fig. 3 of Ohta.
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Ohta fails to teach “an entirety of orthographic projections of the first semiconductor layer, the first doped layer, the second semiconductor layer, and the second doped layer on the substrate are located within an orthographic projection of the first gate on the substrate” because Ohta teaches the structures of the first active component have a shape where only a portion of orthographic projections of these structures of the first active component on the substrate is within an orthographic projection of the first gate on the substrate (as cited above).
Yamazaki teaches an entirety of orthographic projections (See annotated figure demarking the projection) of all structures of the first active component (the collection of 87, 88, 92a, 92b, 92c) on the substrate (50) are located within an orthographic projection (See annotated figure demarking the projection) of the first gate (51) on the substrate. Modifying the shape of the structures of the first active component (of Ohta) by incorporating patterning method and resultant shape of Yamazaki when patterning the structures of the first active component of Ohta (See patterning step of Ohta: Fig. 3(e)), would arrive at the claimed orthographic projections configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Yamazaki teaches incorporating this patterning method and resultant shape is an improvement over a patterning method and resultant shape substantially similar to the shape disclosed by Ohta (Yamazaki: Fig. 1D is substantially the same shape as Ohta: Fig. 1). Yamazaki provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the claimed patterning method and resultant shape of the structures of the first active component in that it would reduce manufacturing complexity by reducing the number of photomasks required for patterning ([0265]: “a display device can be formed in which a multi-tone mask is used to reduce the number of masks”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed orthographic projections configuration because it would reduce manufacturing complexity. MPEP 2143 (I)(G).
Ohta separately teaches the component having utility in both a light sensor and a display panel ([0168]: “display apparatuses…image sensors”); however, Ohta in view of Yamazaki fails to disclose the claimed nested configuration of “a display panel, comprising: […] a light sensor”. Nonetheless, Ohta does not expressly require these utilities being mutually exclusive of one another ([0168]).
Wu discloses a display panel (Fig. 2; [0021]: “touch display device”), comprising: a light sensor (T1; [0028]: “sense”) and a switching transistor (T2; [0030]: “turns on”).
Modifying the display panel of Ohta in view of Yamazaki, by including the switching transistor and light sensor in the same panel in the same way as Wu, would arrive at the claimed functional configuration. One of ordinary skill in the art before the effective filing date could have combined the functional configurations of Ohta in view of Yamazaki, and Wu and in combination each element merely performs the same function as it does separately (i.e. the switching transistor and the light sensor each retain these functions). One of ordinary skill in the art before the effective filing date would have recognized that the results of the combination were predictable because Wu teaches a panel using the same elements as Ohta, and functionally configured together in the same panel. One of ordinary skill in the art before the effective filing date would have been motivated to do so to produce a display panel having both input (a light sensor) and output functionality (a display panel) in a single integrated display panel. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it appears to be a mere combination of prior art element configurations according to known functional configurations yielding a predictable panel. MPEP 2143 (I)(A).
Regarding claim 13, Ohta in view of Yamazaki and Wu discloses the display panel according to claim 12 (Ohta: Fig. 1), wherein a material of the first active component and the second active component comprises any one of amorphous silicon, IZO, In2O3, IGZO, and ZnO (selecting amorphous silicon; [0071]: “amorphous silicon”).
Regarding claim 14, Ohta in view of Yamazaki and Wu discloses the display panel according to claim 12 (Ohta: Fig. 1), further comprising: a light-shielding layer ([0166]: “color filter”. Note: the color filter filters at least some colors, thereby “shielding” one side from another) disposed on the switching transistor, wherein an orthographic projection of the second active component on the substrate is within an orthographic projection of the light-shielding layer on the substrate ([0166]: “attached together”, therefor there must be at least a direction between these features, thus an orthographic projection).
Regarding claim 15, Ohta in view of Yamazaki and Wu discloses the display panel according to claim 12 (Ohta: Fig. 1), wherein the first semiconductor layer is an amorphous silicon layer ([0078]: “amorphous silicon layer”); and the first doped layer is an N-type doped amorphous silicon layer ([0078]: “amorphous silicon layer…n type impurity”).
Regarding claim 16, Ohta in view of Yamazaki and Wu discloses the display panel according to claim 12 (Ohta: Fig. 1), wherein the second doped layer is an N-type doped amorphous silicon layer ([0078]: “amorphous silicon layer…n type impurity”).
Regarding claim 17, Ohta in view of Yamazaki and Wu discloses the display panel according to claim 12 (Ohta: Fig. 1), wherein a thickness of the first doped layer ranges from 5 nm to 10 nm ([0088]: “greater than 0 nm but not greater than 20 nm”), and a thickness of the second doped layer ranges from 5 nm to 10 nm ([0088]: “greater than 0 nm but not greater than 20 nm”).
Regarding claim 18, Ohta in view of Yamazaki and Wu discloses the display panel according to claim 12 (Ohta: Fig. 1), wherein a thickness of the second semiconductor layer ranges from 10 nm to 12 nm (the prior art discloses ranges overlapping the claimed ranges; [0088]: “73(n) may be e.g. greater than 0 nm but not greater than 20 nm…72(n) may be equal to or greater than the thickness of the third a-Si layer 73(n)”).
Regarding claim 19, Ohta in view of Yamazaki and Wu discloses the display panel according to claim 12 (Ohta: Fig. 1), wherein the second active component comprises: a third semiconductor layer (4; [0070]: “semiconductor layer”) disposed on the gate insulating layer; and a third doped layer (74; [0090]: “containing an n type impurity”) disposed on the third semiconductor layer.
Regarding claim 20, Ohta in view of Yamazaki and Wu discloses the display panel according to claim 12 (Ohta: Fig. 1), wherein the second active component comprises: a third semiconductor layer (4; [0070]: “semiconductor layer”); and a second contact layer stack (collection of Cs and Cd; [0070]: “contact layer”) disposed on the third semiconductor layer and disposed in second doped regions (Rs, Rd; [0072]: “first region…second region”; [0108]: “may contain an n type impurity at a relatively low concentration”), wherein the second contact layer stack comprises: a third doped layer (74; [0090]: “containing an n type impurity”) disposed on the third semiconductor layer; a fourth semiconductor layer (72(1); [0078]: “a-Si”) disposed on the third doped layer; and a fourth doped layer (73(1); [0078]: “n type impurity contained”) disposed on the fourth semiconductor layer.
Response to Arguments
Applicant's arguments filed 9/27/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1 and 9 that “First, the claimed “first semiconductor layer disposed on and directly contacting the gate insulating layer” can only correspond to LV’s bottom amorphous silicon layer 41, because layer 41 is the only layer directly contacting gate insulation layer 3”. Remarks at pg. 2.
Examiner’s reply:
The examiner agrees with Applicant’s remarks and has relied upon Lv consistent with this interpretation.
Applicant argues:
Applicant argues with respect to amended claims 1 and 9 that “Secondly, the claimed “first doped layer disposed on and directly contacting the first semiconductor layer” can only correspond to LV’s lightly doped amorphous silicon layer 43 disposed directly on layer 41”. Remarks at pg. 2.
Examiner’s reply:
The examiner disagrees and points to MPEP 2111: Broadest Reasonable Interpretation. The examiner finds “layer” as claimed reasonably including meanings beyond Applicant’s contended configuration. Accordingly, the examiner has relied upon a collection of sub-layers (Lv: Fig. 2: sub-layers 43/44/43) to read on the claim. The examiner finds this meaning a reasonable interpretation based at least upon a meaning found elsewhere in the claim for a different layer (i.e., “wherein the second semiconductor layer is a single undoped amorphous silicon layer”) which implies a person of ordinary skill in the art might consider the meaning of a layer could include a plurality of sub-layers or a single sub-layer.
To promote clarity of the record, and to promote compact prosecution, the examiner finds Lv requiring at least two sub-layers 43 ([0035]: “at least two”) and does not teach any configuration requiring fewer than two sub-layers 43.
Applicant argues:
Applicant argues with respect to amended claims 1 and 9 that “Third, the claimed “second semiconductor layer” must be a “single undoped amorphous silicon layer” disposed directly on the first doped layer”. Remarks at pg. 2.
Examiner’s reply:
The examiner does not find Applicant’s remarks persuasive, based on the reading of the reference in the instant Office action for “the first doped layer”. The examiner has relied upon Lv: layer 45 to read on “the second semiconductor layer”.
Applicant argues:
Applicant argues with respect to amended claims 1 and 9 that “Fourth, the claimed “second doped layer” must therefore correspond to the further lightly doped amorphous silicon layer 43 disposed directly on layer 44…Lv does not disclose this arrangement”. Remarks at pg. 2.
Examiner’s reply:
The examiner does not find Applicant’s remarks persuasive, based on the reading of the reference in the instant Office action for “the first doped layer”. The examiner has relied upon Lv: layer 42 to read on “the second doped layer”.
Applicant argues:
Applicant argues with respect to amended claims 1, 9, and 12 that “the presently claimed layer configuration […] Accordingly, neither Ohta nor Yamazaki, alone or in combination, teaches or suggests the amended limitations of Claim 1”. Remarks at pg. 5.
Examiner’s reply:
The examiner disagrees and points to MPEP 2111: Broadest Reasonable Interpretation. The examiner finds “layer” as claimed reasonably including meanings beyond Applicant’s contended configuration. Accordingly, the examiner has relied upon single and plural sub-layers to read on the claimed layers. The examiner finds this meaning a reasonable interpretation based at least upon a meaning found in the claim (i.e., “wherein the second semiconductor layer is a single undoped amorphous silicon layer”) which implies a person of ordinary skill in the art might consider the meaning of a layer could include a plurality of sub-layers or a single sub-layer. The examiner has adjusted the citations and clarifying remarks as necessitated by the claim amendments, and to promote clarity of the record.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Primary Examiner, Art Unit 2817
