DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Butterworth [US 2016/0322549] previously applied, in view of Basin et al [US 2007/0045761] newly applied.
With respect to claim 1, Butterworth (fig. 6) disclose a LED chip scale package, comprising:
a light emitting diode chip (16, pp [0025]) including a top surface, a bottom surface, and a plurality of side surfaces, and having a pad (18, 20, pp [0025]) disposed on the bottom surface that is electrically connected to an external object on one surface thereof, wherein the pad includes a bonding surface;
a phosphor silicon film (64, pp [0041]) surrounding the light emitting diode chip so that at least a portion of the bonding surface of the pad is outside of the phosphor silicon film, and including a plurality of side surfaces having shapes corresponding to the plurality of side surfaces of the light emitting diode chip; and
a metal layer (12, 14, pp [0025]) disposed under a lower surface of the phosphor silicon film and a at least one portion of the bonding surface,
wherein a remaining portion of the bonding surface other than the at least one portion of the bonding surface is not surrounded by the phosphor silicon film and the remaining portion is exposed to the outside of the phosphor silicon film
wherein a maximum width of the metal layer is configured to be smaller than a maximum width of the lower surface of the phosphor silicon film, and
wherein light from the light emitting diode chip is configured to be emitted to the outside of the phosphor silicon film through an upper surface and the plurality of side surfaces of the phosphor silicon film.
Butterworth does not disclose the phosphor silicon film includes a plurality of side surfaces having shapes that are substantially parallel corresponding to the plurality of side surfaces of the light emitting diode chip. However, Basin et al (fig. 12) disclose the phosphor silicon film (26, 62, pp [0063]) includes a plurality of side surfaces having shapes that are substantially parallel corresponding to the plurality of side surfaces of the light emitting diode chip (60, pp [0063]). Moreover, it would have been an obvious matter of design choice to have the phosphor silicon film includes a plurality of side surfaces having shapes that are substantially parallel corresponding to the plurality of side surfaces of the light emitting diode chip as applicant claimed, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1995).
With respect to claim 2, Butterworth (fig. 6) disclose wherein the pad (18, 20, pp [0025]) includes a pair of pad (18, 20, pp [0025]) units spaced apart from each other, the metal layer includes a pair of metal layer units (12, 14, pp [0025]) connected to each of the pad units, and a separation distance between the metal layer units is larger than or equal to a separation distance between the pad units.
With respect to claim 3, Butterworth (fig. 6) disclose a method for manufacturing the LED chip scale package of Claim 1, comprising: a package forming step of wrapping the light emitting diode chip (16, pp [0025]) with the phosphor silicon film (64, pp [0041]) and exposing the bonding surface of the pad to the outside of the phosphor silicon film; and a pad bonding step of bonding the metal layer (12, 14, pp [0025]) to the bonding surface.
With respect to claim 10, Butterworth (fig. 6) disclose wherein the phosphor silicon film (64, pp [0041]) includes one side disposed on the same plane as the bonding surface, and the metal layer (12, 14, pp [0025]) is in contact with the one side of the phosphor silicon film and the at least one portion of the bonding surface that is on the outside of the phosphor silicon film.
With respect to claim 11, Butterworth (fig. 6) disclose wherein the metal layer (12, 14, pp [0025]) is in contact with all of the one side of the phosphor silicon film.
With respect to claim 12, Butterworth (fig. 6) disclose wherein an area of the at least one portion of the bonding surface is bigger than an area of the remaining portion of the bonding surface.
With respect to claim 13, Butterworth (fig. 6) disclose wherein the metal layer (12, 14, pp [0025]) is in direct contact with the at least one portion of the bonding surface that is on the outside of the phosphor silicon film.
Allowable Subject Matter
Claims 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 10/11/2025 have been fully considered but they are not persuasive.
Applicant argues that Butterworth does not disclose the phosphor silicon film includes a plurality of side surfaces having shapes that are substantially parallel corresponding to the plurality of side surfaces of the light emitting diode chip"
Applicant’s argument is not found persuasive because Basin et al (fig. 12) disclose the phosphor silicon film (26, 62, pp [0063]) includes a plurality of side surfaces having shapes that are substantially parallel corresponding to the plurality of side surfaces of the light emitting diode chip (60, pp [0063]). Moreover, it would have been an obvious matter of design choice to have the phosphor silicon film includes a plurality of side surfaces having shapes that are substantially parallel corresponding to the plurality of side surfaces of the light emitting diode chip as applicant claimed, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1995).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V PHAM whose telephone number is (571)272-1715. The examiner can normally be reached M-F 8:30a.m-10:00p.m.
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/HOAI V PHAM/Primary Examiner, Art Unit 2892