Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Remarks
Amendments to the Claims
The Examiner acknowledges the amendments to the claims.
35. U.S.C. 112
The Examiner acknowledges the amendments to claim 15, the 112(a) and 112(b) rejections against claim 15 are withdrawn due to amendments to the claim.
35 U.S.C. 102
The Examiner acknowledges and has fully considered the applicant’s arguments. The applicant argues, (Remarks page 9 paragraph 2) that the prior art does not show each and every feature of the claimed invention. The Examiner respectfully disagrees. The applicant further argues (Remarks page 10 paragraph 6 – page 11 paragraphs 1-2) that Petti et al. (U.S. Patent No. 10534840 B1) has conductor line, 308, that intersects each conductive line 306 in a column, thus there is no “open connection”. The applicant further argues that the Examiner’s assertion that Fig. 6A of Petti shows a memory cell array with memory cells on different layers, thus there would be “opens” between a column of one layer and another layer, as the Examiner had argued in the previous office action mailed on 10/28/2025 (pages 8 and 13). The applicant further argues that Petti does not mention nor show memory cells on different layers or open connections, which would then lead Petti to fail teaching or suggesting the features of independent claims. The Examiner respectfully disagrees for at least the same reasons mentioned in the Final Rejection Office action mailed on 07/01/2025 (pages 3-5), and the Non-Final Rejection Office action mailed on 10/28/2025 (pages 4-9). The Examiner, similarly to the Non-Final Rejection Office action mailed on 10/28/2025 (page4), points out that the argument of the circuitry having an “open connection” seemingly relies on the applicant’s drawing Figure 8, and [0036] of the applicant’s specification. The applicant’s specification [0036] seemingly describes a 3-D array that has been flattened, and what is described as “opens” are the now flattened layers, not electrically directly connected to one another, thus layers of a 3-D array: “The K layers of the sub-voltage approach can effectively be flattened in order to allow the approach to be implemented in a 2D physical array. In example 800, black squares may depict memory devices connecting (or otherwise coupled to) the horizontal and vertical lines which intersect at that location. Nodes not having squares are not connected, and are instead “opens” in this arrangement.” Figure 8 goes on to showcase two drawings. The drawing on the left, with the black squares at intersections, has an equation at the bottom of the first three columns, grouping them together in the equation: “I1 = I11 + I21 + I31”. The applicant’s specification, as mentioned above from [0036], seemingly describes this drawing as a flattened out array with layers. The drawing, in view of the specification, appears to suggest that the column I11 is on a first layer, I21 is on a second layer, and I31 is on a third layer, whereas if the circuit was not flattened out, it would appear that all three were on the same column, I1, but in actuality they are on different columns with depth separating them. This could be seen when looking at I1 in both versions of the circuit in figure 8 whereas when drawn a certain way, the lines V11, V21, and V31 all seemingly intersect the same column, I1, but when taking into account the description of [0036] of the circuit having layers, and looking at the drawing on the right, it indicates that even though the drawing on the right appears to have intersections on the same column, they are actually different columns due to layers in the array.
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In the drawing, V11 intersects, with a black box, column I11. If looking at this at coordinates on a graph, this could be understood as an intersection at (x, y, z) coordinates (0, 0, 0), then the intersection of V21
and I21 could be understood as at coordinates (0, 0, 1), and then the intersection of V31 and I31 could be understood as at coordinates (0, 0, 2), hence the “opens”. Then, to continue the example, the intersection of V11 and I12 could be understood as at coordinates (1, 0, 0), which is how the node at the V11 and I12 intersection connects to column I12, because they are at the same depth (layer). Petti does not have the same exact drawing as the applicant’s figure 8, but it teaches what is to be understood from the applicant’s [0036] and figure 8 drawing. Petti, Column 6 lines 13-17 discuss the memory cell array as a three-dimensional array of memory cells. Petti, Column 6 lines 21-27 discuss a three-dimensional array of memory cells with multiple levels. The Examiner interprets figure 6A of Petti as a layered array of memory cells. Before giving further response, the Examiner wants to highlight the similarity of the right side drawing of the applicant’s figure 8, and figure 6A of Petti.
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In Fig. 6A of Petti, three cells are grouped together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). Even though only two coordinates are shown for the grouping, the reason it is to be understood as a three-dimensional array, or an array with layers, is because the differences in the coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects
with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell
just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the
cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer,
or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled
308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a
second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3)
respectively. Due to this, the cell at 0.25V1 in the grouping of 310(1,1) of Petti figure 6A, is analogous to
the black box cell at intersection V11 and I11 of the applicant’s figure 8, with the cell at 0.5V1 of
grouping 310(1,1) and V1 of grouping 310(1,1) of Petti figure 6A analogous to the black box cell at the
intersection of V21 and I21 and the black box cell at the intersection of V31 and I31 respectively, of the
applicant’s figure 8.
Below the Examiner provides more graphs drawn, derived from the information given from Petti Fig. 6A and Petti, Column 6 lines 13-17 discuss the memory cell array as a three-dimensional array of memory cells, Petti, Column 6 lines 21-27 discuss a three-dimensional array of memory cells with multiple levels, to further show the Examiner’s rebuttal.
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The drawing above is a redrawing of Petti Fig. 6A given the information of locations of points. As shown, at this angle in the graph the three different nodes appear as if they are at a single point for example V1, 0.5V1 and 0.25V1 all grouped together and appearing at location 310(1,1).
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The above drawing is of the exact same graph as before, except at a slightly altered angle. This drawing appears the same as Fig. 6A of Petti (and as the right hand drawing of the applicant’s Figure 8).
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The above drawing is again of the same exact graph as the previous two, only at another slightly different angle. As shown, the same graph at different angles shows more as to what is going on with the circuit in the same manner as the two drawings of the applicant’s figure 8 is seemingly of the same exact circuit at different angles. Figure 6A of Petti, must be a drawing of a 3-D circuit or an array with layers, due to supposedly singular points (such as 310(1,1)) having a plurality of intersections. This singular graph created above is derived from this information given by Petti, and shows that at different angles of the drawing, there are what appears to be “opens” in the same manner as the applicant’s left hand drawing of Figure 8. Due to Figure 6A of Petti being an array with multiple layers (as shown above and described in Petti Column 6 lines 13-17 discuss the memory cell array as a three-dimensional array of memory cells, Petti, Column 6 lines 21-27 discuss a three-dimensional array of memory cells with multiple levels), what may appear as a singular column (as does the applicant’s right hand drawing of Figure 8) seemingly is actually be different columns of the different layers. As with the applicant’s right hand drawing of Figure 8, Petti seemingly combines these columns regardless to add up to values Iv1, Iv2, etc.
Seemingly, the purpose of the applicant highlighting the “opens” of the circuit of figure 8, is to highlight that there are the different layers which, even if flattened down to resemble a 2D array, are not electronically connected, and still function as a layered memory cell array. See the modified drawing of applicant’s figure 8 below where a black box (node) has been added to every intersection of a column and a row.
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The modified drawing above is used to highlight that, if each intersection were connected (not having opens), it would resemble a 2-D cell array, and thus further showing how, as expressed in [0036] of the applicant’s specification, the circuit is meant to represent an array with multiple cell layers.
As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti shows a memory cell array with memory cells on different layers, thus there would be “opens” between a column of one layer and another layer, otherwise it would simply be a regular two-dimensional memory cell array. Due to these reasons, the 102(a)(1) and 102(a)(2) rejections regarding the claims remain.
The applicant seemingly further argues (Remarks page 12), that for similar reasons as argued regarding independent claim 1, claim 11 overcomes the 102 rejections. The Examiner respectfully disagrees for at least the same reasons referenced above.
The applicant seemingly further argues (Remarks page 12-page 13 paragraph 1-2) that dependent claims are in the condition for allowance due to dependance on the independent claims. The Examiner respectfully disagrees for at least the reasons referenced above. The applicant further argues that additional limitations to the dependent claims render them allowable regardless of the independent claim, such as claims 2 and 12 reciting “the first set of memory cells comprising the open connection to a fifth column of the plurality of columns”, and claims 4 and 14 reciting “the second set of memory cells comprising the open connection to a fourth column of the plurality of columns”. The Examiner respectfully disagrees for at least the reasons referenced above regarding Petti teaching layers of an array, and furthermore in regards to the drawn graphs showing the different angles where “open” connections can be seen between a fourth column, and a fifth column, along with more.
35 U.S.C. 103
The applicant argues (Remarks page 13 paragraph 3-4), that no proper combination of the applied art teaches or suggests each and every feature of the claimed invention. The Examiner respectfully disagrees for at least the reasons and motivations for combinations given in the Non-Final Rejection mailed on 02/28/2025 (page 9 regarding claim 6, page 13 regarding claim 16, page 15 regarding claim 8, and page 16 regarding claim 18), the Final Rejection mailed on 07/01/2025 (page 20 regarding claim 6, page 21 regarding claim 16, page 22 regarding claim 8, and page 23 regarding claim 18), the Non-Final Rejection mailed on 10/28/2025 (page 30 regarding claim 6, page 31 regarding claim 16, page 32 regarding claim 8, and page 33 regarding claim 18).
The applicant further seemingly argues (Remarks page 13 – 14 paragraph 2) that the dependent claims 6, 16, 8, 18, 10 and 20 are in condition for allowance due to dependance on the independent claims. The Examiner respectfully disagrees for at least the reasons referenced above. The applicant further seemingly argues that these dependent claims are in condition for allowance by virtue of their own merits, the Examiner respectfully disagrees for at least the reasons listed in the prior office actions.
Conclusion
The Examiner acknowledges the applicant’s conclusion statements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7, 9, 11-15, 17, and 19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Petti.
With regards to claim 1, Petti teaches:
A memory device, comprising: (Col. 5 Lines 45-55 regarding a memory chip device);
a) a memory array arranged in a plurality of rows and a plurality of columns; (Fig. 2B; Col. 5
Lines 58-62 regarding addresses to rows and columns; Col. 9. Lines 34-39 regarding Fig. 2B as a cross point memory array with a plurality of word lines (rows) and bit lines (columns));
b) a plurality of memory cells comprising a first set of memory cells (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three-dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; As interpreted by the Examiner, a first set of memory cells is considered a first layer of memory cells, such as figure 6A memory cells on 0.25V1 at layer 1, 308(1,1), and memory cells on 0.25V2 at layer 1 308(2,1));
and a second set of memory cells, (Col. 6 Lines 13-17 regarding one or more two-dimensional
arrays of memory cells used or one or more three-dimensional arrays of memory cells; Col. 6 Lines 21-27
regarding a three-dimensional array of memory cells with multiple levels; As interpreted by the
Examiner, a second set of memory cells is considered a second layer of memory cells, such as figure 6A
memory cells on 0.5V1 at layer 2, 308(1,2), and memory cells on 0.5V2 at layer 2, 308(2,2));
the first set of memory cells connecting to a first set of rows of the plurality of rows (Fig. 6A
regarding memory cells in a plurality of rows, such as figure 6A memory cells on 0.25V1 at layer 1,
308(1,1));
and a first column of the plurality of columns which intersects the first set of rows, (Col. 6
Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three-
dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory
cells with multiple levels; Fig. 6A regarding memory cells in a plurality of rows, with column 306(1) as a
first column of the plurality of columns intersecting the first set of rows; As interpreted by the Examiner,
figure 6A is to be understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells
are grouped together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted
by the Examiner, even though only two coordinates are shown for the grouping, the reason it is to be
understood as a three-dimensional array, or an array with layers, is because the differences in the
coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects
with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell
just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the
cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer,
or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled
308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a
second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3)
respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti
shows a memory cell array with memory cells on different layers, thus there would be “opens” between
a column of one layer and another layer, otherwise it would simply be a regular two-dimensional
memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column, the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the
different layers (and thus different sub-columns) in the layered cell array);
the first set of memory cells comprising an open connection to a second column and a third column of the plurality of columns, (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three- dimensional array of memory cells with multiple levels; Col. 6 lines 42-44 regarding architecture of 3D array, or stacked 2D arrays; Fig. 6A regarding memory cells in a plurality of rows, such as figure 6A memory cells on 0.25V1 at layer 1, 308(1,1). As interpreted by the Examiner, figure 6A is to be understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells are grouped
together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted by the
Examiner, even though only two coordinates are shown for the grouping, the reason it is to be
understood as a three-dimensional array, or an array with layers, is because the differences in the
coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects
with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell
just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the
cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer,
or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled
308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a
second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3)
respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti
shows a memory cell array with memory cells on different layers, thus there would be “opens” between
a column of one layer and another layer, otherwise it would simply be a regular two-dimensional
memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column, the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the
different layers (and thus different sub-columns) in the layered cell array; See drawings below derived from Petti Fig 6A data
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the second set of memory cells connecting to a second set of rows of the plurality of rows (Fig.
6A regarding memory cells in a plurality of rows, such as figure 6A memory cells on 0.5V1 at layer 2,
308(1,2));
and the second column which intersects the second set of rows, (Col. 6 Lines 13-17 regarding
one or more two-dimensional arrays of memory cells used or one or more three-dimensional arrays of
memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple
levels; Fig. 6A regarding memory cells in a plurality of rows, with column 306(1) as a first column of the
plurality of columns intersecting the first set of rows; As interpreted by the Examiner, figure 6A is to be
understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells are grouped
together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted by the
Examiner, even though only two coordinates are shown for the grouping, the reason it is to be
understood as a three-dimensional array, or an array with layers, is because the differences in the
coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects
with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell
just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the
cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer,
or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled
308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a
second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3)
respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti
shows a memory cell array with memory cells on different layers, thus there would be “opens” between
a column of one layer and another layer, otherwise it would simply be a regular two-dimensional memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column,
the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the
different layers (and thus different sub-columns) in the layered cell array);
the second set of memory cells comprising an open connection to the first column and the third column, (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Col. 6 lines 42-44 regarding architecture of 3D array, or stacked 2D arrays; Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Fig. 6A regarding memory cells in a plurality of rows, with column 306(1) as a first column of the plurality of columns intersecting the first set of rows; As interpreted by the Examiner, figure 6A is to be understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells are grouped together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted by the Examiner, even though only two coordinates are shown for the grouping, the reason it is to be understood as a three-dimensional array, or an array with layers, is because the differences in the coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer, or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled 308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3) respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti shows a memory cell array with memory cells on different layers, thus there would be “opens” between a column of one layer and another layer, otherwise it would simply be a regular two-dimensional memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column, the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the different layers (and thus different sub-columns) in the layered cell array See drawings below derived from Petti Fig 6A data
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wherein each memory cell of the plurality of memory cells is configured to be set to a
predetermined conductance state such that the plurality of memory cells correspond to a plurality of
predetermined conductance states; (Col. 11 Lines 32-40 regarding an example where the memory cells
are related to the resolution of the multiplicand and thus their values are specifically set to reflect that
multiplicand; Col. 11 Lines 1-4 regarding use of an adjustable resistor such that it has different resistance
(or conductance) states);
c) a row control circuit configured to apply a first set of sub-voltages on the first set of rows
(Col. 5 Lines 58-62 regarding a control circuit generating voltages to word lines of the memory array; Fig
6A regarding V1, 0.5V1, 0.25V1; Col. 4 Lines 57-67 and Col. 5 Lines 1-3 regarding each memory cell in a
node receiving voltages with an example of different voltages passed to each);
wherein each sub-voltage of the first set of sub-voltages is proportional to the first total input-
voltage (Fig 6A regarding V1, 0.5V1, 0.25V1; Col. 4 Lines 57-67 and Col. 5 Lines 1-3 regarding each
memory cell in a node receiving voltages with an example of different voltages passed to each);
and each sub-voltage of the second set of sub-voltages is proportional to a second total input
voltage; (Fig 6A regarding V1, 0.5V1, 0.25V1; Col. 4 Lines 57-67 and Col. 5 Lines 1-3 regarding each
memory cell in a node receiving voltages with an example of different voltages passed to each);
and d) a sensing circuit configured to determine a plurality of column currents comprising a
first column current and a second column current, (Figs. 3A-3D, and 9 regarding item 150, a sense
circuit; Col. 8 Lines 33-44 regarding a sense circuit configured to sense the current of memory cells in a
bit line);
the first column flowing out of the first column and the second column current flowing out of
the second column, (Figs. 3A-3D, and 9 regarding item 150, a sense circuit; Col. 8 Lines 33-44 regarding
a sense circuit configured to sense the current of memory cells in a bit line or the combined memory cell
current from multiple memory cells connected to the same bit line; Fig. 6A regarding IV1, IV2, IV3, IV4;
Col 10 Lines 6-7 regarding each bit line current is the summation of the currents of memory cells
connected to that bit line);
wherein the first column current is a sum of currents through each memory cell of the first set
of memory cells and the second column current is a sum of currents through each memory cell of the
second set of memory cells, (Figs. 3A-3D, and 9 regarding item 150, a sense circuit; Col. 8 Lines 33-44
regarding a sense circuit configured to sense the current of memory cells in a bit line or the combined
memory cell current from multiple memory cells connected to the same bit line; Fig. 6A regarding IV1,
IV2, IV3, IV4; Col 10 Lines 6-7 regarding each bit line current is the summation of the currents of
memory cells connected to that bit line);
such that a total current comprises a sum of the plurality of column currents. (Figs. 3A-3D, and
9 regarding item 150, a sense circuit; Col. 8 Lines 33-44 regarding a sense circuit configured to sense the
current of memory cells in a bit line or the combined memory cell current from multiple memory cells
connected to the same bit line; Fig. 6A regarding IV1, IV2, IV3, IV4; Col 10 Lines 6-7 regarding each bit
line current is the summation of the currents of memory cells connected to that bit line).
With regards to claim 2, Petti teaches the memory device of claim 1, as referenced above.
Petti further teaches:
wherein the plurality of predetermined conductance states are equally spaced apart
conductance states, ((Col. 3 Lines 45-47 regarding “multiplicand” being a term used for the value stored in the node of memory cells; Col. 11 Lines 1-4 regarding use of an adjustable resistor such that it has different resistance (or conductance) states; Col. 11 Lines 32-40 regarding an example of the number of memory cells relating to the resolution of the multiplicand where in the example given the values of the memory cells are equally spaced by 1/8 (0.25, 0.375, 0.5)).
and the first set of memory cells comprising the open connection to a fifth column of the plurality of columns. (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three- dimensional array of memory cells with multiple levels; Col. 6 lines 42-44 regarding architecture of 3D array, or stacked 2D arrays; Fig. 6A regarding memory cells in a plurality of rows, such as figure 6A memory cells on 0.25V1 at layer 1, 308(1,1). As interpreted by the Examiner, figure 6A is to be understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells are grouped
together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted by the
Examiner, even though only two coordinates are shown for the grouping, the reason it is to be
understood as a three-dimensional array, or an array with layers, is because the differences in the
coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects
with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell
just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the
cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer,
or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled
308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a
second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3)
respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti
shows a memory cell array with memory cells on different layers, thus there would be “opens” between
a column of one layer and another layer, otherwise it would simply be a regular two-dimensional
memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column, the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the
different layers (and thus different sub-columns) in the layered cell array; See drawings below derived from Petti Fig 6A data
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592
704
media_image5.png
Greyscale
).
With regards to claim 3, Petti teaches the memory device of claim 2, as referenced above.
Petti further teaches:
wherein a remaining each of the plurality of predetermined conductance states are multiples of a first predetermined conductance state. (Col. 3 Lines 45-47 regarding “multiplicand” being a term used for the value stored in the node of memory cells; Col. 11 Lines 1-4 regarding use of an adjustable resistor such that it has different resistance (or conductance) states; Col. 11 Lines 32-40 regarding an example of the number of memory cells relating to the resolution of the multiplicand where in the example given the values of the memory cells are equally spaced by 1/8 (0.125, 0.25, 0.375, 0.5). As interpreted by the examiner, in this example the equally spaced out represented values are multiples of the first value).
With regards to claim 4, Petti teaches the memory device of claim 1, as referenced above.
Petti further teaches:
wherein each sub-voltage of the first set of sub-voltages is a ratio of the first total input voltage, (Fig 6A regarding V1, 0.5V1, 0.25V1 as sub-voltages).
And the second set of memory cells comprising the open connection to a fourth column of the plurality of columns. (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three- dimensional array of memory cells with multiple levels; Col. 6 lines 42-44 regarding architecture of 3D array, or stacked 2D arrays; Fig. 6A regarding memory cells in a plurality of rows, such as figure 6A memory cells on 0.25V1 at layer 1, 308(1,1). As interpreted by the Examiner, figure 6A is to be understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells are grouped
together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted by the
Examiner, even though only two coordinates are shown for the grouping, the reason it is to be
understood as a three-dimensional array, or an array with layers, is because the differences in the
coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects
with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell
just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the
cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer,
or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled
308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a
second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3)
respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti
shows a memory cell array with memory cells on different layers, thus there would be “opens” between
a column of one layer and another layer, otherwise it would simply be a regular two-dimensional
memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column, the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the
different layers (and thus different sub-columns) in the layered cell array; See drawings below derived from Petti Fig 6A data
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608
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592
704
media_image5.png
Greyscale
).
With regards to claim 5, Petti teaches the memory device of claim 1, as referenced above.
Petti further teaches:
wherein a number of different column currents is equal to 𝟏 + 𝑵𝑮(
∑
i
N
v
(
V
/
k
i
)
)
M
a
x
(
k
i
)
,
wherein NG is the number of predetermined conductance states, Nv is the number of memory cell layers, and V/ki is the sub-voltage applied to memory cell layer i. (Fig. 6A. As interpreted by the examiner, the equation in this claim is implicit in the structure of the circuit. With a number of columns, and a number of memory cells, and the circuit it configured such that the cells are of different conductance states, then the number of different column currents is a direct result of that structure shown in Fig. 6A).
With regards to claim 7, Petti teaches the memory device of claim 1, as referenced above.
Petti further teaches:
wherein each of the memory cells comprises conductive bridging random-access memory (CBRAM) whereby each of the plurality of rows serve as an anode of CBRAM cells. (Col. 6 Lines 48-51 regarding memory cells including conductive bridge memory).
With regards to claim 9, Petti teaches the memory device of claim 1, as referenced above.
Petti further teaches:
wherein each of the memory cells comprises resistive RAM (ReRAM). (Col. 6 Lines 35-36 regarding memory cells including ReRAM technologies).
With regards to claim 11, Petti teaches:
A method of controlling a memory device having a memory array arranged in a plurality of rows and a plurality of columns, (Col. 5 Lines 45-55 regarding a memory chip device; Fig. 6A regarding a plurality of rows and columns);
and a plurality of memory cells at each row and column intersection, (Fig. 2B; Col. 5 Lines 58- 62 regarding addresses to rows and columns; Col. 9. Lines 34-39 regarding Fig. 2B as a cross point memory array with a plurality of word lines (rows) and bit lines (columns));
the plurality of memory cells comprising a first set of memory cells (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three-dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; As interpreted by the Examiner, a first set of memory cells is considered a first layer of memory cells, such as figure 6A memory cells on 0.25V1 at layer 1, 308(1,1), and memory cells on 0.25V2 at layer 1 308(2,1));
and a second set of memory cells, (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three-dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; As interpreted by the Examiner, a second set of memory cells is considered a second layer of memory cells, such as figure 6A memory cells on 0.5V1 at layer 2, 308(1,2), and memory cells on 0.5V2 at layer 2, 308(2,2));
the first set of memory cells connecting to a first set of rows of the plurality of rows (Fig. 6A regarding memory cells in a plurality of rows such as figure 6A memory cells on 0.25V1 at layer 1, 308(1,1));
and a first column of the plurality of columns which intersects the first set of rows, (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Fig. 6A regarding memory cells in a plurality of rows, with column 306(1) as a first column of the plurality of columns intersecting the first set of rows; As interpreted by the Examiner,
figure 6A is to be understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells are grouped together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted by the Examiner, even though only two coordinates are shown for the grouping, the reason it is to be understood as a three-dimensional array, or an array with layers, is because the differences in the coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer, or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled 308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3) respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti shows a memory cell array with memory cells on different layers, thus there would be “opens” between a column of one layer and another layer, otherwise it would simply be a regular two-dimensional memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column, the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the different layers (and thus different sub-columns) in the layered cell array; See drawings below derived from Petti Fig 6A data
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);
the first set of memory cells comprising an open connection to a second column and a third column of the plurality of columns, (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three- dimensional array of memory cells with multiple levels; Col. 6 lines 42-44 regarding architecture of 3D array, or stacked 2D arrays; Fig. 6A regarding memory cells in a plurality of rows, such as figure 6A memory cells on 0.25V1 at layer 1, 308(1,1). As interpreted by the Examiner, figure 6A is to be understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells are grouped
together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted by the
Examiner, even though only two coordinates are shown for the grouping, the reason it is to be
understood as a three-dimensional array, or an array with layers, is because the differences in the
coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects
with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell
just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the
cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer,
or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled
308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a
second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3)
respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti
shows a memory cell array with memory cells on different layers, thus there would be “opens” between
a column of one layer and another layer, otherwise it would simply be a regular two-dimensional
memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column,
the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the
different layers (and thus different sub-columns) in the layered cell array; See drawings below derived from Petti Fig 6A data
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608
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592
704
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);
the second set of memory cells connecting to a second set of rows of the plurality of rows (Fig.
6A regarding memory cells in a plurality of rows, such as figure 6A memory cells on 0.5V1 at layer 2,
308(1,2));
and the second column which intersects the second set of rows, (Col. 6 Lines 13-17 regarding
one or more two-dimensional arrays of memory cells used or one or more three-dimensional arrays of
memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple
levels; Fig. 6A regarding memory cells in a plurality of rows, with column 306(1) as a first column of the plurality of columns intersecting the first set of rows; As interpreted by the Examiner, figure 6A is to be
understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells are grouped
together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted by the
Examiner, even though only two coordinates are shown for the grouping, the reason it is to be
understood as a three-dimensional array, or an array with layers, is because the differences in the
coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects
with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell
just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the
cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer,
or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled
308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a
second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3)
respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti
shows a memory cell array with memory cells on different layers, thus there would be “opens” between
a column of one layer and another layer, otherwise it would simply be a regular two-dimensional
memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column,
the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the
different layers (and thus different sub-columns) in the layered cell array; See drawings below derived from Petti Fig 6A data
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608
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592
704
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Greyscale
); the second set of memory cells comprising an open connection to the first column and the third column, (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Col. 6 lines 42-44 regarding architecture of 3D array, or stacked 2D arrays; Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Fig. 6A regarding memory cells in a plurality of rows, with column 306(1) as a first column of the plurality of columns intersecting the first set of rows; As interpreted by the Examiner, figure 6A is to be understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells are grouped together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted by the Examiner, even though only two coordinates are shown for the grouping, the reason it is to be understood as a three-dimensional array, or an array with layers, is because the differences in the coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer, or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled 308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3) respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti shows a memory cell array with memory cells on different layers, thus there would be “opens” between a column of one layer and another layer, otherwise it would simply be a regular two-dimensional memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column, the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the different layers (and thus different sub-columns) in the layered cell array See drawings below derived from Petti Fig 6A data
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592
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);
wherein each memory cell of the plurality of memory cells is configured to be set to a
predetermined conductance state, (Col. 11 Lines 32-40 regarding an example where the memory cells
are related to the resolution of the multiplicand and thus their values are specifically set to reflect that
multiplicand; Col. 11 Lines 1-4 regarding use of an adjustable resistor such that it has different resistance
(or conductance) states);
the method comprising: a) setting each memory cell layer to its predetermined conductance
state such that the plurality of memory cells correspond to a plurality of predetermined conductance
states; (Col. 11 Lines 32-40 regarding an example where the memory cells are related to the resolution
of the multiplicand and thus their values are specifically set to reflect that multiplicand; Col. 11 Lines 1-4
regarding use of an adjustable resistor such that it has different resistance (or conductance) states);
b) applying a first set of sub-voltages on the first set of rows (Col. 5 Lines 58-62 regarding a
control circuit generating voltages to word lines of the memory array; Fig 6A regarding V1, 0.5V1,
0.25V1; Col. 4 Lines 57-67 and Col. 5 Lines 1-3 regarding each memory cell in a node receiving voltages
with an example of different voltages passed to each);
and a second set of sub-voltages on the second set of rows, (Col. 5 Lines 58-62 regarding a
control circuit generating voltages to word lines of the memory array; Fig 6A regarding V1, 0.5V1,
0.25V1; Col. 4 Lines 57-67 and Col. 5 Lines 1-3 regarding each memory cell in a node receiving voltages
with an example of different voltages passed to each);
wherein each sub-voltage of the first set of sub-voltages is proportional to a first total input
voltage (Fig 6A regarding V1, 0.5V1, 0.25V1; Col. 4 Lines 57-67 and Col. 5 Lines 1-3 regarding each
memory cell in a node receiving voltages with an example of different voltages passed to each);
and each sub-voltage of the second set of sub-voltages is proportional to a second total input
voltage; (Fig 6A regarding V1, 0.5V1, 0.25V1; Col. 4 Lines 57-67 and Col. 5 Lines 1-3 regarding each
memory cell in a node receiving voltages with an example of different voltages passed to each);
and c) determining a plurality of column currents comprising a first column current and a
second column current, (Figs. 3A-3D, and 9 regarding item 150, a sense circuit; Col. 8 Lines 33-44
regarding a sense circuit configured to sense the current of memory cells in a bit line);
the first column current flowing out of the first column and the second column current flow
out of the second column, (Figs. 3A-3D, and 9 regarding item 150, a sense circuit; Col. 8 Lines 33-44 regarding a sense circuit configured to sense the current of memory cells in a bit line or the combined
memory cell current from multiple memory cells connected to the same bit line; Fig. 6A regarding IV1,
IV2, IV3, IV4; Col 10 Lines 6-7 regarding each bit line current is the summation of the currents of
memory cells connected to that bit line);
wherein the first column current is a sum of currents through each memory cell of the first set
of memory cells and the second column current is a sum of currents through each memory cell of the
second set of memory cells; (Figs. 3A-3D, and 9 regarding item 150, a sense circuit; Col. 8 Lines 33-44
regarding a sense circuit configured to sense the current of memory cells in a bit line or the combined
memory cell current from multiple memory cells connected to the same bit line; Fig. 6A regarding IV1,
IV2, IV3, IV4; Col 10 Lines 6-7 regarding each bit line current is the summation of the currents of
memory cells connected to that bit line);
and d) calculating a total current by summing the plurality of column currents. (Figs. 3A-3D,
and 9 regarding item 150, a sense circuit; Col. 8 Lines 33-44 regarding a sense circuit configured to sense
the current of memory cells in a bit line or the combined memory cell current from multiple memory
cells connected to the same bit line; Fig. 6A regarding IV1, IV2, IV3, IV4; Col 10 Lines 6-7 regarding each
bit line current is the summation of the currents of memory cells connected to that bit line).
With regards to claim 12, Petti teaches the method of claim 11, as referenced above.
Petti further teaches:
wherein the plurality of predetermined conductance states are equally spaced apart
conductance states, (Col. 3 Lines 45-47 regarding “multiplicand” being a term used for the value stored
in the node of memory cells; Col. 11 Lines 32-40 regarding an example of the number of memory cells
relating to the resolution of the multiplicand where in the example given the values of the memory cells
are equally spaced by 1/8 (0.25, 0.375, 0.5)).
And the first set of memory cells comprising the open connection to a fifth column of the plurality of columns. (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Col. 6 lines 42-44 regarding architecture of 3D array, or stacked 2D arrays; Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Fig. 6A regarding memory cells in a plurality of rows, with column 306(1) as a first column of the plurality of columns intersecting the first set of rows; As interpreted by the Examiner, figure 6A is to be understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells are grouped together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted by the Examiner, even though only two coordinates are shown for the grouping, the reason it is to be understood as a three-dimensional array, or an array with layers, is because the differences in the coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer, or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled 308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3) respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti shows a memory cell array with memory cells on different layers, thus there would be “opens” between a column of one layer and another layer, otherwise it would simply be a regular two-dimensional memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column, the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the different layers (and thus different sub-columns) in the layered cell array See drawings below derived from Petti Fig 6A data
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608
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592
704
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).
With regards to claim 13, Petti teaches the method of claim 12, as referenced above.
Petti further teaches:
wherein a remaining each of the plurality of predetermined conductance states are multiples
of a first predetermined conductance state. (Col. 3 Lines 45-47 regarding “multiplicand” being a term
used for the value stored in the node of memory cells; Col. 11 Lines 32-40 regarding an example of the
number of memory cells relating to the resolution of the multiplicand where in the example given the
values of the memory cells are equally spaced by 1/8 (0.125, 0.25, 0.375, 0.5). As interpreted by the
examiner, in this example the equally spaced out represented values are multiples of the first value).
With regards to claim 14, Petti teaches the method of claim 11, as referenced above.
Petti further teaches:
wherein each sub-voltage of the first set of sub-voltages is a ratio of the first total input
voltage, (Fig 6A regarding V1, 0.5V1, 0.25V1 as sub-voltages).
And the second set of memory cells comprising the open connection to a fourth column of the plurality of columns. (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Col. 6 lines 42-44 regarding architecture of 3D array, or stacked 2D arrays; Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Fig. 6A regarding memory cells in a plurality of rows, with column 306(1) as a first column of the plurality of columns intersecting the first set of rows; As interpreted by the Examiner, figure 6A is to be understood as a memory cell array with multiple layers. In Fig. 6A of Petti, three cells are grouped together (V1, 0.5V1, and 0.25V1), and labeled as 310 with coordinates (1,1). As interpreted by the Examiner, even though only two coordinates are shown for the grouping, the reason it is to be understood as a three-dimensional array, or an array with layers, is because the differences in the coordinates from the row lines. The row lines, 308, are labeled 308(1,3) for the line which intersects with the top left cell at V1 in the grouping of 310(1,1), 308(1,2) for the line which intersects with the cell just below it in the figure at 0.5V1 in the grouping 310(1,1), and 308(1,1) for the line that intersects the cell just below that one in the figure at 0.25V1 in the grouping 310(1,1). If it were simply a single layer, or a strict 2D array, then all three of those cells would be at coordinates (1,1), however, the lines labeled 308 suggest a third dimension or layers to the array with the cell at 0.25V1 at a first layer, 0.5V1 at a second layer, and V1 at a third layer due to them intersecting lines 308(1,1), 308(1,2), and 308(1,3) respectively. As shown above, Petti discusses the layered memory cell array, and figure 6A of Petti shows a memory cell array with memory cells on different layers, thus there would be “opens” between a column of one layer and another layer, otherwise it would simply be a regular two-dimensional memory cell array. Due to these reasons, though column 306(1) appears to resemble a single column, the Examiner interprets the figure to resemble that, but to use the coordinates shown to indicate the different layers (and thus different sub-columns) in the layered cell array See drawings below derived from Petti Fig 6A data
PNG
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592
704
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).
With regards to claim 15, Petti teaches the memory device of claim 11, as referenced above.
Petti further teaches:
wherein a number of different column currents is equal to 𝟏 + 𝑵𝑮(
∑
i
N
v
(
V
/
k
i
)
)
M
a
x
(
k
i
)
, wherein NG is the number of predetermined conductance states, Nv is the number of memory cell
layers, and V/ki is the sub-voltage applied to memory cell layer i. (Fig. 6A. As interpreted by the
examiner, the equation in this claim is implicit in the structure of the circuit. With a number of columns,
and a number of memory cells, and the circuit it configured such that the cells are of different
conductance states , then the number of different column currents is a direct result of that structure
shown in Fig. 6A).
With regards to claim 17, Petti teaches the memory device of claim 11, as referenced above.
Petti further teach:
wherein each of the memory cells comprises conductive bridging random-access memory
(CBRAM) whereby each of the plurality of rows serve as an anode of CBRAM cells. (Col. 6 Lines 48-51
regarding memory cells including conductive bridge memory).
With regards to claim 19, Petti teaches the memory device of claim 11, as referenced above.
Petti further teaches:
wherein each of the memory cells comprises resistive RAM (ReRAM). (Col. 6 Lines 35-36
regarding memory cells including ReRAM technologies).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Petti.
With regards to claim 6, Petti teaches the memory device of claim 5, as referenced above.
Petti does not explicitly teach:
wherein a number of bits equivalent to the number of different column currents is equal to
the binary logarithm of 𝟏 + 𝑵𝑮(
∑
i
N
v
(
V
/
k
i
)
)
M
a
x
(
k
i
)
.
However, in reading this claim in view of the specification, as interpreted by the examiner, this simply is stating the number of bits required to represent the number of different column currents. The number of bits needed to represent the number of different column currents flows from it requiring a certain number of bits to represent that number of different column currents. Furthermore, use of the binary logarithm1 to calculate the minimum number of bits required is well known in the art. Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Petti with use of a binary logarithm to determine the number of bits required to represent the number of different column currents, because doing so would be use of a known technique to improve similar devices, MPEP 2141(III)(C).
With regards to claim 16, Petti teaches the memory device of claim 15, as referenced above.
Petti does not explicitly teach:
wherein a number of bits equivalent to the number of different column currents is equal to
the binary logarithm of 𝟏 + 𝑵𝑮(
∑
i
N
v
(
V
/
k
i
)
)
M
a
x
(
k
i
)
.
However, in reading this claim in view of the specification, as interpreted by the examiner, this simply is stating the number of bits required to represent the number of different column currents. The number of bits needed to represent the number of different column currents flows from it requiring a certain number of bits to represent that number of different column currents. Furthermore, use of the binary logarithm to calculate the minimum number of bits required is well known in the art. Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Petti with use of a binary logarithm to determine the number of bits required to represent the number of different column currents, because doing so would be use of a known technique to improve similar devices, MPEP 2141(III)(C).
Claims 8, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Petti in view of Gopalakrishnan (U.S. Patent Application Publication No. 2008/0232160 A1) hereinafter, “Gopalakrishnan”.
With regards to claim 8, Petti teaches the memory device of claim 7, as referenced above.
Petti further teaches:
wherein: a) each of the plurality of columns comprises a metal; (Col. 6 Lines 51-58 regarding use of Solid Electrolyte material which include two solid metal electrodes with examples of metals used such as tungsten, silver, or copper);
and c) each of the plurality of rows comprises a multi-layer stack having an oxide, (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Col. 16 Lines 32-36 regarding use of a metal oxide material for memory cells);
an anode, and (Col.6 Lines 51-58 regarding solid electrolyte materials used, including two solid
metal electrodes, with an example of one relatively inert and the other electrochemically active);
and a capping layer. (Col. 6 Lines 57-58 regarding a thin film of solid electrolyte between two electrodes);
Petti does not explicitly teach:
b) a plurality of vias comprises a metal;
However, Gopalakrishnan teaches:
b) a plurality of vias comprises a metal; (Figs. 11A-11F; ¶0172 regarding via fill material; ¶0085 regarding different metal material used)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Petti with a metal via from Gopalakrishnan. It is obvious to apply a known technique to a known device (method, or product) ready for improvement to yield predictable results. MPEP 2141.III.(D). In circuitry a via2 is typically made of metal for the purpose of conducting electricity.
With regards to claim 18, Petti teaches the method of claim 17, as referenced above.
Petti further teaches:
wherein: a) each of the plurality of columns comprises a metal; (Col. 6 Lines 51-58 regarding use of Solid Electrolyte material which include two solid metal electrodes with examples of metals used such as tungsten, silver, or copper);
and c) each of the plurality of rows comprises a multi-layer stack having an oxide (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three- dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Col. 16 Lines 32-36 regarding use of a metal oxide material for memory cells);
, an anode, (Col.6 Lines 51-58 regarding solid electrolyte materials used, including two solid metal electrodes, with an example of one relatively inert and the other electrochemically active);
and a capping layer. (Col. 6 Lines 57-58 regarding a thin film of solid electrolyte between two electrodes).
Petti does not explicitly teach:
b) a plurality of vias comprises a metal;
However, Gopalakrishnan teaches:
b) a plurality of vias comprises a metal; (Figs. 11A-11F; ¶0172 regarding via fill material; ¶0085 regarding different metal material used)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Petti with a metal via from Gopalakrishnan. It is obvious to apply a known technique to a known device (method, or product) ready for improvement to yield predictable results. MPEP 2141.III.(D). In circuitry a via3 is typically made of metal for the purpose of conducting electricity.
Claims 10, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Petti in view of Kamalanathan (U.S. Patent No. 9001553 B1) hereinafter, “Kamalanathan”.
With regards to claim 10, Petti teaches the memory device of claim 1, as referenced above.
Petti further teaches:
wherein each of the plurality of predetermined conductance states is verified by the row control circuit and the sensing circuit being configured to: (Figs. 3A-3D, and 9 regarding item 150, a sense circuit; Col. 8 Lines 33-44 regarding a sense circuit configured to sense the current of memory cells in a bit line; Col. 8 Lines 23-25 regarding memory cell sensed by the circuit and compared to determine the state memory cell is in);
a) raise each of the plurality of rows and the plurality of columns to a predetermined read voltage; (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one or more three-dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional array of memory cells with multiple levels; Col. 8 Lines 23-25 regarding applying a read voltage to the circuit);
b) measure the plurality of column currents; (Figs. 3A-3D, and 9 regarding item 150, a sense circuit; Col. 8 Lines 33-44 regarding a sense circuit configured to sense the current of memory cells in a bit line);
d) measure a column current flowing out of a column containing the memory cell to be verified in order to verify a desired conductance state. (Figs. 3A-3D, and 9 regarding item 150, a sense circuit; Col. 8 Lines 33-44 regarding a sense circuit configured to sense the current of memory cells in a bit line; Col. 8 Lines 23-25 regarding memory cell sensed by the circuit and compared to determine the state memory cell is in).
Petti does not explicitly teach:
c) change the voltage applied to a row containing the memory cell to be verified to a verification voltage; and
However, Kamalanathan teaches:
c) change the voltage applied to a row containing the memory cell to be verified to a verification voltage; and (Col. 6 Lines 11-12 regarding a verification operation in which a verification voltage is applied)
Therefore, it would have been obvious before the effective filing date of the claimed invention
to one of ordinary skill in the art to which said subject matter pertains to combine Petti with a verification feature of Kamalanathan “to verify that the memory unit is programmed into a stable low resistance state” (Kamalanathan: Col. 5 Lines 56-58).
With regards to claim 20, Petti teaches the method of claim 11, as referenced above.
Petti further teaches:
further comprising verifying each of the plurality of predetermined conductance states by:
(Figs. 3A, 3D, and 9 regarding item 150, a sense circuit; Col. 8 Lines 33-44 regarding a sense circuit
configured to sense the current of memory cells in a bit line; Col. 8 Lines 23-25 regarding memory cell
sensed by the circuit and compared to determine the state memory cell is in);
a) raising each of the plurality of rows and the plurality of columns to a predetermined read
voltage; (Col. 6 Lines 13-17 regarding one or more two-dimensional arrays of memory cells used or one
or more three-dimensional arrays of memory cells; Col. 6 Lines 21-27 regarding a three-dimensional
array of memory cells with multiple levels; Col. 8 Lines 23-25 regarding applying a read voltage to the
circuit);
b) measuring the plurality of column currents; (Figs. 3A-3D, and 9 regarding item 150, a sense
circuit; Col. 8 Lines 33-44 regarding a sense circuit configured to sense the current of memory cells in a
bit line);
and d) measuring a column current flowing out of a column containing the memory cell to be
verified in order to verify a desired conductance state. (Figs. 3A-3D, and 9 regarding item 150, a
sense circuit; Col. 8 Lines 33-44 regarding a sense circuit configured to sense the current of memory cells
in a bit line; Col. 8 Lines 23-25 regarding memory cell sensed by the circuit and compared to determine
the state memory cell is in).
Petti does not explicitly teach:
c) changing the voltage applied to a row containing the memory cell to be verified to a verification voltage;
However, Kamalanathan teaches:
c) changing the voltage applied to a row containing the memory cell to be verified to a verification voltage; (Col. 6 Lines 11-12 regarding a verification operation in which a verification voltage is applied)
Therefore, it would have been obvious before the effective filing date of the claimed invention
to one of ordinary skill in the art to which said subject matter pertains to combine Petti with a
verification feature of Kamalanathan “to verify that the memory unit is programmed into a stable low
resistance state” (Kamalanathan: Col. 5 Lines 56-58).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.A.K./Examiner, Art Unit 2182
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
1 Chapter 1 algorithms with numbers. (2016a). https://people.eecs.berkeley.edu/~vazirani/algorithms/chap1.pdf
2 ExpressPCB. (2015, July 10). Expresspcb Manufacturing Service. https://www.expresspcb.com/what-is-the-
difference-between-a-pad-and-a-via/
3 ExpressPCB. (2015, July 10). Expresspcb Manufacturing Service. https://www.expresspcb.com/what-is-the-
difference-between-a-pad-and-a-via/
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