Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
37 pending office actions • 16 art units • 36 examiners • 0 of 37 (0%) have an AI response strategy ready • 185 patents granted in the last 365 days
Globalfoundries U S Inc. is managing 37 pending office actions in the Semiconductors, Circuits & Optics technology area. These actions are distributed among 36 distinct examiners and 16 distinct art units. This suggests a broad prosecution strategy across many specialized semiconductor units within the patent office.
PETERSON, ERIK T is the busiest examiner for the company, with 2 pending office actions. Given that there are 37 actions and 36 examiners, almost every examiner is reviewing only a single application for the company. This requires managing prosecution across 16 different art units with very little examiner-level overlap. The high number of 36 distinct examiners relative to 16 art units indicates that the company often deals with multiple examiners within the same technical group. This decentralized environment means that the company must adapt to a wide variety of individual examiner styles across the Semiconductors, Circuits & Optics sector.
Based on the USPTO statutory response window for each pending office action. 9 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 9 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 + other | 1 (3%) |
| §103 only | 10 (27%) |
| §102 only | 4 (11%) |
| §112 only | 2 (5%) |
| Double-patenting only | 1 (3%) |
| Double-patenting + other | 1 (3%) |
| Multi-statute (no §101) | 18 (49%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| PETERSON, ERIK T | 2 | 76.5% | +11.0% |
| PHAM, LY D | 1 | 94.0% | +3.4% |
| AGGER, ELIZABETH ROSE | 1 | 95.2% | -0.9% |
| GONDARENKO, NATALIA A | 1 | 72.8% | +20.5% |
| KIANNI, KAVEH C | 1 | 87.2% | +11.0% |
| RETEBO, METASEBIA T | 1 | 89.5% | +5.3% |
| GHEYAS, SYED I | 1 | 82.5% | +3.9% |
| BESLER, CHRISTOPHER JAMES | 1 | 68.4% | +41.5% |
| YOON, ERIC | 1 | 58.9% | +65.9% |
| CRAWFORD EASON, LATANYA N | 1 | 78.4% | +0.4% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18790021 | COMPARATOR CIRCUITS | RETEBO, METASEBIA T | 36d |
| 18973257 | METHOD AND CIRCUIT FOR BIT READ DURING NON-VOLATILE MEMEORY POWER-ON-RESET | AGGER, ELIZABETH ROSE | — |
| 18802210 | PIC DIE AND PACKAGE WITH MULTIPLE LEVEL AND MULTIPLE DEPTH CONNECTIONS OF FIBERS TO ON-CHIP OPTICAL COMPONENTS | KIANNI, KAVEH C | — |
| 18767418 | LATERAL BIPOLAR TRANSISTORS | GHEYAS, SYED I | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18237195 | TRANSISTOR WITH THERMAL PLUG | PETERSON, ERIK T | 19d overdue |
| 18228713 | FIELD-EFFECT TRANSISTORS WITH A GATE DIELECTRIC LAYER FORMED ON A SURFACE TREATED BY ATOMIC LAYER ETCHING | NICELY, JOSEPH C | 15d overdue |
| 17902463 | HIGH-ELECTRON-MOBILITY TRANSISTOR | YEMELYANOV, DMITRIY | 13d |
| 18378788 | WAVEGUIDE STRUCTURES | LEPISTO, RYAN A | 71d |
| 18392464 | HETEROJUNCTION BIPOLAR TRANSISTOR WAFERS WITH BACKSIDE SUB-COLLECTOR CONTACT | NGUYEN, DUY T V | 76d |
| 19004610 | BIT CELL, IN-MEMORY COMPUTING CIRCUIT FOR MAJORITY FUNCTIONS, AND IN-MEMORY COMPUTING METHOD | PHAM, LY D | — |
| 18886381 | VERTICALLY STACKED DIODE-TRIGGER SILICON CONTROLLED RECTIFIER | GONDARENKO, NATALIA A | — |
| 18676963 | FIXTURE | BESLER, CHRISTOPHER JAMES | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 6 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18237195 | TRANSISTOR WITH THERMAL PLUG | PETERSON, ERIK T | 19d overdue |
| 18886381 | VERTICALLY STACKED DIODE-TRIGGER SILICON CONTROLLED RECTIFIER | GONDARENKO, NATALIA A | — |
| 18802210 | PIC DIE AND PACKAGE WITH MULTIPLE LEVEL AND MULTIPLE DEPTH CONNECTIONS OF FIBERS TO ON-CHIP OPTICAL COMPONENTS | KIANNI, KAVEH C | — |
| 18676963 | FIXTURE | BESLER, CHRISTOPHER JAMES | — |
| 18660942 | ANALYSIS AND MANUFACTURE OF CURVED FEATURES FOR INTEGRATED CIRCUITS | YOON, ERIC | — |
| 18415955 | STRUCTURE WITH TWO WORK FUNCTION METALS OVER CONDUCTIVE BRIDGE, AND METHOD TO FORM SAME | PETERSON, ERIK T | — |
| Art Unit | Apps |
|---|---|
| 2898 | 4 |
| 2897 | 4 |
| 2813 | 2 |
| 2817 | 2 |
| 2893 | 2 |
| 2891 | 2 |
| 2818 | 2 |
| 2812 | 2 |
| 2874 | 2 |
| 2827 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19004610 | BIT CELL, IN-MEMORY COMPUTING CIRCUIT FOR MAJORITY FUNCTIONS, AND IN-MEMORY COMPUTING METHOD | PHAM, LY D | 2827 | §102§112 | Non-Final OA | — | Pending | Dec 30, 2024 |
| 18973257 | METHOD AND CIRCUIT FOR BIT READ DURING NON-VOLATILE MEMEORY POWER-ON-RESET | AGGER, ELIZABETH ROSE | 2824 | §103 | Non-Final OA | — | Pending | Dec 09, 2024 |
| 18886381 | VERTICALLY STACKED DIODE-TRIGGER SILICON CONTROLLED RECTIFIER | GONDARENKO, NATALIA A | — | §103§112Other | Non-Final OA | — | Pending | Sep 16, 2024 |
| 18802210 | PIC DIE AND PACKAGE WITH MULTIPLE LEVEL AND MULTIPLE DEPTH CONNECTIONS OF FIBERS TO ON-CHIP OPTICAL COMPONENTS | KIANNI, KAVEH C | — | §103 | Non-Final OA | — | Pending | Aug 13, 2024 |
| 18790021 | COMPARATOR CIRCUITS | RETEBO, METASEBIA T | 2842 | §103DP | Non-Final OA | 36d | Pending | Jul 31, 2024 |
| 18767418 | LATERAL BIPOLAR TRANSISTORS | GHEYAS, SYED I | — | DP | Non-Final OA | — | Pending | Jul 09, 2024 |
| 18676963 | FIXTURE | BESLER, CHRISTOPHER JAMES | — | §102§112 | Non-Final OA | — | Pending | May 29, 2024 |
| 18660942 | ANALYSIS AND MANUFACTURE OF CURVED FEATURES FOR INTEGRATED CIRCUITS | YOON, ERIC | 4100 | §101§102§103 | Final Rejection | — | Pending | May 10, 2024 |
| 18659282 | SEMICONDUCTOR ON INSULATOR WAFER WITH CAVITY STRUCTURES | CRAWFORD EASON, LATANYA N | 2813 | §102§103Other | Non-Final OA | — | Pending | May 09, 2024 |
| 18635547 | STACKED HIGH-POWER RF SWITCH | BAIG, ANEESA RIAZ | — | §102§103§112 | Non-Final OA | — | Pending | Apr 15, 2024 |
| 18604947 | ISOLATION STRUCTURE FOR MULTI-VOLTAGE INTEGRATED CIRCUIT | AHMADI, MOHSEN | 2896 | §102§103 | Non-Final OA | — | Pending | Mar 14, 2024 |
| 18603348 | STRUCTURES INCLUDING AN ISOTOPICALLY-DEPLETED SEMICONDUCTOR LAYER | JAHAN, BILKIS | 2817 | §103 | Non-Final OA | — | Pending | Mar 13, 2024 |
| 18594074 | CAPACITIVE JUNCTION BETWEEN CONDUCTIVE LINE AND CONDUCTIVE PILLAR WITH METHODS TO FORM SAME | NETTLES, CORALIE ANN | 2893 | §102§103 | Final Rejection | — | Pending | Mar 04, 2024 |
| 18589686 | BIPOLAR TRANSISTOR STRUCTURE WITH FERROELECTRIC MATERIAL | PRIDEMORE, NATHAN ANDREW | 2898 | §102§103§112 | Non-Final OA | — | Pending | Feb 28, 2024 |
| 18586666 | THREE-DIMENSIONAL INTEGRATED CIRCUIT (3DIC) AND 3DIC DESIGN METHOD AND SYSTEM | NGO, BRIAN | — | §102 | Non-Final OA | — | Pending | Feb 26, 2024 |
| 18442069 | INDUCTOR STRUCTURE INTEGRATED IN SEMICONDUCTOR DEVICE | ANDERSON, WILLIAM H | 2817 | §103 | Final Rejection | — | Pending | Feb 14, 2024 |
| 18427028 | DEVICE WITH INNER SPACER SIDEWALL STRUCTURES | WATTS, JEREMY DANIEL | 2897 | §102§103 | Final Rejection | — | Pending | Jan 30, 2024 |
| 18427206 | DEVICE WITH OUTER CONDUCTIVE SPACER | WRIGHT, TUCKER J | 2891 | §102 | Non-Final OA | — | Pending | Jan 30, 2024 |
| 18415955 | STRUCTURE WITH TWO WORK FUNCTION METALS OVER CONDUCTIVE BRIDGE, AND METHOD TO FORM SAME | PETERSON, ERIK T | 2898 | §102§103§112 | Non-Final OA | — | Pending | Jan 18, 2024 |
| 18416466 | STRUCTURE AND METHOD FOR AN INDUCTOR HAVING A WINDING WITH A FIRST SEGMENT CONNECTED TO TWO SECOND SEGMENTS | PATEL, RAKESH BHASKARBHAI | — | §102 | Non-Final OA | — | Pending | Jan 18, 2024 |
| 18414508 | EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR (EDMOS) FIELD EFFECT TRANSISTOR (FET) WITH DUAL THICKNESS SEMICONDUCTOR MATERIAL | MANN, WILLIAM ROBERT | 2897 | §102§103 | Non-Final OA | — | Pending | Jan 17, 2024 |
| 18392464 | HETEROJUNCTION BIPOLAR TRANSISTOR WAFERS WITH BACKSIDE SUB-COLLECTOR CONTACT | NGUYEN, DUY T V | 2818 | §102§103 | Final Rejection | 76d | Pending | Dec 21, 2023 |
| 18515375 | STRUCTURE AND METHOD FOR INDUCTOR WITH WINDINGS HAVING DIFFERENT WIDTHS | HINSON, RONALD | — | §102§103 | Non-Final OA | — | Pending | Nov 21, 2023 |
| 18509591 | SWITCHING MEMORY ELEMENTS ACCESSED BY HETEROJUNCTION BIPOLAR TRANSISTORS | CHOI, CALVIN Y | 2812 | §103 | Non-Final OA | — | Pending | Nov 15, 2023 |
| 18501602 | PHOTODETECTORS WITH A NOTCHED LIGHT-ABSORBING LAYER | CHU, CHRIS H | 2874 | §103 | Non-Final OA | 75d | Pending | Nov 03, 2023 |
| 18378788 | WAVEGUIDE STRUCTURES | LEPISTO, RYAN A | 2874 | §103§112 | Non-Final OA | 71d | Pending | Oct 11, 2023 |
| 18478452 | SILICON CARBIDE CHANNEL WITH CAPPING SEMICONDUCTOR HAVING HIGHER CHARGE CARRIER MOBILITY | RAHMAN, MOIN M | 2898 | §102 | Non-Final OA | — | Pending | Sep 29, 2023 |
| 18463288 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND METHODS OF FORMING THE SAME | HAIDER, WASIUL | 2812 | §103 | Final Rejection | — | Pending | Sep 07, 2023 |
| 18237195 | TRANSISTOR WITH THERMAL PLUG | PETERSON, ERIK T | 2898 | §102§103§112 | Non-Final OA | 19d overdue | Pending | Aug 23, 2023 |
| 18228713 | FIELD-EFFECT TRANSISTORS WITH A GATE DIELECTRIC LAYER FORMED ON A SURFACE TREATED BY ATOMIC LAYER ETCHING | NICELY, JOSEPH C | 2813 | §103§112 | Final Rejection | 15d overdue | Pending | Aug 01, 2023 |
| 18200683 | PHOTODETECTORS WITH ONE OR MORE CONFINING FEATURES | DEGRASSE, IAN ISAAC | 2818 | §103 | Non-Final OA | 36d | Pending | May 23, 2023 |
| 18302349 | SYSTEM FOR IMAGING SUBSTRATE SURFACE AND RELATED METHOD | GARBER, ERIN R | 2878 | §103 | Final Rejection | — | Pending | Apr 18, 2023 |
| 18111959 | HIGH PERFORMANCE SILICON CONTROLLED RECTIFIER DEVICES | KIM, JAHAE | 2897 | §103 | Non-Final OA | — | Pending | Feb 21, 2023 |
| 18072127 | DEVICE WITH PLASMA INDUCED DAMAGE (PID) PROTECTION | ZHU, SHENG-BAI | 2897 | §112 | Non-Final OA | — | Pending | Nov 30, 2022 |
| 17902463 | HIGH-ELECTRON-MOBILITY TRANSISTOR | YEMELYANOV, DMITRIY | 2891 | §102§103§112 | Final Rejection | 13d | Pending | Sep 02, 2022 |
| 17521076 | TRANSISTOR WITH FACETED, RAISED SOURCE/DRAIN REGION | CHEN, JACK S J | 2893 | §112 | Non-Final OA | 15d overdue | Pending | Nov 08, 2021 |
| 17601778 | MEMORY-BASED VECTOR-MATRIX MULTIPLICATION | KLOSTERMAN II, JEROME ANTHONY | 2182 | §102§103 | Non-Final OA | — | Pending | Oct 06, 2021 |
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