Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This responds to Applicant’s Arguments/Remarks filed 03/04/2026. Claim 1has been amended. Claims 3-4 and 6-7 have been cancelled. Claims 1-2, 5, 8-11 are now pending in this Application.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2, 5, 8-11 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Claims 1-2,5,8-11 appears to be directed to an abstract idea without reciting additional limitations that tie it to a practical application or without reciting additional limitations that amount to significantly more than the abstract idea. One can mentally generate graph with nodes for spaces in a building as well as assets that are contained within those spaces. Then one can also mentally associate and classify senor readings and generate relationships between spaces, assets and sensors. The additional limitations are receiving data. These additional limitations are mere data gathering which are insignificant extra solution activities under step 2A prong II and well understood routine and conventional under step 2B (For Berkhiemer See MPEP 2106.05(d)(II) Versata.)
Step 2A, Prong One: Mathematical Concepts
Independent claims 1, and 5 are directed to a search system includes an input portion, display portion, a processing portion and an arithmetic portion;
A database in which a second circuit diagram information is register,
The input portion is to input circuit diagram,
The first circuit diagram; circuit element comprise at least one of a transistor, a capacitor, a resistor, and inductor, a diode or a light-emitting diode,
The processing portion is to convert the input first circuit diagram into a first graph,
The arithmetic portion is to calculate similarity between the first and a second graph based on the second circuit diagram,
Display the similarity.
Step 2A Prong Two and Step 2B
Use of circuit diagram, processing portion, arithmetic portion to input, convert, calculate and display the similarity constitute use of a generic computer used as tool to implement the abstract idea discussed above.
The step of receiving data associated with a building constitutes an insignificant extra-solution activity in the form of mere data gather, see MPEP 2106.05(g)
i. Performing clinical tests on individuals to obtain input for an equation, In re Grams, 888 F.2d 835, 839-40; 12 USPQ2d 1824, 1827-28 (Fed. Cir. 1989);
Looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. There is no indication that the combination of elements improves the functioning of a computer or improves any other technology. Their collective functions merely provide conventional computer implementation.
Claims 2, 8-11 are rejected under 35 U.S. C. 101 because as they depend from independent claims 1 and 5. Which is directed to a judicial exception without significantly more. The additional limitation of claim 2 “a server connected to the terminal via a network, wherein the database is stored in the server”, claims 8-11 “wherein the graph comprises nodes and edges, undirected graph” constitutes insignificant extra solution activity and does not integrate the abstract idea into a practical application. The limitation is merely a generic implement using a computer and does not amount to significantly more than the abstract idea.
Therefore, the examiner respectfully maintained the rejection.
Claim Objections
Applicant argues that claims 1 and 5 do not disclose “whereby” clauses, but recite particular configuration/functional aspects of the “input portion,” “first circuit diagram information,” “each of the circuit elements,” “processing portion” “arithmetic portion” and “display portion” in the wherein clauses.
In response to Applicant argues, the examiner submits that, Applicant’s argument is not persuasive because the rejection is not based on the use of “whereby” clause. The rejection convers the functional language recited in the “wherein” clauses, which state intended use, result or functional characteristics of the claimed “input portion” “first circuit diagram information,” “each of the circuit elements,” “processing portion” “arithmetic portion” and “display portion” without positively reciting sufficient structural or operational limitations. Accordingly, the claim fails to particularly point out and distinctly claim the invention under claims objection. The examiner respectfully maintained the rejection.
Response to Arguments
Applicant's arguments filed 03/04/2026 have been fully considered but they are not persuasive.
Applicant argues that “one of ordinary skill in the art would have had no reason to combine Scheer and Mathur”.
In response to Applicant’s argument, the examiner submits that, although Scheer discloses modeling and simulation of superconducting circuits and Mathur teaches using graph representations of circuits to determine circuit equivalence, one of ordinary skill in the art would have recognized that the references are reasonably pertinent to the same filed of endeavor, namely circuit analysis and processing and Mathur’s graph-based equivalence techniques are applicable to circuit representations generally, including superconducting circuits modeled by Mathur. The combination would improve analysis, comparison and equivalence determination of circuit topologies.
Therefore, the examiner respectfully maintained the rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 8, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Scheer et al (U.S. Pub No. 2018/0240035), and in view of Mathur et al (U.S. Patent No. 7,222,317).
As per claim 1, Scheer discloses a search system comprising:
a computer comprising an input portion, a display portion, a processing portion and an arithmetic portion; and (Par [0031, 0078, 0110]);
wherein the input portion is configured to input first circuit diagram information; wherein the first circuit diagram information is a circuit element included in a circuit diagram (Par [0043, 0049]);
wherein each of the circuit element comprise at least one of a transistor, a capacitor, a resistor, an inductor, a diode, or a light-emitting diode (Par [0043]);
wherein the processing portion configured to convert the input first circuit diagram information into a first graph (par [0044, 0049]);
wherein the display portion is configured to display (Par [0110]).
Scheer does not explicitly disclose a database in which second circuit diagram information, a second graph based on the second circuit diagram are registered; wherein the arithmetic portion configured to calculate similarity between the first graph and a second graph based on the second diagram information; and wherein the display portion configured to display the similarity on the terminal.
However, Mathur discloses a database in which second circuit diagram information, a second graph based on the second circuit diagram are registered; wherein the arithmetic portion configured to calculate similarity between the first graph and a second graph based on the second diagram information; and wherein the display portion configured to display the similarity on the terminal (Col 2 lines 63-67 through col 3 lines 1-35).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Mathur into the teaching of Scheer in order to provide an efficient method for the comparison arithmetic circuit (Col 9 lines 36-38).
As per claim 2, Scheer discloses the search system according to claim 1, further comprising a server connected to the terminal via a network, wherein the database is stored in the server (Col 10 lines 11-25).
As per claim 5, Scheer discloses a search method comprising the steps of:
inputting first circuit diagram information to a first region of a terminal (Par [0069]),
converting the first circuit diagram information into a first graph (Par [0094]);
wherein the first circuit diagram information is a circuit element included in a circuit diagram (Par [0069]).
Wherein the first circuit diagram information is circuit element included in a circuit diagram and the circuit diagram (Par [0043, 0049]), and
wherein the circuit element comprises at least one of a transistor, a capacitor, a resistor, an inductor, a diode or a light-emitting diode (par [0043]);
display portion is configured to display (Par [0110]).
Scheer does not explicitly disclose displaying the first graph on a second region of the terminal; calculating similarity between the first graph and a second graph registered in a database; and displaying the similarity and the second graph that correspond to the similarity on the terminal.
However, Mathur discloses displaying the first graph on a second region of the terminal; calculating similarity between the first graph and a second graph registered in a database; and displaying the similarity and the second graph that correspond to the similarity on the terminal (Col 2 lines 63-67 through col 3 lines 1-35).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Mathur into the teaching of Scheer in order to provide an efficient method for the comparison arithmetic circuit (Col 9 lines 36-38).
As per claim 8, Scheer discloses the search system according to claim 1, wherein the first graph comprises nodes and edges (Par [0044, 0049]).
As per claim 10, Scheer discloses the search method according to claim 5, wherein the first graph comprises nodes and edges (Par [0044, 0049]).
Claim(s) 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Scheer et al, Mathur et al, and further in view of Agarwal (U.S. Pub No. 2008/0097941 A1).
As per claim 9, Scheer and Mathur do not explicitly disclose the search system according to claim 1, wherein the first graph is an undirected graph.
However, Agarwal discloses wherein the first graph is an undirected graph (Par [0091]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Agarwal into the teaching of Scheer as modified by Mathur in order to provide a flexible for a ranking function on a graph data (par [0024]).
As per claim 11, Scheer and Mathur do not explicitly disclose the search method according to claim 5, wherein the first graph is an undirected graph.
However, Agarwal discloses wherein the first graph is an undirected graph (Par [0091]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Agarwal into the teaching of Scheer as modified by Mathur in order to provide a flexible for a ranking function on a graph data (par [0024]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 7-8, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cecchi et al (U.S. Pub No. 2016/0379267 A), and Lu (U.S. Pub No. 2015/0178963 A1), and further in view of Kurokawa (U.S. Pub No. 2012/0182788 A1).
As per claim 1, Cecchi discloses a search system comprising:
a computer comprising an input portion, a display portion, a processing portion and an arithmetic portion; and (Par [0094]);
a database in which second circuit diagram information is registered (Par [0063, 0069-0070]);
wherein the input portion is configured to input first circuit diagram information (Par [0069, 0094]);
wherein the processing portion configured to convert the input first circuit diagram information into a first graph (par [0094]).
Cecchi does not explicitly disclose wherein the arithmetic portion configured to calculate similarity between the first graph and a second graph based on the second diagram information; and wherein the display portion configured to display the similarity on the terminal.
However, Lu discloses wherein the arithmetic portion configured to calculate similarity between the first graph and a second graph based on the second diagram information; and wherein the display portion configured to display the similarity on the terminal (Par [0024-0026]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Lu into the teaching of Cecchi in order to provide an accurate graph result (par [0007]).
Cecchi and Lu do not explicitly disclose the first circuit diagram information is circuit elements included in a circuit diagram and the circuit diagram; wherein the circuit element comprises at least one of a transistor, a capacitor, a resistor, an inductor, a diode or a light-emitting diode.
However, Kurokawa discloses the first circuit diagram information is circuit elements included in a circuit diagram and the circuit diagram (Par [0081, 0125-0129]
wherein the circuit element comprises at least one of a transistor, a capacitor, a resistor, an inductor, a diode or a light-emitting diode (Par [0022, 0037, 0081]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Kurokawa into the teaching of Cecchi as modified by Lu in order to reduce power consumption (par [0013]).
As per claim 2, Cecchi discloses the search system according to claim 1, further comprising a server connected to the terminal via a network, wherein the database is stored in the server (par 0048]).
As per claim 5, Cecchi discloses a search method comprising the steps of:
inputting first circuit diagram information (Par [0069]),
converting the first circuit diagram information into a first graph (Par [0094]).
Cecchi does not explicitly disclose a first region of terminal; displaying the first graph on a second region of the terminal; calculating similarity between the first graph and a second graph registered in a database; and displaying the similarity on the terminal.
However, Lu discloses inputting information a first region of a terminal; displaying the first graph on a second region of the terminal; calculating similarity between the first graph and a second graph registered in a database; and displaying the similarity and the second circuit diagram that correspond to the similarity on the terminal (Par [0024-0026, 0032, 0038, 0040]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Lu into the teaching of Cecchi in order to provide an accurate graph result (par [0007]).
Cecchi and Lu do not explicitly disclose the first circuit diagram information is circuit elements included in a circuit diagram and the circuit diagram; wherein the circuit element comprises at least one of a transistor, a capacitor, a resistor, an inductor, a diode or a light-emitting diode.
However, Kurokawa discloses the first circuit diagram information is circuit elements included in a circuit diagram and the circuit diagram (Par [0081, 0125-0129]
wherein the circuit element comprises at least one of a transistor, a capacitor, a resistor, an inductor, a diode or a light-emitting diode (Par [0022, 0037, 0081]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Kurokawa into the teaching of Cecchi as modified by Lu in order to reduce power consumption (par [0013]).
As per claim 7, Cecchi discloses the search method according to claim 5, wherein the first circuit diagram information is text describing the circuit diagram (Par [0069]).
As per claim 8, Cecchi discloses the search system according to claim 1, wherein the first graph comprises nodes and edges (Par [0059]).
As per claim 10, Cecchi discloses the search method according to claim 5, wherein the first graph comprises nodes and edges (Par [0059]).
Claim(s) 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cecchi et al, Lu and Kurokawa, and further in view of Agarwal (U.S. Pub No. 2008/0097941 A1).
As per claim 9, Cecchi, Lu and Kurokawa do not explicitly disclose the search system according to claim 1, wherein the first graph is an undirected graph.
However, Agarwal discloses wherein the first graph is an undirected graph (Par [0091]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Agarwal into the teaching of Cecchi as modified by Lu and Kurokawa in order to provide a flexible for a ranking function on a graph data (par [0024]).
As per claim 11, Cecchi, Lu and Kurokawa do not explicitly disclose the search method according to claim 5, wherein the first graph is an undirected graph.
However, Agarwal discloses wherein the first graph is an undirected graph (Par [0091]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the features as disclosed in Agarwal into the teaching of Cecchi as modified by Lu and Kurokawa in order to provide a flexible for a ranking function on a graph data (par [0024]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THU N NGUYEN whose telephone number is (571)270-1765. The examiner can normally be reached Monday to Thursday from 9:30AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Boris Gorney can be reached on 571-270-5626. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
May 18, 2026
/THU N NGUYEN/Examiner, Art Unit 2154
Prosecution Insights