DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed October 29, 2025 has been entered. Applicant' s amendment to claim 14 has overcome the objection set forth in the Non-Final Office Action mailed September 8, 2025, which is hereby withdrawn.
Claims 1-4, 6-14, and 16-20 remain pending in the application.
Response to Arguments
Applicant's arguments filed October 29, 2025 have been fully considered and some of the grounds are persuasive.
Specifically, applicant’s argument that prior art Kwan fails to teach the limitation of the Amended claims 1 and 8 “wherein a lateral edge of the gate, a lateral edge of the gate insulating layer, and a lateral edge of the semiconductor part of the active layer are aligned with each other” is persuasive, and the 35 U.S.C § 102 rejections are hereby withdrawn. However, a new grounds of rejection are made under 35 U.S.C § 103 in combination with the previously cited prior art Morinaga.
In regards to the argument that Morinaga fails to teach the limitations of the amended claims 1, 8 and 20 “wherein the active layer comprises a semiconductor part in electrical contact with the second electrode; wherein the semiconductor part of the active layer comprises a source region or a drain region, wherein a lateral edge of the gate, a lateral edge of the gate insulating layer, and a lateral edge of the semiconductor part of the active layer are aligned with each other”, the argument is not persuasive. The Examiner fails to find enablement for any structural difference between the instant application and Morinaga with regards to this limitation. Morinaga discloses formation of a channel region (12c; Fig 3B; ¶ [0175]) in a semiconductor layer (12; Fig 3B; ¶ [0175]), and having a lateral edge (shared by 12c and 12d; Fig 3B) aligned with a gate insulating layer (13; Fig 3B; ¶ [0174]) and with a gate (GE; Fig 3B; ¶ [0175]). The semiconductor layer further includes a source region (12s; Fig 3B; ¶ [0175]) and a drain region (12d; Fig 3B; ¶ [0175]) on either side of the channel region. Fig 1 of the instant application and supporting paragraphs including ¶ [0037] appear to disclose the same structure (reproduced below), the only difference apparent to the Examiner is the same features of the structure variously being called by different names. No identifiable structural delineation is found between a drain region and a drain electrode in either of the below figures of the structure or in their respective descriptions such as to enable one of ordinary skill to delineate where a drain region ends and a drain electrode begins. Applicant argues that channel region 12 does not comprise source region 12s or drain region 12d, with which the Examiner agrees by definition of a field effect transistor structure having a source, drain and channel. In addition, ”channel region” is not included in the claim language, which renders the argument moot.
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Please see the claim rejections below, which have been updated somewhat for clarity.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-14, 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Morinaga; Junichi (US 2021/0200045; hereinafter Morinaga) in view of (Kwon; Hyuk Soon; US 2017/0294464; hereinafter Kwon).
Regarding claim 1, Morinaga discloses thin-film transistor (TFT) (11; Fig 3B; ¶ [0152,0174]), comprising:
a gate (GE; Fig 3B; ¶ [0174]);
a gate insulating layer (13; Fig 3B; ¶ [0174]) disposed on a side of the gate;
an active layer (12, comprising 12s,12c; Fig 3B; ¶ [0174-175]) disposed on a side of the gate insulating layer away from the gate and disposed opposite to the gate;
a first electrode (SL, made of a metal film; Fig 3B; ¶ [0143-144,0184,0195-197]) disposed on a side of the active layer away from the gate; and
an interlayer insulating layer (15; Fig 3B; ¶ [0174]) disposed between the first electrode and the active layer to insulate the first electrode from the active layer, a first via (CH1; Fig 3B; ¶ [0189]) penetrating the interlayer insulating layer and extending to a surface of the first electrode is defined on the interlayer insulating layer, the active layer is connected to the first electrode by the first via (Fig 3B); and
a second electrode connected (12d; Fig 3B; ¶ [0175]) to the active layer, wherein the second electrode and the active layer are disposed on a same layer;
wherein the active layer comprises a semiconductor part (12s,12c; Fig 3B; ¶ [0174-175]) in electrical contact with the second electrode (Fig 3B; ¶ [0175); wherein the semiconductor part of the active layer comprises a source region (12s; Fig 3B; ¶ [0175]),
wherein a lateral edge of the gate, a lateral edge of the gate insulating layer, and a lateral edge of the semiconductor part of the active layer are aligned with each other (as shown in the annotated Fig 3B below).
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Morinaga implies a thickness of the interlayer insulating layer is greater than a thickness of the gate insulating layer (see ¶ [199-200 and 0205-206]), but the Examiner finds the wording insufficient to conclude a specific disclosure.
In the same field of endeavor, Kwon discloses a thin film transistor, wherein a thickness of an interlayer insulating layer (111; Fig 2A; ¶ [0046]) is greater than a thickness of a gate insulating layer (140; Fig 2A; ¶ [0062-64]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the thicknesses of the interlayer insulating layer and gate insulating layer of Morinaga may have a similar relationship as the corresponding ones of Kwon. One would have been motivated to come to this conclusion, with a reasonable expectation of success due to the similar structure, materials, and endeavors of Kwon and Morinaga, as well as this being a well-known relationship in the art.
Regarding claim 2, Morinaga in view of Kwon discloses the TFT of claim 1, comprising:
an auxiliary electrode (Morinaga; 14; Fig 3B; ¶ [0172]) disposed opposite to the active layer (Morinaga; 12; Fig 3B), wherein the interlayer insulating layer (Morinaga; 15; Fig 3B) is disposed between the auxiliary electrode and the active layer.
Regarding claim 3, Morinaga in view of Kwon discloses the TFT of claim 2, wherein the first electrode (Morinaga; SL; Fig 3B) and the auxiliary electrode (Morinaga; 14; Fig 3B) are disposed on a same layer (Morinaga; source metal layer; Fig 3B; ¶ [0183]), and the active layer is connected to the first electrode by the first via (per claim 1).
Regarding claim 4, Morinaga in view of Kwon discloses the TFT of claim 1, wherein the active layer (Morinaga; 12; Fig 3B) further comprises a first electrode contact part (Morinaga; 12s; Fig 3B; ¶ [0175]), conductivity of the first electrode contact part is less than conductivity of the first electrode (Morinaga; SL is made of metal, as cited in claim 1, versus the semiconductor active layer), and the conductivity of the first electrode contact part is greater than conductivity of the semiconductor part (Morinaga; ¶ [0175]); and
the first electrode contact part is connected to the first electrode by the first via (CH1; as shown in Fig 3B).
Regarding claim 6, Morinaga in view of Kwon discloses the TFT of claim 1, wherein the thickness of the interlayer insulating layer (Kwon; layer 111, 3000Å to 5000Å; Fig 2A; ¶ [0046, 0053]) is greater than or equal to two times the thickness of the gate insulating layer (Kwon; layer 140, 500Å to 1500Å; Fig 2A; ¶ [0062-64]).
Regarding claim 7, Morinaga in view of Kwon discloses the TFT of claim 1, but does not specifically wherein the thickness of the interlayer insulating layer is equal to three times the thickness of the gate insulating layer. However, a thickness ratio disclosed by Kwon ranges from two times to ten times ({3000Å to 5000Å}/{500Å to 1500Å}, per claim 6), which almost entirely overlaps the limitation of claim 7. Absent evidence of criticality or demonstrated difference for the non-overlapping range of greater than two times, but less than three times, the Examiner concludes that the prior art range is disclosed with sufficient specificity to anticipate the claimed range. See MPEP 2131.03.II.
Regarding claim 8, Morinaga discloses a display panel, comprising:
a first electrode (source wiring line SL, made of metal; Fig 3B; ¶ [0143-144,0184,0195-197]) disposed on a first metal layer (source metal film; ¶ [0195]);
an interlayer insulating layer (15; Fig 3B; ¶ [0174]) disposed on the first electrode, wherein a first via (CH1; Fig 3B; ¶ [0189]) penetrating the interlayer insulating layer and extending to a surface of the first electrode is defined on the interlayer insulating layer;
an active layer (12, comprising 12s,12c; Fig 3B; ¶ [0174-175]) disposed on the interlayer insulating layer, wherein the active layer is connected to the first electrode by the first via (Fig 3B);
a second electrode (12d; Fig 3B; ¶ [0175]) connected to the active layer;
a gate insulating layer (13; Fig 3B; ¶ [0174]) disposed on the active layer; and
a gate (GE; Fig 3B; ¶ [0174]) disposed on a second metal layer (gate metal film; ¶ [0205]) disposed on the gate insulating layer, wherein the gate is disposed opposite to the active layer (as shown in Fig 3B);
wherein the active layer comprises a semiconductor part (12s,12c; Fig 3B; ¶ [0174-175]) in electrical contact with the second electrode (Fig 3B; ¶ [0175); wherein the semiconductor part of the active layer comprises a source region (12s; Fig 3B; ¶ [0175]),
wherein a lateral edge of the gate, a lateral edge of the gate insulating layer, and a lateral edge of the semiconductor part of the active layer are aligned with each other (as shown in the annotated Fig 3B below).
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Morinaga implies a thickness of the interlayer insulating layer is greater than a thickness of the gate insulating layer (see ¶ [199-200 and 0205-206]), but the Examiner finds the wording insufficient to conclude a specific disclosure.
In the same field of endeavor, Kwon discloses a display panel, wherein a thickness of an interlayer insulating layer (111; Fig 2A; ¶ [0046]) is greater than a thickness of a gate insulating layer (140; Fig 2A; ¶ [0062-64]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the thicknesses of the interlayer insulating layer and gate insulating layer of Morinaga may have a similar relationship as the corresponding ones of Kwon. One would have been motivated to come to this conclusion, with a reasonable expectation of success due to the similar structure, material, and endeavors of Kwon and Morinaga, as well as this being a well-known relationship in the art.
Regarding claim 9, Morinaga in view of Kwon discloses the display panel of claim 8, comprising:
an auxiliary electrode (Morinaga; 14; Fig 3B; ¶ [0172]) disposed opposite to the active layer (Morinaga; 12; Fig 3B), wherein the interlayer insulating layer (Morinaga; 15; Fig 3B) is disposed between the auxiliary electrode and the active layer.
Regarding claim 10, Morinaga in view of Kwon discloses the display panel of claim 8, wherein the first electrode is a drain and the second electrode is a source; or the first electrode is the source (Morinaga; source wiring SL; Fig 3B; ¶ [0184]) and the second electrode is the drain (Morinaga; drain region 12d; Fig 3B; ¶ [0175,0177]).
Regarding claim 11, Morinaga in view of Kwon discloses the display panel of claim 9, wherein the auxiliary electrode (Morinaga; 14; Fig 3B) is disposed on the first metal layer (Morinaga; source metal film; ¶ [0195]), and the interlayer insulating layer (Morinaga; 15; Fig 3B; ¶ [0174]) covers the first electrode (Morinaga; SL; Fig 3B) and the auxiliary electrode (Morinaga; ¶ [0174,0199; Fig 3B).
Regarding claim 12, Morinaga in view of Kwon discloses the display panel of claim 8, wherein the active layer (Morinaga; 12; Fig 3B) further comprises a first electrode contact part (Morinaga; 12s; Fig 3B; ¶ [0175]), conductivity of the first electrode contact part is less than conductivity of the first electrode (Morinaga; SL is made of metal, as cited in claim 8, versus the semiconductor active layer), and the conductivity of the first electrode contact part is greater than conductivity of the semiconductor part (Morinaga; ¶ [0175]); and
the first electrode contact part is connected to the first electrode by the first via (CH1; as shown in Fig 3B).
Regarding claim 13, Morinaga in view of Kwon discloses the display panel of claim 8, comprising a pixel electrode (Morinaga; PE; Fig 3B; ¶ [0177]), wherein the pixel electrode and the active layer (Morinaga; 12; Fig 3B) are disposed on a same layer, the pixel electrode is electrically connected to the active layer (Morinaga; through the second electrode 12d; Fig 3B; ¶ [0177]), and the active layer comprises a metal oxide semiconductor (Morinaga; ¶ [0293]).
Regarding claim 14, Morinaga in view of Kwon discloses the display panel of claim 13, comprising:
a substrate (Morinaga; 10; Fig 3B; ¶ [0170]), wherein the first metal layer (Morinaga; comprising SL(m),14,TL(m); Fig 3B) is disposed on the substrate and comprises a plurality of data lines (Morinaga; SL(m); Fig 3B; ¶ [0155);
a plurality of scan lines (Morinaga; GL2(n); Fig 3B; ¶ [0156]) disposed on the second metal layer (GE,GL2(n); Fig3B), wherein the scan lines cross the data lines to define a plurality of sub-pixel units (Morinaga; PIX; Figs 2A,3A; ¶ [0151-0152]), and a thin-film transistor (TFT) (11; Fig 4A) composed of the first electrode, the second electrode, the gate, and the active layer and the pixel electrode connected to the TFT are disposed in the sub-pixel units (Morinaga; Figs 3A-3B,4A-4B; ¶ [0169-170]);
a passivation layer (Morinaga; 16; Fig 3B; ¶ [0180]) disposed on the second metal layer and covering the gate and the pixel electrode; and
a common electrode (Morinaga; CE; Fig 3B; ¶ [0170]) disposed on the passivation layer and disposed opposite to the pixel electrode.
Regarding claim 16, Morinaga in view of Kwon discloses the display panel of claim 8, wherein the thickness of the interlayer insulating layer (Kwon; layer 111, 3000Å to 5000Å; Fig 2A; ¶ [0046, 0053]) is greater than or equal to two times the thickness of the gate insulating layer (Kwon; layer 140, 500Å to 1500Å; Fig 2A; ¶ [0062-64]).
Regarding claim 17, Morinaga in view of Kwon discloses the display panel of claim 16, but does not specifically wherein the thickness of the interlayer insulating layer is equal to three times the thickness of the gate insulating layer. However, a thickness ratio disclosed by Kwon ranges from two times to ten times ({3000Å to 5000Å}/{500Å to 1500Å}, per claim 16), which almost entirely overlaps the limitation of claim 17. Absent evidence of criticality or demonstrated difference for the non-overlapping range of greater than two times, but less than three times, the Examiner concludes that the prior art range is disclosed with sufficient specificity to anticipate the claimed range. See MPEP 2131.03.II.
Regarding claim 19, Morinaga in view of Kwon discloses the display panel of claim 8, comprising a second touch control electrode (Morinaga; another electrode; ¶ [0146]), wherein the second touch control electrode is insulated from the first touch control electrode and is disposed opposite to the first touch control electrode (Morinaga; the mutual capacitive touch sensor, for example with liquid crystal layer therebetween; ¶ [0146].)
Regarding claim 20, Morinaga discloses a method of manufacturing the display panel, comprising following steps:
providing a substrate (10; Fig 6A; ¶ [0195]);
forming a first metal layer (source metal film; ¶ [0195]) on the substrate, and patterning the first metal layer to form a first electrode (SL; Fig 6A; ¶ [0195]);
disposing an interlayer insulating layer (15; Fig 6B; ¶ [0199]) on the first metal layer, and patterning the interlayer insulating layer to form a first via (CH1; Fig 7C; ¶ [0213]);
disposing a patterned active layer (12’; Fig 6C; ¶ [0201-203]) on the interlayer insulating layer, wherein the active layer is connected to the first electrode by the first via (Fig 7C), and the active layer comprises a metal oxide semiconductor (¶ [0293]);
forming a gate insulating layer (13; Fig 6D; ¶ [0205]) and a second metal layer (gate metal film; ¶ [0205]) on the active layer;
patterning the second metal layer to form a gate (GE; Fig 6D; ¶ [0205]), wherein the gate and the active layer are disposed opposite to each other;
using the patterned gate as a mask plate to pattern the gate insulating layer to expose the active layer disposed on the first electrode (¶ [0205]); and
using the patterned gate as the mask plate to metalize the exposed active layer (a portion of 12’ is made conductive; Fig 7A; ¶ [0209]) to form a first electrode contact part (12s; Fig 7A; ¶ [0209]) and a second electrode (12d; Fig 7A; ¶ [0209]) which is connected to the active layer, wherein the first electrode contact part is connected to the first electrode by the first via (Figs 7C-7D);
wherein the active layer comprises a semiconductor part (12s,12c; Fig 3B; ¶ [0174-175]) in electrical contact with the second electrode (Fig 3B; ¶ [0175); wherein the semiconductor part of the active layer comprises a source region (12s; Fig 3B; ¶ [0175]),
wherein a lateral edge of the gate, a lateral edge of the gate insulating layer, and a lateral edge of the semiconductor part of the active layer are aligned with each other (as shown in the annotated Fig 3B below).
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Morinaga implies a thickness of the interlayer insulating layer is greater than a thickness of the gate insulating layer (see ¶ [199-200 and 0205-206]), but does not disclose a thickness of the interlayer insulating layer is greater than or equal to two times a thickness of the gate insulating layer.
In the same field of endeavor, Kwon discloses a similar display panel, wherein a thickness of an interlayer insulating layer (111, 3000Å to 5000Å; Fig 2A; ¶ [0046, 0053]) is greater than or equal to two times a thickness of a gate insulating layer (140, 500Å to 1500Å; Fig 2A; ¶ [0062-64]). Accordingly, it would have been obvious to a person having ordinary skill in the art that a thickness of the interlayer insulating layer of Moringa may be greater than or equal to two times a thickness of the gate insulating layer of Moringa. One would have been motivated to come to this conclusion because Moringa is silent in regards to this thickness relationship, and it is well known in the art that an interlayer insulating layer is typically has a thickness at least two times greater than a gate insulating layer. One would have had a reasonable expectation of success because of the similar structures and materials of Kwon and Morinaga.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Morinaga; Junichi (US 2021/0200045; hereinafter Morinaga) in view of (Kwon; Hyuk Soon; US 2017/0294464; hereinafter Kwon), and further in view of Noh; SoYoung et al. (US 2019/0006521; hereinafter Noh).
Regarding claim 18, Morinaga in view of Kwon discloses the display panel of claim 8, wherein the first metal layer (Morinaga; comprising SL(m),14,TL(m); Fig 3B) comprises a touch control signal line (Morinaga; TL(m); Fig 3B; ¶ [0143]); and the display panel comprises: a first touch control electrode (Morinaga; TX; Fig 3B; ¶ [0143]),
Morinaga in view of Kwon does not disclose wherein the first touch control electrode and the active layer are disposed on a same layer, and the first touch control electrode is connected to the active layer.
In the same field of endeavor, Noh discloses a display device comprising a first touch control electrode (161; Fig 3; ¶ [0073]) and an active layer (121; Fig 3; ¶ [0073]) disposed on a same layer, and the first touch control electrode is connected to the active layer (at least, physically connected by layer 117; ¶ [0073]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the disclosure of Noh with that of Morinaga in view of Kwon to include the first touch control electrode disposed on a same layer as the active layer. One would have been motivated to do this in order to include a mutual capacitive touch sensor (disclosed by Morinaga; ¶ [0146]) without increasing the thickness of the display and without adding an additional insulating layer (Noh; ¶ [0075]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang; Wenlin et al. (US 2016/0334909; the prior art discloses a display device comprising a touch electrode and an active layer disposed on the same layer).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817