DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 11/18/2025 has been entered. Claim 1 has been amended, claims 24-25 have been newly added, and claims 14-15 and 19-21 have been canceled. Applicant’s amendments to the claims are noted.
Therefore, claims 1-13, 16-18, and 22-25 remain pending in the application.
Response to Arguments
Applicant's arguments filed on 11/18/2025 have been fully considered but they are not persuasive. Regarding the arguments on pages 13-16, Kim (US 20200111390 A1) teaches a surface of the conductive connecting part proximal to the base substrate is entirely in direct contact with the base substrate (connecting line 180 disposed between the individual substrates 111 and the lower substrate 110, the connecting line being in direct contact with the lower substrate and having a uniform height from the lower substrate for its entire length without a step, and electrically coupled to a pad through a contact hole CT formed in an insulating layer 114, Para [0049] and Fig. 3).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13, 16-18, and 22-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites "the display unit comprises a first insulating part and a conductive part" and "the conductive connecting part" as a component of "the connection unit." However, claim 1 further recites that the conductive connecting part "extends ... to an area of the base substrate where the display unit is located." Since the conductive connecting part is located within the area of the display unit, it is unclear whether the conductive connecting part should be regarded as a component of the display unit or as a component belonging solely to the connection unit.
Claim 24 recites “orthographic projections of the hollowed-out patterns on the first sub-layer are at least partially overlapped.” It is unclear which elements are overlapped with one another, as the claim fails to identify the objects of the recited overlapping relationship.
Claims 2-13, 16-18, and 22-25 are also rejected being dependent on rejected claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 12-13, 17, and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 10964769 B2), and further in view of Kim (US 20200111390 A1).
Regarding claim 1, Park teaches a display substrate (stretchable display device 1000, Fig. 3), comprising a base substrate (stretchable substrate SS), and a display unit (display unit DP at island area IA), a connection unit (wiring part WP at hinge area HA) and a hollowed-out unit disposed on the base substrate (penetration area PA enclosed by the island area IA and the hinge area HA where the stretchable substrate SS is depressed or penetrated, Fig. 1), wherein the display unit, the connection unit and the hollowed-out unit are adjacent to each other (the island area IA, the hinge area HA, and the penetration area PA are adjacent to one another, Fig. 1);
the display unit comprises a first insulating part (inorganic insulating layer CIL including buffer layer BL, gate insulating layer GL, and data insulating layer DL on the island area IA) and a conductive part (thin film transistor TFT including active layer AL, gate electrode GE, source electrode SE, and drain electrode DE); the connection unit comprises a second insulating part (organic insulating layer OIL including via insulating layer VL) and a conductive connecting part (wiring part WP located at the hinge area HA), the second insulating part is arranged on a side of the conductive connecting part away from the base substrate (the via insulating layer VL of the organic insulating layer OIL is disposed on the wiring part WP on a side thereof away from the stretchable substrate SS, Fig. 3);
a surface of the conductive connecting part proximal to the base substrate is in direct contact with the base substrate (the opening OP overlapping the hinge area HA penetrates the data insulating layer DL, the gate insulating layer GL, and the buffer layer BL and exposes the surface of the hinge area HA, and the wiring part WP overlapping the opening OP is in direct contact with the stretchable substrate SS, Fig. 3), the conductive connecting part extends from an area of the base substrate where the connection unit is located to an area of the base substrate where the display unit is located (the wiring part WP connects the display units DP disposed on the adjacent island areas IA through the hinge area HA, extending from one island area IA to another island area IA, Fig. 3), and is electrically coupled to the conductive part through a via hole formed in the first insulating part (the wiring part WP includes a first line LI1 overlapping the island area IA and a second line LI2 bridge-connected to the first line LI1 through a contact hole of the data insulating layer DL, and is electrically connected to the thin film transistor TFT, Fig. 3);
the second insulating part has a tensile property superior to that of the first insulating part (the inorganic insulating layer CIL has brittleness, whereas the organic insulating layer OIL comprises an organic material such as polyimide, phenylene, or siloxane that deforms corresponding to the stress applied to the hinge area HA such that the stress is dispersed, col. 4 and col. 7).
But Park does not explicitly teach a surface of the conductive connecting part proximal to the base substrate is entirely in direct contact with the base substrate.
However, Kim teaches a surface of the conductive connecting part proximal to the base substrate is entirely in direct contact with the base substrate (connecting line 180 disposed between the individual substrates 111 and the lower substrate 110, the connecting line being in direct contact with the lower substrate and having a uniform height from the lower substrate for its entire length without a step, and electrically coupled to a pad through a contact hole CT formed in an insulating layer 114, Para [0049] and Fig. 3).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify the conductive connecting part of Park to be entirely in direct contact with the base substrate along its full extent, as taught by Kim, to reduce damage to the conductive connecting part caused by a step and thereby improve reliability of the stretchable display device (Para [0132] in Kim; KSR).
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Regarding claim 2, Park in view of Kim teaches the display substrate according to claim 1, wherein the conductive part comprises a driving circuit and a light emitting element disposed on a side of the driving circuit away from the base substrate; the driving circuit is electrically coupled to the light emitting element for driving the light emitting element to emit light (the thin film transistor TFT disposed on the island area IA, and the organic light emitting element OLED including a first electrode E1 connected to the thin film transistor TFT, an organic emission layer OL, and a second electrode E2 sequentially stacked, the OLED being driven by the TFT, Figs. 2-3);
the conductive connecting part comprises at least one of a data line, a scan line, a power supply line and a control signal line (the wiring part WP includes a data line DA, a first scan line Sn, a second scan line S(n-1), a third scan line S(n-2), a driving power line ELVDDL, and a light emission control line EM, Fig. 2);
the data line, the scan line, the power supply line and the control signal line are respectively electrically coupled to the driving circuit (the data line DA, the scan lines Sn/S(n-1)/S(n-2), the driving power line ELVDDL, and the light emission control line EM are connected to the respective gate/source electrodes of the thin film transistors T1-T7, Fig. 2);
the data line is configured to provide a data signal for driving the light emitting element to emit light (the data line DA transmits a data signal to the second source electrode S2 of the second thin film transistor T2, Fig. 2);
the scan line is configured to provide a scan signal for driving the light emitting element to emit light (the first scan line Sn transmits a first scan signal to the second and third gate electrodes G2/G3, Fig. 2);
the power supply line is configured to provide a power supply signal for driving the light emitting element to emit light (the driving power line ELVDDL supplies a driving power to the fifth source electrode S5, Fig. 2);
the control signal line is configured to provide a control signal for driving the light emitting element to emit light (the light emission control line EM transmits a light emission control signal to the fifth and sixth gate electrodes G5/G6, Fig. 2).
Regarding claim 12, Park in view of Kim teaches the display substrate according to claim 1, wherein a surface of the first insulating part on a side thereof away from the base substrate is substantially flush with a surface of the second insulating part on a side thereof away from the base substrate (the via insulating layer VL of the organic insulating layer OIL covering the opening OP at the hinge area is substantially coplanar with the organic insulating layer OIL over the island area, Fig. 3).
Regarding claim 13, Park in view of Kim teaches the display substrate according to claim 12, wherein the first insulating part is adjacent to the second insulating part, and an acute included angle between an adjacent surface of the first insulating part and the second insulating part and the base substrate is greater than or equal to 45° and less than 90° (the sidewall of the opening OP penetrating the buffer layer BL, the gate insulating layer GL, and the data insulating layer DL forms an inclined surface with the stretchable substrate SS at the boundary between the island area and the hinge area, the angle being an acute included angle, Fig. 3).
Regarding claim 17, Park in view of Kim teaches the display substrate according to claim 1, wherein the conductive connecting part is made of any one of Ti, Al, Mo, Ag, ITO, IZO, ZnO, In2O3, IGO, AZO, rubber mixed with conductive particles, and carbon nanotubes (the wiring part WP is disposed on the same layer as and includes the same material as the source electrode SE and the drain electrode DE, or the gate electrode GE, which comprise a conductive metal; Kim further teaches the connecting line 180 comprising a base polymer mixed with conductive particles, Para [0061]).
Regarding claim 22, Park in view of Kim teaches a display panel, comprising the display substrate according to claim 1 (the stretchable display device 1000 constitutes a display panel, Fig. 3).
Regarding claim 23, Park in view of Kim teaches a display device, comprising the display panel according to claim 22 (the stretchable display device 1000, Fig. 1).
Claim 3 is rejected under 35 U.S.C. § 103 as being unpatentable over Park (US 10964769 B2) in view of Kim (US 20200111390 A1) as applied to claim 2 above, and further in view of Shin (US 9224972 B2).
Regarding claim 3, Park in view of Kim teaches the display substrate according to claim 2, wherein the driving circuit comprises a driving transistor comprising a first gate electrode, an active layer, a source electrode, and a drain electrode (the thin film transistor TFT including a gate electrode GE, an active layer AL, a source electrode SE, and a drain electrode DE, Fig. 3 in Park); orthographic projections of the source electrode and the drain electrode on the base substrate are respectively positioned at two opposite ends of the orthographic projection of the active layer on the base substrate (Fig. 3 in Park); the light emitting element is arranged on a side of the planarization layer away from the base substrate, and comprises a first electrode, a light emitting functional layer and a second electrode which are sequentially stacked (the first electrode E1, the organic emission layer OL, and the second electrode E2 sequentially stacked, Fig. 3 in Park); the drain electrode is electrically coupled to the first electrode through a via hole formed in the planarization layer (the first electrode E1 connected to the drain electrode DE through a contact hole of the via insulating layer VL, Fig. 3 in Park).
But Park does not explicitly teach a second gate electrode; orthographic projections of the first gate electrode and the second gate electrode on the base substrate respectively fall into an orthographic projection of the active layer on the base substrate; the first insulating part comprises a first insulating layer, a buffer layer, a first gate insulating layer, a second gate insulating layer, an intermediate dielectric layer and a planarization layer which are sequentially stacked in a direction away from the base substrate; the active layer is positioned between the buffer layer and the first gate insulating layer; the first gate electrode is positioned between the first gate insulating layer and the second gate insulating layer; the second gate electrode is positioned between the second gate insulating layer and the intermediate dielectric layer; the source electrode and the drain electrode are located between the intermediate dielectric layer and the planarization layer.
However, Shin teaches a driving transistor comprising a first gate electrode and a second gate electrode, orthographic projections of which on the base substrate respectively fall into an orthographic projection of the active layer (the first gate electrode 25 and the second gate electrode 26 each overlapping the channel region of the active layer, Fig. 8); the active layer is positioned between the buffer layer and the first gate insulating layer (Fig. 8); the first gate electrode is positioned between the first gate insulating layer and the second gate insulating layer (the first gate electrode 25 on the first gate insulating layer 141 and below the second gate insulating layer 142, Fig. 8); the second gate electrode is positioned between the second gate insulating layer and the intermediate dielectric layer (the second gate electrode 26 on the second gate insulating layer 142 and below the interlayer insulating layer, Fig. 8); the source electrode and the drain electrode are located between the intermediate dielectric layer and the planarization layer (the source electrode 176 and the drain electrode 177 on the interlayer insulating layer, Fig. 8).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to form the driving transistor of Park with the first and second gate electrodes vertically stacked over the active layer through the first and second gate insulating layers as taught by Shin, to improve the driving characteristics and stability of the thin film transistor (Shin; KSR).
Claims 4-11 and 18 are rejected under 35 U.S.C. § 103 as being unpatentable over Park (US 10964769 B2) in view of Kim (US 20200111390 A1) and of Shin (US 9224972 B2), and further in view of Cho (US 20210005693 A1).
Regarding claim 4, the combination teaches the display substrate according to claim 3, wherein the conductive connecting part extending from the area where the connection unit is located to the area where the display unit is located is located between the first insulating layer and the base substrate (the connecting line 180 disposed between the individual substrate 111 and the lower substrate 110, Para [0049] and Fig. 3 in Kim).
But Park in view of Kim and Shin does not explicitly teach the second insulating part comprises a second insulating layer, and the second insulating layer and the planarization layer are made of a same material.
However, Cho teaches the second insulating part comprises a second insulating layer, and the second insulating layer and the planarization layer are made of a same material (the first planarization layer 117 in the non-display area and in the display area formed of a same organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, Fig. 1 in Cho).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to form the second insulating layer and the planarization layer of the device of Park from a same material as taught by Cho, to simplify the manufacturing process and improve reliability of the display apparatus (Cho; KSR).
Regarding claim 5, the combination teaches the display substrate according to claim 4, wherein the driving circuit further comprises a third electrode disposed between the intermediate dielectric layer and the planarization layer, and the third electrode is electrically coupled to the drain electrode (the data pad 173 disposed between the intermediate dielectric layer and the planarization layer and electrically connected to the drain electrode 154, Para [0075] and Fig. 3 in Kim); the conductive connecting part comprises the data line, and the data line extending from the area where the connection unit is located to the area where the display unit is located is electrically coupled to the third electrode through via holes formed in the first insulating layer, the buffer layer, the first gate insulating layer, the second gate insulating layer and the intermediate dielectric layer (the connecting line 180 functioning as the data line electrically coupled to the data pad 173 through contact holes in the stacked insulating layers, Para [0075] and Fig. 3 in Kim).
Regarding claim 6, the combination teaches the display substrate according to claim 4, wherein the driving circuit further comprises a third electrode and a fourth electrode, the third electrode is disposed between the intermediate dielectric layer and the planarization layer, and the third electrode is electrically coupled to the drain electrode (the data pad 173 electrically connected to the drain electrode 154, Fig. 3 in Kim); the fourth electrode is arranged between the first gate insulating layer and the second gate insulating layer, and the fourth electrode and the first gate electrode are made of a same material (the gate pad 171 disposed on the same layer as and made of the same material as the gate electrode 151, Para [0074] in Kim); the conductive connecting part comprises the data line, the data line is electrically coupled to the fourth electrode through via holes in the first insulating layer, the buffer layer and the first gate insulating layer, and the fourth electrode is electrically coupled to the third electrode through via holes in the second gate insulating layer and the intermediate dielectric layer (the connecting line 180 coupled to the gate pad 171, and the gate pad 171 coupled to the data pad 173, through the respective contact holes, Para [0074]-[0075] and Fig. 3 in Kim).
Regarding claim 7, the combination teaches the display substrate according to claim 4, wherein the driving circuit further comprises a third electrode and a fourth electrode, the third electrode is disposed between the intermediate dielectric layer and the planarization layer, and the third electrode is electrically coupled to the drain electrode (the data pad 173 electrically connected to the drain electrode 154, Fig. 3 in Kim); the fourth electrode is arranged between the second gate insulating layer and the intermediate dielectric layer, and the fourth electrode and the second gate electrode are made of a same material (the gate pad of Kim disposed on the same layer and of the same material as a gate electrode, Para [0074] in Kim, corresponding to the second gate electrode 26 layer of Shin, Fig. 8 in Shin); the conductive connecting part comprises the data line, the data line is electrically coupled to the fourth electrode through via holes in the first insulating layer, the buffer layer, the first gate insulating layer and the second gate insulating layer, and the fourth electrode is electrically coupled to the third electrode through a via hole in the intermediate dielectric layer (Para [0074]-[0075] and Fig. 3 in Kim).
Regarding claim 8, the combination teaches the display substrate according to claim 4, wherein the driving circuit further comprises a third electrode, a fourth electrode and a fifth electrode, the third electrode is disposed between the intermediate dielectric layer and the planarization layer, and the third electrode is electrically coupled to the drain electrode (the data pad 173 electrically connected to the drain electrode 154, Fig. 3 in Kim); the fourth electrode is arranged between the second gate insulating layer and the intermediate dielectric layer, and the fourth electrode and the second gate electrode are made of a same material (the gate pad of Kim corresponding to the second gate electrode 26 layer of Shin, Para [0074] in Kim; Fig. 8 in Shin); the fifth electrode is arranged between the first gate insulating layer and the second gate insulating layer, and the fifth electrode and the first gate electrode are made of a same material (the first capacitor electrode 141 disposed on the same layer as and made of the same material as the first gate electrode, Fig. 1 in Cho); the conductive connecting part comprises the data line, and the data line is electrically coupled to the fourth electrode through via holes in the first insulating layer, the buffer layer, the first gate insulating layer and the second gate insulating layer, the fourth electrode is electrically coupled to the third electrode through a via hole in the intermediate dielectric layer (Para [0074]-[0075] and Fig. 3 in Kim); the data line is electrically coupled to the fifth electrode through via holes in the first insulating layer, the buffer layer and the first gate insulating layer, and the fifth electrode is electrically coupled to the third electrode through via holes in the second gate insulating layer and the intermediate dielectric layer (the connecting line 180 coupled to the first capacitor electrode 141, and the first capacitor electrode 141 coupled to the data pad 173, Fig. 1 in Cho and Fig. 3 in Kim).
Regarding claim 9, the combination teaches the display substrate according to claim 5, wherein the driving circuit further comprises a sixth electrode disposed between the first gate insulating layer and the second gate insulating layer, and the sixth electrode and the first gate electrode are made of a same material and electrically connected (the gate pad 171 disposed on the same layer as and made of the same material as the gate electrode 151, Para [0074] in Kim); the conductive connecting part further comprises the scan line which comprises a first scan line, and the first scan line is electrically coupled to the sixth electrode through via holes formed in the first insulating layer, the buffer layer and the first gate insulating layer (the connecting line 180 functioning as a first scan line electrically coupled to the gate pad 171, Para [0074]-[0075] and Fig. 3 in Kim).
Regarding claim 10, the combination teaches the display substrate according to claim 9, wherein the driving circuit further comprises a seventh electrode disposed between the second gate insulating layer and the intermediate dielectric layer, and the seventh electrode and the second gate electrode are made of a same material and electrically connected (the second gate electrode 26 of Shin disposed between the second gate insulating layer 142 and the interlayer insulating layer, made of a gate material and electrically connected through a gate contact hole, Fig. 8 in Shin); the scan line further comprises a second scan line, and the second scan line is electrically coupled to the seventh electrode through via holes formed in the first insulating layer, the buffer layer, the first gate insulating layer and the second gate insulating layer (the connecting line 180 functioning as a second scan line electrically coupled to the seventh electrode through contact holes, Para [0074]-[0075] and Fig. 3 in Kim; Fig. 8 in Shin).
Regarding claim 11, the combination teaches the display substrate according to claim 4, wherein the first insulating part further comprises a pixel defining layer and a protective layer disposed on a side of the planarization layer away from the base substrate and stacked sequentially in a direction away from the base substrate (the pixel defining layer and the inorganic encapsulating layer stacked sequentially on the planarization layer, Fig. 3 in Park; the bank 180 and the encapsulating element 220 on the first planarization layer 117, Fig. 1 in Cho); the pixel defining layer is configured to define an arrangement position of the light emitting element (the bank 180 defines an emission region, Fig. 1 in Cho); the second insulating part further comprises a third insulating layer arranged on a side of the second insulating layer away from the base substrate, and the third insulating layer and the protective layer are made of a same material (the inorganic encapsulating layer in the connection area made of a same inorganic material such as silicon nitride or silicon oxide as the protective layer in the display area, Para [0096] in Cho).
Regarding claim 18, the combination teaches the display substrate according to claim 4, wherein the second insulating layer is made of any one of a general-purpose polymer of polymethylmethacrylate and polystyrene, a phenol group-based polymer derivative, an acryl-based polymer, a p-xylene-based polymer, an arylene ether-based polymer, an amide-based polymer, a fluoride-based polymer, and a vinyl alcohol-based polymer, or a mixture of two or more thereof (the organic insulating layer made of an acryl-based resin or a polyimide, Park; the first planarization layer 117 formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, Fig. 1 in Cho).
Claim 16 is rejected under 35 U.S.C. § 103 as being unpatentable over Park (US 10964769 B2) in view of Kim (US 20200111390 A1) as applied to claim 1 above, and further in view of Cho (US 20210005693 A1).
Regarding claim 16, Park in view of Kim teaches the display substrate according to claim 1.
But Park in view of Kim does not explicitly teach that in the display unit, an orthographic projection of the intermediate dielectric layer on the base substrate covers an entire area where the display unit is located; a part of an orthographic projection of the planarization layer on the base substrate is not overlapped with the orthographic projection of the intermediate dielectric layer on the base substrate, a plurality of grooves are formed in the intermediate dielectric layer at a side thereof away from the base substrate, and the grooves are located in an area of the intermediate dielectric layer, an orthographic projection of which on the base substrate is not overlapped with the orthographic projection of the planarization layer on the base substrate; parts of the protective layer and the encapsulation layer corresponding to the grooves are embedded in the grooves.
However, Cho teaches that in the display unit, an orthographic projection of the intermediate dielectric layer on the base substrate covers an entire area where the display unit is located (the second interlayer insulating layer 116 covers the entire display area, Fig. 1 in Cho); a part of an orthographic projection of the planarization layer on the base substrate is not overlapped with the orthographic projection of the intermediate dielectric layer on the base substrate, a plurality of grooves are formed in the intermediate dielectric layer at a side thereof away from the base substrate, and the grooves are located in an area of the intermediate dielectric layer, an orthographic projection of which on the base substrate is not overlapped with the orthographic projection of the planarization layer on the base substrate (recesses formed in the second interlayer insulating layer 116 at a side away from the substrate in an area not overlapped with the first planarization layer 117, Fig. 1 in Cho); parts of the protective layer and the encapsulation layer corresponding to the grooves are embedded in the grooves (portions of the encapsulating element 220 embedded in the recesses, Fig. 1 in Cho).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to form the grooves in the intermediate dielectric layer with the protective layer and the encapsulation layer embedded therein as taught by Cho, to provide a more stable and reliable encapsulation for the display unit (Cho; KSR).
Claim 24 is rejected under 35 U.S.C. § 103 as being unpatentable over Park (US 10964769 B2) in view of Kim (US 20200111390 A1) as applied to claim 1 above, and further in view of Hong (US 20180052493 A1).
Regarding claim 24, Park in view of Kim teaches the display substrate according to claim 1, wherein a plurality of display units are disposed on the base substrate and are arranged in an array, and the connection unit is configured to connect adjacent ones of the display units along a row direction and a column direction of the array (a plurality of display units DP arranged in an array, the wiring part WP connecting adjacent display units along row and column directions, Fig. 1 in Park); the hollowed-out unit is arranged between the display unit and the connection unit (the penetration area PA arranged between the island area IA and the hinge area HA, Fig. 1 in Park).
But Park in view of Kim does not explicitly teach the base substrate comprises a first sub-layer and a second sub-layer stacked on each other, the second sub-layer is closer to the display unit and the connection unit than the first sub-layer; the hollowed-out unit comprises hollowed-out patterns arranged in the second sub-layer and in film layers on the second sub-layer, orthographic projections of the hollowed-out patterns in the second sub-layer and in film layers on the second sub-layer on the first sub-layer are at least partially overlapped.
However, Hong teaches the base substrate comprises a first sub-layer (carrier substrate 140) and a second sub-layer (substrate 120) stacked on each other, the second sub-layer is closer to the display unit and the connection unit than the first sub-layer (Para [0085] and Fig. 11 in Hong); the hollowed-out unit comprises hollowed-out patterns arranged in the second sub-layer and in film layers on the second sub-layer, orthographic projections of the hollowed-out patterns in the second sub-layer and in film layers on the second sub-layer on the first sub-layer are at least partially overlapped (the openings 116 extending through the insulating layers 130 and the substrate 120 such that the carrier substrate 140 may be exposed, Para [0086]-[0087] and Fig. 11 in Hong).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the sub-layered base substrate and the hollowed-out patterns of Hong into the device of Park in view of Kim, to optimize the structure size (Para [0078] in Hong; KSR).
Claim 25 is rejected under 35 U.S.C. § 103 as being unpatentable over Park (US 10964769 B2) in view of Kim (US 20200111390 A1) and Hong (US 20180052493 A1) as applied to claim 24 above, and further in view of Cho (US 20210005693 A1).
Regarding claim 25, Park in view of Kim and Hong teaches the display substrate according to claim 24, further comprising an encapsulation layer disposed on a side of the display unit and the connection unit away from the base substrate, wherein the encapsulation layer encapsulates the display unit and the connection unit (the encapsulation layer encapsulating the display unit and the connection unit, Fig. 3 in Park); a part of the encapsulation layer, which forms encapsulation for the display unit, is a first part, and a part of the encapsulation layer, which forms encapsulation for the connection unit, is a second part (Fig. 3 in Park).
But Park in view of Kim and Hong does not explicitly teach the first part has a thickness greater than that of the second part.
However, Cho teaches the first part has a thickness greater than that of the second part (the second organic encapsulating layer 220b in the display area DA having a greater thickness than that in the non-display area NDA, Para [0096] and Fig. 8 in Cho).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to form the encapsulation layer of Park with a greater thickness over the display unit than over the connection unit as taught by Cho, to enhance encapsulation of the light emitting element while relieving tensile stress at the connection unit (Cho; KSR).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897
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