Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 6-8 and 16-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6-8 and 16-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are: the second-fifth via holes. Specifically, the claims in question each disclose the formation of a first via hole, a fifth via hole, and/or a sixth via hole, but fail to mention the formation of any second-fourth via holes. For the sake of further analysis, the terms “fifth via hole” will be interpreted as a second via hole, while the “sixth via hole” will be interpreted as a second via hole for claims 7 and 17 but considered a third via hole for claims 8 and 18.
Additionally, claims 6, 8, 16, and 18 list a number of other elements that require the existence of other elements that appear to have been omitted. Specifically, the terms “second buffer layer”, “second semiconductor layer”, “sixth interlayer insulating layer”, “seventh interlayer insulating layer”, “third gate”, and “fourth gate” imply the existence of multiple other elements that appear to have been omitted.
Claim Rejections - 35 USC § 102
Claim(s) 1-2 and 9-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sun (US Patent No. 12588375).
Regarding claim 1, Sun teaches a spliced display panel, comprising: a display area; and a non-display area on a side of the display area (Fig. 20 points to a display device comprising a plurality of display modules 002 and a non-display area between the display modules 002 adjacent to each other that is mainly formed by a seam A.), wherein the spliced display panel further comprises: a plurality of display components in the display area, wherein each of the display components comprises a plurality of first connection terminals and a display substrate electrically connected to the first connection terminals (Fig. 2 points to a display module 002 (display component) comprising bottom electrodes 203 (first connection terminals) and a flexible substrate 201.); a driving backplane comprising a connecting circuit layer in the display area, wherein the connecting circuit layer comprises a plurality of second connection terminals bound to the plurality of first connection terminals, and a plurality of the display components are arranged in an array on the driving backplane (Figs. 2 and 23 point to a connection structure 003 and connection electrodes 101 (second connection terminals).); and a driving integrated circuit electrically connected to the plurality of second connection terminals; wherein the driving integrated circuit sequentially transmits signals to the plurality of first connection terminals and the display substrate through the plurality of second connection terminals to drive the display substrate to emit light (Fig. 2 and Col. 11, lines 64-67 point to a driving chip IC.).
Regarding claim 2, Sun teaches wherein the driving backplane further comprises a substrate layer, and the connecting circuit layer and the driving integrated circuit are disposed on the substrate layer (Fig. 2 points to a substrate 102.).
Regarding claim 9, Sun teaches wherein the connecting circuit layer further comprises a sealing layer, and the sealing layer is disposed between the display component and the driving backplane and covers the first connection terminal and the second connection terminal (Col. 11, lines 19-22 point to the connection structure 003 (connecting circuit layer) which may be formed by an anisotropic conductive adhesive (sealing layer).).
Regarding claim 10, Sun teaches wherein the connecting circuit layer further comprises a sealing layer, and the sealing layer is disposed between the display component and the driving backplane and covers the first connection terminal and the second connection terminal (Col. 11, lines 19-22 point to the connection structure 003 (connecting circuit layer) which may be formed by an anisotropic conductive adhesive (sealing layer).).
Claim Rejections - 35 USC § 103
Claim(s) 3-5, 7, 11-15, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sun (US Patent No. 12588375).
Regarding claim 3, Sun teaches wherein the connecting circuit layer further comprises a connection trace, a first interlayer insulating layer, and a second interlayer insulating layer in the display area (Fig. 2 points to a connection electrode 103 (connection trace), a protective film 104 (first interlayer insulating layer), and at least one of an anisotropic conductive adhesive, a conductive silver paste, an alloy formed by eutectic bonding, or the like (second interlayer insulating layer) which is used to form the connection structure 003.), the first interlayer insulating layer is disposed on the substrate layer, the connection trace is disposed on the first interlayer insulating layer, the second interlayer insulating layer is disposed on the connection trace (The court has held that the mere rearrangement of parts is an obvious matter of design choice with no patentable significance unless it would modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975).). Thus it is considered obvious that one of ordinary skill in the art would rearrange the previously mentioned components in order to reduce the critical dimensions of the overall structure and/or improve signal transmission to/from the driving chip IC, resulting in a connection structure 003 (connecting circuit layer) on the substrate 102 comprising the protective film 104 (first interlayer insulating layer), the connection electrode 103 (connection trace), and the material (second interlayer insulating layer) previously used to form the connection structure 003.), the second connection terminal is electrically connected to the connection trace and the first connection terminal through a first via hole penetrating the second interlayer insulating layer (Fig. 2 points to the connection electrodes 101 (second connection terminal) and 103 (connection trace) being connected by a via hole O7.), the driving integrated circuit in the non-display area is electrically connected to the connection trace, and orthographic projections of the driving integrated circuit and the connection trace projected on the substrate layer do not overlap each other (Id. points to the driving chip IC. The court has held that the mere rearrangement of parts is an obvious matter of design choice with no patentable significance unless it would modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975).). Thus, it is considered obvious the one of ordinary skill in the art would rearrange the driving chip IC such that it was arranged in the non-display area between the display modules 002 and not orthographically overlapping with the connection electrode 103 (connection trace) in order to create a separate structure that, while still electrically connected to said electrode/trace, now has improved thermal isolation, electrical isolation, and repairability/replaceability.).
Regarding claim 4, Sun teaches wherein the display substrate comprises: a substrate; a driving circuit layer disposed on a side of the substrate away from the driving backplane; the driving circuit layer is electrically connected to the first connection terminal; and a light-emitting function layer, wherein the first connection terminal is disposed on a surface of the substrate facing the driving backplane and is electrically connected to the light-emitting function layer (Fig. 2 points to the flexible substrate 201, a first metal layer 2041 (driving circuit layer), and a light-emitting function layer 2071.).
Regarding claim 5, Sun teaches wherein the connecting circuit layer further comprises a driving function layer in the display area (Fig. 2 points to a connection electrode 103 (driving function layer).), the second connection terminal is electrically connected to the driving function layer through a first via hole of the connecting circuit layer (Id. points to the connection electrodes 101 (second connection terminal) and 103 (driving function layer) being connected by a via hole O7.), the driving integrated circuit is disposed in the non-display area and electrically contacts the driving function layer, and orthographic projections of the driving integrated circuit and the driving function layer projected on the substrate layer do not overlap each other (Id. points to the driving chip IC. The court has held that the mere rearrangement of parts is an obvious matter of design choice with no patentable significance unless it would modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975). Thus, it is considered obvious the one of ordinary skill in the art would rearrange the driving chip IC such that it was arranged in the non-display area between the display modules 002 and not orthographically overlapping with the connection electrode 103 (driving function layer) in order to create a separate structure that, while still electrically connected to said electrode/layer, now has improved thermal isolation, electrical isolation, and repairability/replaceability.).
Regarding claim 7, Sun teaches wherein the connecting circuit layer further comprises a driving function layer in the display area (Fig. 2 points to a connection electrode 103 (driving function layer).), the second connection terminal is electrically connected to the driving function layer through the first via hole (Id. points to the connection electrodes 101 (second connection terminal) and 103 (driving function layer) being connected by a via hole O7.), the driving integrated circuit is disposed on the substrate layer in the display area, and the connecting circuit layer is disposed on the drive integrated circuit (Id. points to the substrate 102, the driving chip IC and the connection structure 003 (connecting circuit layer). The court has held that the mere rearrangement of parts is an obvious matter of design choice with no patentable significance unless it would modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975). Thus, it is considered obvious that one of ordinary skill in the art would rearrange the driving chip IC (driving integrated circuit) such that it is between the substrate 102 and connection structure 003 (connecting circuit layer) in order to better protect said chip by forming it further within the overall structure.), the connecting circuit layer is further provided with a sixth via hole (The court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Thus, it is considered obvious that one of ordinary skill in the art would create an additional via hole similar to the via hole O7, in order to create additional signal paths.), and the driving integrated circuit is electrically connected to the driving function layer through the sixth via hole (It is considered obvious that one of ordinary skill in the art would connect the driving integrated circuit to the driving function layer via the sixth via hole in order to establish an interface that that would reduce interference while still maintaining communication. The court has held that the mere rearrangement of parts is an obvious matter of design choice with no patentable significance unless it would modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975).).
Regarding claim 11, Sun teaches a display device, comprising: a housing defining a containing cavity; and a spliced display panel, wherein the spliced display panel is disposed in the containing cavity; wherein the spliced display panel comprises a display area and a non-display area on a side of the display area (Fig. 20 points to a display device comprising a plurality of display modules 002 and a non-display area between the display modules 002 adjacent to each other that is mainly formed by a seam A. It is considered obvious that one of ordinary skill in the art would form a housing containing a cavity in order to surround the spliced display panel and create a protective layer that would prevent any undue external interference.); wherein the spliced display panel further comprises: a plurality of display components in the display area, wherein each of the display components comprises a plurality of first connection terminals and a display substrate electrically connected to the first connection terminals (Fig. 2 points to a display module 002 (display component) comprising bottom electrodes 203 (first connection terminals) and a flexible substrate 201.); a driving backplane comprising a connecting circuit layer in the display area, wherein the connecting circuit layer comprises a plurality of second connection terminals bound to the plurality of first connection terminals, and a plurality of the display components are arranged in an array on the driving backplane (Figs. 2 and 23 point to a connection structure 003 and connection electrodes 101 (second connection terminals).); and a driving integrated circuit electrically connected to the plurality of second connection terminals, wherein the driving integrated circuit sequentially transmits signals to the plurality of first connection terminals and the display substrate through the plurality of second connection terminals to drive the display substrate to emit light (Fig. 2 and Col. 11, lines 64-67 point to a driving chip IC.).
Regarding claim 12, Sun teaches wherein the driving backplane further comprises a substrate layer, and the connecting circuit layer and the driving integrated circuit are disposed on the substrate layer (Fig. 2 points to a substrate 102.).
Regarding claim 13, Sun teaches wherein the connecting circuit layer further comprises a connection trace, a first interlayer insulating layer, and a second interlayer insulating layer in the display area (Fig. 2 points to a connection electrode 103 (connection trace), a protective film 104 (first interlayer insulating layer), and at least one of an anisotropic conductive adhesive, a conductive silver paste, an alloy formed by eutectic bonding, or the like (second interlayer insulating layer) which is used to form the connection structure 003.), the first interlayer insulating layer is disposed on the substrate layer, the connection trace is disposed on the first interlayer insulating layer, the second interlayer insulating layer is disposed on the connection trace (The court has held that the mere rearrangement of parts is an obvious matter of design choice with no patentable significance unless it would modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975). Thus it is considered obvious that one of ordinary skill in the art would rearrange the previously mentioned components in order to reduce the critical dimensions of the overall structure and/or improve signal transmission to/from the driving chip IC, resulting in a connection structure 003 (connecting circuit layer) on the substrate 102 comprising the protective film 104 (first interlayer insulating layer), the connection electrode 103 (connection trace), and the material (second interlayer insulating layer) previously used to form the connection structure 003.), the second connection terminal is electrically connected to the connection trace and the first connection terminal through a first via hole penetrating the second interlayer insulating layer (Fig. 2 points to the connection electrodes 101 (second connection terminal) and 103 (connection trace) being connected by a via hole O7.), the driving integrated circuit in the non-display area is electrically connected to the connection trace, and orthographic projections of the driving integrated circuit and the connection trace projected on the substrate layer do not overlap each other (Id. points to the driving chip IC. The court has held that the mere rearrangement of parts is an obvious matter of design choice with no patentable significance unless it would modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975). Thus, it is considered obvious the one of ordinary skill in the art would rearrange the driving chip IC such that it was arranged in the non-display area between the display modules 002 and not orthographically overlapping with the connection electrode 103 (connection trace) in order to create a separate structure that, while still electrically connected to said electrode/trace, now has improved thermal isolation, electrical isolation, and repairability/replaceability.).
Regarding claim 14, Sun teaches wherein the display substrate comprises: a substrate; a driving circuit layer disposed on a side of the substrate away from the driving backplane; the driving circuit layer is electrically connected to the first connection terminal; and a light-emitting function layer, wherein the first connection terminal is disposed on a surface of the substrate facing the driving backplane and is electrically connected to the light-emitting function layer (Fig. 2 points to the flexible substrate 201, a first metal layer 2041 (driving circuit layer), and a light-emitting function layer 2071.).
Regarding claim 15, Sun teaches wherein the connecting circuit layer further comprises a driving function layer in the display area (Fig. 2 points to a connection electrode 103 (driving function layer).), the second connection terminal is electrically connected to the driving function layer through a first via hole of the connecting circuit layer (Id. points to the connection electrodes 101 (second connection terminal) and 103 (driving function layer) being connected by a via hole O7.), the driving integrated circuit is disposed in the non-display area and electrically contacts the driving function layer, and orthographic projections of the driving integrated circuit and the driving function layer projected on the substrate layer do not overlap each other (Id. points to the driving chip IC. The court has held that the mere rearrangement of parts is an obvious matter of design choice with no patentable significance unless it would modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975). Thus, it is considered obvious the one of ordinary skill in the art would rearrange the driving chip IC such that it was arranged in the non-display area between the display modules 002 and not orthographically overlapping with the connection electrode 103 (driving function layer) in order to create a separate structure that, while still electrically connected to said electrode/layer, now has improved thermal isolation, electrical isolation, and repairability/replaceability.).
Regarding claim 17, Sun teaches wherein the connecting circuit layer further comprises a driving function layer in the display area (Fig. 2 points to a connection electrode 103 (driving function layer).), the second connection terminal is electrically connected to the driving function layer through the first via hole (Id. points to the connection electrodes 101 (second connection terminal) and 103 (driving function layer) being connected by a via hole O7.), the driving integrated circuit is disposed on the substrate layer in the display area, and the connecting circuit layer is disposed on the drive integrated circuit (Id. points to the substrate 102, the driving chip IC and the connection structure 003 (connecting circuit layer). The court has held that the mere rearrangement of parts is an obvious matter of design choice with no patentable significance unless it would modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975). Thus, it is considered obvious that one of ordinary skill in the art would rearrange the driving chip IC (driving integrated circuit) such that it is between the substrate 102 and connection structure 003 (connecting circuit layer) in order to better protect said chip by forming it further within the overall structure.), the connecting circuit layer is further provided with a sixth via hole (The court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Thus, it is considered obvious that one of ordinary skill in the art would create an additional via hole similar to the via hole O7, in order to create additional signal paths.), and the driving integrated circuit is electrically connected to the driving function layer through the sixth via hole (It is considered obvious that one of ordinary skill in the art would connect the driving integrated circuit to the driving function layer via the sixth via hole in order to establish an interface that that would reduce interference while still maintaining communication. The court has held that the mere rearrangement of parts is an obvious matter of design choice with no patentable significance unless it would modify the operation of the device. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975).).
Regarding claim 19, Sun teaches wherein the connecting circuit layer further comprises a sealing layer, and the sealing layer is disposed between the display component and the driving backplane and covers the first connection terminal and the second connection terminal (Col. 11, lines 19-22 point to the connection structure 003 (connecting circuit layer) which may be formed by an anisotropic conductive adhesive (sealing layer).).
Regarding claim 20, Sun teaches wherein the connecting circuit layer further comprises a sealing layer, and the sealing layer is disposed between the display component and the driving backplane and covers the first connection terminal and the second connection terminal (Col. 11, lines 19-22 point to the connection structure 003 (connecting circuit layer) which may be formed by an anisotropic conductive adhesive (sealing layer).).
Claim(s) 6, 8, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sun in further view of Park (PGPub No. 20210376036).
Regarding claim 6, Park teaches wherein the connecting circuit layer further comprises a first interlayer insulating layer and a second interlayer insulating layer on the substrate layer (Fig. 7 points to a pixel circuit layer PCL (connecting circuit layer) comprising a substrate 100, a buffer layer 111a (first interlayer insulating layer), and an interlayer insulating layer 114 (second interlayer insulating layer).); wherein the driving function layer comprises: a second buffer layer disposed on the first interlayer insulating layer; a second semiconductor layer disposed on the second buffer layer; a sixth interlayer insulating layer disposed on the second buffer layer and covering the second semiconductor layer; a third gate disposed on the sixth interlayer insulating layer and being opposite the second semiconductor layer; a seventh interlayer insulating layer disposed on the sixth interlayer insulating layer and covering the third gate, wherein the second interlayer insulating layer is disposed on the seventh interlayer insulating layer; a fourth gate disposed on the seventh interlayer insulating layer, wherein the second interlayer insulating layer covers the fourth gate, and the first via hole is electrically connected to the second semiconductor layer; and a third connection terminal and a fourth connection terminal disposed on the second interlayer insulating layer, wherein the third connection terminal is electrically connected to the fourth connection terminal, the third connection terminal is electrically connected to the second semiconductor layer through a fifth via hole of the connecting circuit layer, and the driving integrated circuit electrically contacts the fourth connection terminal (Id. points to a pixel circuit PC (driving function layer) comprising a buffer layer 111b (second buffer layer), a semiconductor layer A2, gate insulating layers 112 (sixth interlayer insulating layer) and 113 (seventh interlayer insulating layer), gate electrodes G1 (third gate) and G2 (fourth gate), a drain electrode D1 (first via hole), and a source electrode S1 (third connection terminal). [0091] further points to the pixel circuit being electrically connected to outer circuits (driving integrated circuit). It is considered obvious that one or ordinary skill in the art would form an extension or interface (fourth connection terminal) between the pixel circuit and outer circuit(s) in order to reduce interference while still maintaining communication.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Sun and Park, such that the driving function layer is formed within the connecting circuit layer and includes a two-gate structure in order to form a pixel circuit that drives a corresponding sub-pixel according to the signals sent by an outer circuit.
Regarding claim 8, Sun in combination with Park teaches wherein the connecting circuit layer further comprises a first interlayer insulating layer and a second interlayer insulating layer on the substrate layer (Fig. 7 of Park points to a pixel circuit layer PCL (connecting circuit layer) comprising a substrate 100, a buffer layer 111a (first interlayer insulating layer), and an interlayer insulating layer 114 (second interlayer insulating layer).); and wherein the driving function layer comprises: a second buffer layer disposed on the first interlayer insulating layer; a second semiconductor layer disposed on the second buffer layer; a sixth interlayer insulating layer disposed on the second buffer layer and covering the second semiconductor layer; a third gate disposed on the sixth interlayer insulating layer and being opposite the second semiconductor layer; a seventh interlayer insulating layer disposed on the sixth interlayer insulating layer and covering the third gate, wherein the second interlayer insulating layer is disposed on the seventh interlayer insulating layer; a fourth gate disposed on the seventh interlayer insulating layer, wherein the second interlayer insulating layer covers the fourth gate, and the first via hole is electrically connected to the second semiconductor layer; and a third connection terminal disposed on the second interlayer insulating layer, wherein the third connection terminal is electrically connected to the second semiconductor layer through a fifth via hole of the connecting circuit layer (Id. points to a pixel circuit PC (driving function layer) comprising a buffer layer 111b (second buffer layer), a semiconductor layer A2, gate insulating layers 112 (sixth interlayer insulating layer) and 113 (seventh interlayer insulating layer), gate electrodes G1 (third gate) and G2 (fourth gate), a drain electrode D1 (first via hole), and a source electrode S1 (third connection terminal; fifth via hole).) and is electrically connected to the driving integrated circuit through the sixth via hole (Fig. 2 of Sun points to a display device comprising the driving chip IC (driving integrated circuit) electrically connected to a portion (third connection terminal) of the connection electrode 103 (driving function layer). It is considered obvious that one of ordinary skill in the art would duplicate the fifth via hole to create a sixth via hole in order to establish a vertical interface between said chip/circuit and electrode/terminal that would reduce interference while still maintaining communication. The court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Sun and Park, such that the driving function layer is formed within the connecting circuit layer and includes a two-gate structure in order to form a pixel circuit that drives a corresponding sub-pixel according to the signals sent by a buried integrated circuit.
Regarding claim 16, Park teaches wherein the connecting circuit layer further comprises a first interlayer insulating layer and a second interlayer insulating layer on the substrate layer (Fig. 7 points to a pixel circuit layer PCL (connecting circuit layer) comprising a substrate 100, a buffer layer 111a (first interlayer insulating layer), and an interlayer insulating layer 114 (second interlayer insulating layer).); wherein the driving function layer comprises: a second buffer layer disposed on the first interlayer insulating layer; a second semiconductor layer disposed on the second buffer layer; a sixth interlayer insulating layer disposed on the second buffer layer and covering the second semiconductor layer; a third gate disposed on the sixth interlayer insulating layer and being opposite the second semiconductor layer; a seventh interlayer insulating layer disposed on the sixth interlayer insulating layer and covering the third gate, wherein the second interlayer insulating layer is disposed on the seventh interlayer insulating layer; a fourth gate disposed on the seventh interlayer insulating layer, wherein the second interlayer insulating layer covers the fourth gate, and the first via hole is electrically connected to the second semiconductor layer; and a third connection terminal and a fourth connection terminal disposed on the second interlayer insulating layer, wherein the third connection terminal is electrically connected to the fourth connection terminal, the third connection terminal is electrically connected to the second semiconductor layer through a fifth via hole of the connecting circuit layer, and the driving integrated circuit electrically contacts the fourth connection terminal (Id. points to a pixel circuit PC (driving function layer) comprising a buffer layer 111b (second buffer layer), a semiconductor layer A2, gate insulating layers 112 (sixth interlayer insulating layer) and 113 (seventh interlayer insulating layer), gate electrodes G1 (third gate) and G2 (fourth gate), a drain electrode D1 (first via hole), and a source electrode S1 (third connection terminal). [0091] further points to the pixel circuit being electrically connected to outer circuits (driving integrated circuit). It is considered obvious that one or ordinary skill in the art would form an extension or interface (fourth connection terminal) between the pixel circuit and outer circuit(s) in order to reduce interference while still maintaining communication.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Sun and Park, such that the driving function layer is formed within the connecting circuit layer and includes a two-gate structure in order to form a pixel circuit that drives a corresponding sub-pixel according to the signals sent by an outer circuit.
Regarding claim 18, Sun in combination with Park teaches wherein the connecting circuit layer further comprises a first interlayer insulating layer and a second interlayer insulating layer on the substrate layer (Fig. 7 of Park points to a pixel circuit layer PCL (connecting circuit layer) comprising a substrate 100, a buffer layer 111a (first interlayer insulating layer), and an interlayer insulating layer 114 (second interlayer insulating layer).); and wherein the driving function layer comprises: a second buffer layer disposed on the first interlayer insulating layer; a second semiconductor layer disposed on the second buffer layer; a sixth interlayer insulating layer disposed on the second buffer layer and covering the second semiconductor layer; a third gate disposed on the sixth interlayer insulating layer and being opposite the second semiconductor layer; a seventh interlayer insulating layer disposed on the sixth interlayer insulating layer and covering the third gate, wherein the second interlayer insulating layer is disposed on the seventh interlayer insulating layer; a fourth gate disposed on the seventh interlayer insulating layer, wherein the second interlayer insulating layer covers the fourth gate, and the first via hole is electrically connected to the second semiconductor layer; and a third connection terminal disposed on the second interlayer insulating layer, wherein the third connection terminal is electrically connected to the second semiconductor layer through a fifth via hole of the connecting circuit layer (Id. points to a pixel circuit PC (driving function layer) comprising a buffer layer 111b (second buffer layer), a semiconductor layer A2, gate insulating layers 112 (sixth interlayer insulating layer) and 113 (seventh interlayer insulating layer), gate electrodes G1 (third gate) and G2 (fourth gate), a drain electrode D1 (first via hole), and a source electrode S1 (third connection terminal; fifth via hole).) and is electrically connected to the driving integrated circuit through the sixth via hole (Fig. 2 of Sun points to a display device comprising the driving chip IC (driving integrated circuit) electrically connected to a portion (third connection terminal) of the connection electrode 103 (driving function layer). It is considered obvious that one of ordinary skill in the art would duplicate the fifth via hole to create a sixth via hole in order to establish a vertical interface between said chip/circuit and electrode/terminal that would reduce interference while still maintaining communication. The court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Sun and Park, such that the driving function layer is formed within the connecting circuit layer and includes a two-gate structure in order to form a pixel circuit that drives a corresponding sub-pixel according to the signals sent by a buried integrated circuit.
Conclusion
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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