DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 27, 2026 has been entered.
Claims 1-4, 6-9, and 12 are pending in this office action and presented for examination. Claims 1-4, 6-9, and 12 are newly amended, and claims 5 and 10 are newly cancelled, by the RCE received April 8, 2026.
Claim Objections
Claims 6-9 and 12 are objected to because of the following informalities. Appropriate correction is required.
In claim 6, line 27, “the second data points” should be “the plurality of second data points” for antecedent basis clarity. (See, for example, claim 1, line 16.)
Claims 7-9 are objected to for failing to alleviate the objection of claim 6 above.
In claim 8, lines 10-11, a comma appears to be immediately followed by a semicolon.
In claim 12, line 29, “the second data points” should be “the plurality of second data points” for antecedent basis clarity. (See, for example, claim 1, line 16.)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-9, and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ould-Ahmed-Vall et al. (Ould-Ahmed-Vall) (US 20140019712 A1).
Consider claim 1, Ould-Ahmed-Vall discloses a data processing method ([0048], lines 1-2, FIG. 3 illustrates an embodiment of a method for processing a VPCOMPRESSN instruction), comprising: obtaining a decoded processing instruction by decoding a processing instruction ([0044], lines 1-2, The VPCOMPRESSN instruction is decoded by decoding logic), wherein the decoded processing instruction includes an operation code ([0041], lines 4-5, VPCOMPRESSN is the instruction's opcode) and an operation field ([0041], line 2, DEST, SRC1, SRC2; [0043], lines 2-4, A VPCOMPRESSN instruction with a two source vector register operands and a destination vector register operand), the operation code indicates a performing of a vector extension processing ([0041], lines 4-5, VPCOMPRESSN is the instruction's opcode; [0037], lines 1-19, below are embodiments of an instruction generically called a vector packed compression and repeat ("VPCOMPRESSN") instruction and embodiments of systems, architectures, instruction formats, etc. that may be used to execute such an instruction that is beneficial in several different areas. This instruction implements a restricted permutation where the order of the elements is maintained but elements can be repeated or skipped. The execution of a VPCOMPRESSN instruction causes the selective storage of packed data operands of a first source vector register into one or more packed data element positions of the destination vector register based on the contents of a second source vector register. More particularly, for each packed data element position of the first source vector register, a corresponding packed data element position of the second vector register determines the number of times (from 0 to n) that the packed data of the packed data element position of the first source register is to be written into previously unused least significant packed data element positions of the destination vector register), the operation field indicates a first vector data ([0037], line 10, packed data operands of a first source vector register), and the first vector data includes a plurality of first data points ([0037], line 10, packed data operands of a first source vector register); determining source data addresses, wherein the source data addresses include consecutive present data storage addresses of the plurality of first data points ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0045], lines 1-4, the source operand values are retrieved/read at 205. For example, the source registers are read. If one or both of the source operands is a memory operand, then the data elements associated with that operand are retrieved; [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location); determining an extension parameter of the first vector data ([0037], lines 12-13, contents of a second source vector register; [0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0045], lines 1-4, the source operand values are retrieved/read at 205. For example, the source registers are read. If one or both of the source operands is a memory operand, then the data elements associated with that operand are retrieved; [0049], lines 1-3, a determination of a value of a least significant packed data element position of the second source vector register is made; [0050], lines 1-3, the next least significant packed data element position of the second source vector register is evaluated for its value); reading the plurality of first data points from the source data addresses and respectively extending the plurality of first data points according to the extension parameter to obtain a plurality of second data points ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0039], lines 1-7, for each data element position of the first source vector register, beginning at the least significant data element position, a corresponding data element position of the second source vector register determines the number of times that the data of that data element position will be copied (stored) into the destination vector register beginning with the least significant data element position; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location); determining destination data addresses, wherein the destination data addresses represent consecutive data storage addresses for storing the plurality of second data points ([0047], lines 1-3, The determined packed data elements of the first source vector register are stored value times in the destination register at 209; [0047], lines 5-7, this storage begins at the least significant packed data element position of the destination vector register as illustrated in FIG. 1; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location); and sequentially storing the plurality of second data points to the destination data addresses to obtain a second vector data ([0047], lines 1-3, The determined packed data elements of the first source vector register are stored value times in the destination register at 209; [0047], lines 5-7, this storage begins at the least significant packed data element position of the destination vector register as illustrated in FIG. 1; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location; [0055], line 2, a serial write).
Consider claim 2, Ould-Ahmed-Vall discloses the data processing method of claim 1 (see above), wherein the source data addresses are determined according to a source data base address of the plurality of first data points and a data size of each of the plurality of first data points ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0045], lines 1-4, the source operand values are retrieved/read at 205. For example, the source registers are read. If one or both of the source operands is a memory operand, then the data elements associated with that operand are retrieved; [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location; [0041], lines 9-10, the size of the data elements may be defined in the "prefix" of the instruction; also see [0078], line 3, base; [0079], line 3, base; [0080], line 8, base), the source data base address represents a base address of the plurality of first data points of the first vector data in a data storage space ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0045], lines 1-4, the source operand values are retrieved/read at 205. For example, the source registers are read. If one or both of the source operands is a memory operand, then the data elements associated with that operand are retrieved; [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location), and the source data base address and the data size are included in the operation field of the decoded processing instruction ([0041], line 2, DEST, SRC1, SRC2; [0043], lines 2-4, A VPCOMPRESSN instruction with a two source vector register operands and a destination vector register operand; [0041], lines 9-10, the size of the data elements may be defined in the "prefix" of the instruction).
Consider claim 3, Ould-Ahmed-Vall discloses the data processing method of claim 1, wherein the plurality of first data points of the first vector data are N data points, and the extension parameter includes N extension parameter values corresponding to the N data points, wherein N is an integer greater than 1, wherein an nth extension parameter value of the N extension parameter values is kn, wherein each extension parameter value indicates a number kn of times a corresponding data point of the N data points is to be copied into the second vector data, wherein kn> 0, and wherein respectively extending the plurality of first data points according to the extension parameter to obtain the plurality of second data points includes: determining, for each 1<=n<=N, kn second data points of the second vector data according to an nth first data point of the first vector data and an nth extension parameter value corresponding to the nth first data point; and generating the second vector data based on the kn second data points determined for each 1<=n<=N ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0039], lines 1-7, for each data element position of the first source vector register, beginning at the least significant data element position, a corresponding data element position of the second source vector register determines the number of times that the data of that data element position will be copied (stored) into the destination vector register beginning with the least significant data element position; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]).
Consider claim 4, Ould-Ahmed-Vall discloses the data processing method of claim 1 (see above), wherein the plurality of second data points is sequentially stored to the destination data addresses according to a destination data base address of the plurality of second data points and a data size of each of the plurality of second data points ([0047], lines 1-3, The determined packed data elements of the first source vector register are stored value times in the destination register at 209; [0047], lines 5-7, this storage begins at the least significant packed data element position of the destination vector register as illustrated in FIG. 1; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location; [0055], line 2, a serial write; [0041], lines 9-10, the size of the data elements may be defined in the "prefix" of the instruction; also see [0078], line 3, base; [0079], line 3, base; [0080], line 8, base), and the destination data base address represents a base address of the plurality of second data points in a data storage space ([0047], lines 1-3, The determined packed data elements of the first source vector register are stored value times in the destination register at 209; [0047], lines 5-7, this storage begins at the least significant packed data element position of the destination vector register as illustrated in FIG. 1; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location; [0055], line 2, a serial write).
Consider claim 6, Ould-Ahmed-Vall discloses a data processing apparatus ([0003], line 2, processor), comprising: a decoding circuit configured to obtain a decoded processing instruction based on a processing instruction ([0044], lines 1-2, The VPCOMPRESSN instruction is decoded by decoding logic), wherein the decoded processing instruction includes an operation code ([0041], lines 4-5, VPCOMPRESSN is the instruction's opcode) and an operation field ([0041], line 2, DEST, SRC1, SRC2; [0043], lines 2-4, A VPCOMPRESSN instruction with a two source vector register operands and a destination vector register operand), the operation code indicates a performing of a vector extension processing ([0041], lines 4-5, VPCOMPRESSN is the instruction's opcode; [0037], lines 1-19, below are embodiments of an instruction generically called a vector packed compression and repeat ("VPCOMPRESSN") instruction and embodiments of systems, architectures, instruction formats, etc. that may be used to execute such an instruction that is beneficial in several different areas. This instruction implements a restricted permutation where the order of the elements is maintained but elements can be repeated or skipped. The execution of a VPCOMPRESSN instruction causes the selective storage of packed data operands of a first source vector register into one or more packed data element positions of the destination vector register based on the contents of a second source vector register. More particularly, for each packed data element position of the first source vector register, a corresponding packed data element position of the second vector register determines the number of times (from 0 to n) that the packed data of the packed data element position of the first source register is to be written into previously unused least significant packed data element positions of the destination vector register), the operation field indicates a first vector data ([0037], line 10, packed data operands of a first source vector register), and the first vector data includes a plurality of first data points ([0037], line 10, packed data operands of a first source vector register); an address determining circuit configured to: determine source data addresses, wherein the source data addresses include consecutive present data storage addresses of the plurality of first data points ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0045], lines 1-4, the source operand values are retrieved/read at 205. For example, the source registers are read. If one or both of the source operands is a memory operand, then the data elements associated with that operand are retrieved; [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location); determine an extension parameter of the first vector data ([0037], lines 12-13, contents of a second source vector register; [0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0045], lines 1-4, the source operand values are retrieved/read at 205. For example, the source registers are read. If one or both of the source operands is a memory operand, then the data elements associated with that operand are retrieved; [0049], lines 1-3, a determination of a value of a least significant packed data element position of the second source vector register is made; [0050], lines 1-3, the next least significant packed data element position of the second source vector register is evaluated for its value); and determine destination data addresses, wherein the destination data addresses represent consecutive data storage addresses for storing a plurality of second data points ([0047], lines 1-3, The determined packed data elements of the first source vector register are stored value times in the destination register at 209; [0047], lines 5-7, this storage begins at the least significant packed data element position of the destination vector register as illustrated in FIG. 1; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location); a data extending circuit configured to read the plurality of first data points from the source data addresses and respectively extend the plurality of first data points according to the extension parameter to obtain the plurality of second data points ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0039], lines 1-7, for each data element position of the first source vector register, beginning at the least significant data element position, a corresponding data element position of the second source vector register determines the number of times that the data of that data element position will be copied (stored) into the destination vector register beginning with the least significant data element position; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location); and a data storing circuit configured to sequentially store the second data points to the destination data addresses to obtain a second vector data ([0047], lines 1-3, The determined packed data elements of the first source vector register are stored value times in the destination register at 209; [0047], lines 5-7, this storage begins at the least significant packed data element position of the destination vector register as illustrated in FIG. 1; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location; [0055], line 2, a serial write).
Consider claim 7, Ould-Ahmed-Vall discloses the data processing apparatus of claim 6 (see above), wherein the address determining circuit is further configured to determine the source data addresses according to a source data base address of the plurality of first data points and a data size of each of the plurality of first data points ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0045], lines 1-4, the source operand values are retrieved/read at 205. For example, the source registers are read. If one or both of the source operands is a memory operand, then the data elements associated with that operand are retrieved; [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location; [0041], lines 9-10, the size of the data elements may be defined in the "prefix" of the instruction; also see [0078], line 3, base; [0079], line 3, base; [0080], line 8, base), the source data base address represents a base address of the plurality of first data points of the first vector data in a data storage space ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0045], lines 1-4, the source operand values are retrieved/read at 205. For example, the source registers are read. If one or both of the source operands is a memory operand, then the data elements associated with that operand are retrieved; [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location), and the source data base address and the data size are included in the operation field of the decoded processing instruction ([0041], line 2, DEST, SRC1, SRC2; [0043], lines 2-4, A VPCOMPRESSN instruction with a two source vector register operands and a destination vector register operand; [0041], lines 9-10, the size of the data elements may be defined in the "prefix" of the instruction).
Consider claim 8, Ould-Ahmed-Vall discloses the data processing apparatus of claim 6, wherein the plurality of first data points of the first vector data are N data points, and the extension parameter includes N extension parameter values corresponding to the N data points, wherein N is an integer greater than 1, wherein an nth extension parameter value of the N extension parameter values is kn, wherein each extension parameter value indicates a number kn of times a corresponding data point of the N data points is to be copied into the second vector data, wherein kn> 0, and the data extending circuit includes: a data point determining sub-circuit configured to determine, for each 1<=n<=N, kn second data points of the second vector data according to an nth first data point of the first vector data and an nth extension parameter value corresponding to the nth first data point; and a data determining sub-circuit configured to generate the second vector data based on the kn second data points determined for each 1<=n<=N ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0039], lines 1-7, for each data element position of the first source vector register, beginning at the least significant data element position, a corresponding data element position of the second source vector register determines the number of times that the data of that data element position will be copied (stored) into the destination vector register beginning with the least significant data element position; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]).
Consider claim 9, Ould-Ahmed-Vall discloses the data processing apparatus of claim 6 (see above), wherein the data storing circuit is further configured to sequentially store the plurality of second data points according to a destination data base address of the plurality of second data points and a data size of each of the plurality of second data points ([0047], lines 1-3, The determined packed data elements of the first source vector register are stored value times in the destination register at 209; [0047], lines 5-7, this storage begins at the least significant packed data element position of the destination vector register as illustrated in FIG. 1; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location; [0055], line 2, a serial write; [0041], lines 9-10, the size of the data elements may be defined in the "prefix" of the instruction; also see [0078], line 3, base; [0079], line 3, base; [0080], line 8, base), and the destination data base address represents a base address of the plurality of second data points in a data storage space ([0047], lines 1-3, The determined packed data elements of the first source vector register are stored value times in the destination register at 209; [0047], lines 5-7, this storage begins at the least significant packed data element position of the destination vector register as illustrated in FIG. 1; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location; [0055], line 2, a serial write).
Consider claim 12, Ould-Ahmed-Vall discloses an electronic device, wherein the electronic device including an artificial intelligence chip ([0163], line 4, chip; [0005], lines 1-5, Scientific, financial, auto-vectorized general purpose, RMS (recognition, mining, and synthesis), and visual and multimedia applications (e.g., 2D/3D graphics, image processing, video compression/decompression, voice recognition algorithms and audio manipulation)), wherein the artificial intelligence chip includes an apparatus for data processing ([0003], line 2, processor), comprising: a decoding circuit configured to obtain a decoded processing instruction based on a processing instruction ([0044], lines 1-2, The VPCOMPRESSN instruction is decoded by decoding logic), wherein the decoded processing instruction includes an operation code ([0041], lines 4-5, VPCOMPRESSN is the instruction's opcode) and an operation field ([0041], line 2, DEST, SRC1, SRC2; [0043], lines 2-4, A VPCOMPRESSN instruction with a two source vector register operands and a destination vector register operand), the operation code indicates a performing of a vector extension processing ([0041], lines 4-5, VPCOMPRESSN is the instruction's opcode; [0037], lines 1-19, below are embodiments of an instruction generically called a vector packed compression and repeat ("VPCOMPRESSN") instruction and embodiments of systems, architectures, instruction formats, etc. that may be used to execute such an instruction that is beneficial in several different areas. This instruction implements a restricted permutation where the order of the elements is maintained but elements can be repeated or skipped. The execution of a VPCOMPRESSN instruction causes the selective storage of packed data operands of a first source vector register into one or more packed data element positions of the destination vector register based on the contents of a second source vector register. More particularly, for each packed data element position of the first source vector register, a corresponding packed data element position of the second vector register determines the number of times (from 0 to n) that the packed data of the packed data element position of the first source register is to be written into previously unused least significant packed data element positions of the destination vector register), the operation field indicates a first vector data ([0037], line 10, packed data operands of a first source vector register), and the first vector data includes a plurality of first data points ([0037], line 10, packed data operands of a first source vector register); an address determining circuit configured to: determine source data addresses, wherein the source data addresses include consecutive present data storage addresses of the plurality of first data points ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0045], lines 1-4, the source operand values are retrieved/read at 205. For example, the source registers are read. If one or both of the source operands is a memory operand, then the data elements associated with that operand are retrieved; [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location); determine an extension parameter of the first vector data ([0037], lines 12-13, contents of a second source vector register; [0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0045], lines 1-4, the source operand values are retrieved/read at 205. For example, the source registers are read. If one or both of the source operands is a memory operand, then the data elements associated with that operand are retrieved; [0049], lines 1-3, a determination of a value of a least significant packed data element position of the second source vector register is made; [0050], lines 1-3, the next least significant packed data element position of the second source vector register is evaluated for its value); and determine destination data addresses, wherein the destination data addresses represent consecutive data storage addresses for storing a plurality of second data points ([0047], lines 1-3, The determined packed data elements of the first source vector register are stored value times in the destination register at 209; [0047], lines 5-7, this storage begins at the least significant packed data element position of the destination vector register as illustrated in FIG. 1; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location); a data extending circuit configured to read the plurality of first data points from the source data addresses and respectively extend the plurality of first data points according to the extension parameter to obtain the plurality of second data points ([0046], lines 4-11, determine, for each packed data element position of the first source vector register, how many times that packed data element position's packed data element is to be stored in the destination vector register based on the value of a corresponding packed data element position of the second source vector register. This evaluation begins at the least significant packed data element position of the source vector registers; [0039], lines 1-7, for each data element position of the first source vector register, beginning at the least significant data element position, a corresponding data element position of the second source vector register determines the number of times that the data of that data element position will be copied (stored) into the destination vector register beginning with the least significant data element position; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location); and a data storing circuit configured to sequentially store the second data points to the destination data addresses to obtain a second vector data ([0047], lines 1-3, The determined packed data elements of the first source vector register are stored value times in the destination register at 209; [0047], lines 5-7, this storage begins at the least significant packed data element position of the destination vector register as illustrated in FIG. 1; [0051], lines 1-7, If the value is not zero, then a write of the corresponding packed data element position of the first source vector register is into "value" number of the least significant unused packed data element positions of the destination register is made at 311. For example, SRC[0]'s value of "a" is written in the two least significant unused packed data element positions of the destination register (i.e., DST[1:0]); [0041], lines 7-8, in some embodiments, the VPCOMPRESSN instruction operates on memory locations instead of registers; [0041], lines 14-15, in some embodiments, the source operand is not a register, but rather a memory location; [0055], line 2, a serial write).
Response to Arguments
Applicant on page 11 argues: "Office Action states that: 37 CFR 1.98 requires legible copies; however, NPL reference 1 of the IDS dated October5.29, 2025, does not meet this requirement. Examiner recommends resubmitting the reference with better legibility. Applicant resubmits the reference."
Examiner thanks Applicant for the resubmission and has considered the reference.
Applicant on page 11 argues: "Claims 1-10 and 12 are objected to because of the following informalities Applicant amended claims 1-4, 6-9, and 12 and canceled claims 5 and 10, to fix the informalities. Applicant respectfully requests the withdrawal of the objections to the claims."
In view of the aforementioned amendments, the previously presented objections to the claims are withdrawn.
Applicant on page 12 argues: "In response to the Office Action, Applicant has amended claims 1-4, 6-9, and 12, as set forth above, to clarify the claims without introducing new matter. Support for the amendments is set forth below."
Examiner thanks Applicant for the paragraph citations across pages 12-16 of the remarks. In view of the aforementioned amendments, the previously presented written description rejections are withdrawn.
Applicant on page 16 argues: "In response to the Office Action, Applicant has amended claims 1-4, 6-9, and 12, as set forth above. Thus, Applicant respectfully requests reconsideration and withdrawal of the outstanding rejections under 35 U.S.C. § 112(b)."
In view of the aforementioned amendments, the previously presented indefinite rejections are withdrawn.
Conclusion
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183
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