DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 06 January 2026 has been entered. Claims 1, 4-20 remain pending in the application.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
“addition unit” in claims 1, 3-5;
“update unit” in claim 1;
“sign processing unit” in claim 11;
“partial product computation unit” in claim 14;
“partial product summation unit” in claim 14;
The term “unit” has been interpreted as a generic placeholder. See MPEP 2181.I.A.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
The corresponding structure as described in the specification and/or the claims are identified as follows:
the “addition unit” is interpreted as “204” in Fig. 2 and “1006” in Fig. 10, to comprise an adder tree “218” in Fig. 2 and “1028” in Fig. 10, and includes input/output connections and equivalents as further disclosed in ([34]; [99], [103]) and in claim 6;
the “update unit” is interpreted as “1008” in Fig. 10, to comprise a second adder “1024” and a register “1026” in Fig. 10, and includes input/output connections and equivalents as further disclosed in ([99], [106-108]);
the “sign processing unit” is interpreted as “306” in Fig. 3 and Fig. 4 and as “822” in Fig. 8, to comprise an exclusive OR logic circuit “412” in Fig. 4, and includes input/output connections and equivalents as further disclosed in ([36], [50]; [97]) and in claim 12;
the “partial product computation unit” is interpreted as “402” in Fig. 4, to comprise a Booth encoding circuit “502” and a partial product generation circuit “504” in Fig. 5, and includes input/output connections and equivalents as further disclosed in ([45], [54], [59]) and in claims 14-15;
the “partial product summation unit” is interpreted as “404” in Fig. 4, to comprise a Wallace tree compressor “506” and an adder “508” in Fig. 5, and includes input/output connections and equivalents as further disclosed in ([45], [47-48], [59-64], [66], [69-73]) and in claims 16-17.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over US 9465578 B2 Tannenbaum et al. (hereinafter “Tannenbaum”) in view of US 7225216 B1 Wyland (hereinafter “Wyland”) in view of US 11188303 Nair et al. (hereinafter “Nair”).
Regarding claim 1, Tannenbaum teaches a computing apparatus (Fig. 5, 500; Col. 13, lines 20-32) for performing a vector inner product (Col. 4, lines 1-4) computation, comprising:
a memory configured to store computer-executable instructions (Fig. 5, 504 and/or 510, Col. 13, lines 61-67; Col. 14, lines 1-7) of a multiplication unit (Fig. 3B, 250 and 320 and 322(H) and 322(L); Col. 5, lines 28-29; Col. 9, lines 60-65), an addition unit (Fig. 3B, 310; Col. 5, lines 41-43), and an update unit; and
one or more processors (Fig. 5, 501; Col. 14, lines 8-16) configured to execute the computer-executable instructions (Col. 14, lines 1-7),
wherein the multiplication unit (Fig. 3B, 250 and 320 and 322(H) and 322(L); Col. 5, lines 28-29; Col. 9, lines 60-65; Fig. 2A “201”, “250” and parts of “260” as specified in Fig. 3B, co. 2 ln. 22-24, co. 4 ln. 47-51) is configured to receive a plurality of first vectors (Fig. 2A “First Input Operand” co. 4 ln. 30-51) and a plurality of second vectors (Fig. 2A “Second Input Operand” co. 4 ln. 30-51) to output a plurality of product results (Fig. 3B outputs from “320”, “322(H)”, and “322(L)” co. 9 ln. 60-67, co. 10 ln. 33-53), and the multiplication unit includes a plurality of floating-point multipliers (Fig. 2E, group of 230(0), 235 Unit (0), 320; Col. 8, lines 67, Col. 9, lines 1-8; Col. 9, lines 62-65),
wherein each floating-point multiplier is configured to multiply (Col. 9, lines 8-12) a first vector element (Fig. 3B, A mantissa(s); Col. 6, lines 49-51; Col. 7, lines 59-61; Fig. 2A, 203; Col. 5, lines 19-27) with a corresponding second vector element (Fig. 3B, B mantissa(s); Col. 6, lines 49-51; Col. 7, lines 59-61; Fig. 2A, 204; Col. 5, lines 19-27) to output the product result (Fig. 3B, output from 320, 322(H), and 322(L), Col. 9, lines 39-44, 55-56, Col. 10, lines 33-42) of the first vector element and the corresponding second vector element;
wherein the addition unit (Fig. 3B, 310; Col. 5, lines 41-43) is configured to receive the plurality of product results (Fig. 3B output from 320, 322(H), and 322(L) input to “305” and output from “305”, Col. 9, lines 39-44, 55-56, Col. 10, lines 8-21, 33-49) from the multiplication unit and sum (Col. 5, lines 34-41) the plurality of product results of elements to output a summation result (Fig. 3B, output from 310 M[76:0], Col. 10, lines 8-17).
Regarding claim 1, the preamble is given patentable weight. The independent claims contain the limitation “performing the vector inner product computation”, which is referring to performing a vector inner product as recited in the preamble. A skilled person in the art reading the claims would consider the claim in view of the body and preamble, and identify them limited to vector inner product computations. The body of the claim depends on the preamble for completeness, and gives life, meaning, and vitality to this claim. Therefore, the preamble of claim 1 should be afforded patentable weight.
It would have been obvious to one of ordinary skill in the art before the effective filing data to modify with the alternative embodiments. It would have been obvious to one of ordinary skill in the art would recognize these features, that although sometimes are omitted from illustration in the figures, are capable of being incorporated optionally (Col. 3, lines 18-20). Thus, modifying by incorporating features from Fig. 2A and Fig. 3B would have been obvious.
Tannenbaum is silent to disclosing an update unit configured to, in response to a case that is an intermediate result, perform multiple addition operations on a plurality of intermediate results that are generated to output a final result; wherein the update unit includes a second adder and a register, wherein the second adder is configured to perform the following operations repeatedly until addition operations of all the plurality of intermediate results are completed: receiving an intermediate result and a previous summation result from the register and a previous addition operation; summing the intermediate result and the previous summation result to obtain a summation result of a present addition operation; and updating a previous summation result stored in the register by using the summation result of the present addition operation. Further, although Tannenbaum discloses vectors and floating-point formats, they appear to be silent with disclosing “receive a first vector and a corresponding second vector each first vector includes a plurality of first vector elements each second vector includes a plurality of second vector elements each first vector element includes a sign an exponent and a mantissa and each second vector element includes a sign an exponent and a mantissa” with respect to each floating-point multiplier, and silent with disclosing “is configured to receive the summation result from the addition unit”.
Wyland teaches
wherein the update unit (Fig. 2, 30; Col. 2, lines 39-41) is configured to receive (co. 2 ln. 64-67, co. 3 ln. 1-2) the summation result from the addition unit (see above mapping of Tannenbaum) and, in response to a case that is an intermediate result (Fig. 2, inputs to 30; Col. 2, lines 38-41), perform multiple addition operations (Col. 2, lines 42-50, fed back to Adder) on a plurality of intermediate results (Fig. 2, input from multiplier 10 and un normalized point result fed back, Col. 2, lines 39-41) that are generated to output a final result (Fig. 2, un normalized point result, Col. 2, lines 42-48);
wherein the update unit (Fig. 2, 30; Col. 2, lines 39-41) includes a second adder (Fig. 2, Adder; Col. 2, lines 48-51) and a register (Fig. 2, mantissa accumulator register; Col. 1, lines 31-33, performs similar function), wherein the second adder is configured to perform the following operations repeatedly until the addition operations of all the plurality of intermediate results are completed (Col. 1, lines 56-65):
receiving the intermediate result (Fig. 2, input to 30 from 42; Col. 2, lines 38-41) and a previous summation result (Fig. 2, fed back value; Col. 2, lines 40-41) obtained in a previous addition operation from the register (Col. 2, lines 39-40);
summing (Col. 2, lines 39-40) the intermediate result and the previous summation result to obtain a summation result of a present addition operation (Fig. 2, un normalized point result after cycle; Col. 2, lines 39-40; Col. 1, lines 56-65); and
updating (Col. 1, lines 31-33, performs similar function) a previous summation result stored in the register by using the summation result of the present addition operation (Fig. 2, un normalized point result after cycle; Col. 2, lines 39-40; Col. 1, lines 56-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Tannenbaum’s vector inner product device with Wyland’s update unit and associated features because they are in the claimed invention’s same field of endeavor of multiply-accumulate operations on floating point numbers [abstract]. It would have been obvious to one of ordinary skill in the art to implement the update unit as it removes the need for a comparison for alignment before the addition operation (Col. 1, lines 34-47), and thus allows the device to compute multiply-accumulate on each clock (Col. 2, lines 42-44) and more easily support pipeline stages in the datapath (Col. 2, lines 64-67). Making this modification would be beneficial, as computing on each clock and supporting pipeline stages allows floating-point MAC devices to achieve similar speed performance to fixed point MAC devices but with better precisions (Col. 3, lines 7-11).
Tannenbaum and Tannenbaum in view of Wyland appears to be silent with disclosing receive a first vector and a corresponding second vector each first vector includes a plurality of first vector elements each second vector includes a plurality of second vector elements each first vector element includes a sign an exponent and a mantissa and each second vector element includes a sign an exponent and a mantissa.
Nair discloses receive (co. 5 ln. 59-67, co. 6 ln. 3-9) a first vector (co. 5 ln. 62-65, co. 6 ln. 11-15 ‘first input vector’) and a corresponding second vector (co. 5 ln. 62-65, co. 6 ln. 11-15 ‘second input vector’), each first vector includes a plurality of first vector elements (co. 6 ln. 5-18 ‘first element’), each second vector includes a plurality of second vector elements (co. 6 ln. 5-18 ‘second element’), each first vector element includes a sign, an exponent, and a mantissa, and each second vector element includes a sign, an exponent, and a mantissa (co. 6 ln. 3-18 largest element size of the first input vector and second input vector alike may be 21-bit floating point number, of which is exemplified as “711 and 721” in Fig. 7, co. 14 ln. 13-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Tannenbaum in view of Wyland’s modified vector inner product device with Nair’s receive and vector features because they are in the claimed invention’s same field of endeavor of floating-point computations ([abstract]). It would have been obvious to one of ordinary skill in the art to implement the receive and vector features because it allows data to be parallelized as multiple data vector can be distributed among a plurality of processing units and computed concurrently (co. 6 ln. 41-48). Making this modification would be beneficial, as doing so would improve throughput (co. 6 ln. 41-48), thus one of ordinary skill in the art would look to Nair to incorporate this improvement before the effective filing date.
Regarding claim 5, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Tannenbaum teaches the apparatus wherein:
the computing apparatus (Fig. 3B, 324; Col. 10, lines 42-46; Fig. 5, 500; Col. 13, lines 20-32) is configured to perform a data type transformation (Col. 10, lines 42-49) on product results to enable the addition unit to perform an addition operation (Col. 10, lines 57-59).
The motivation provided with respect to claim 1 equally applies to claim 5.
Regarding claim 8, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Tannenbaum teaches the apparatus wherein:
the floating-point multiplier is used to perform a floating-point number multiplication computation (Col. 9, lines 11-12) according to a computation mode (Col. 3, lines 36-38, 48-51; Col. 4, lines 1-4),
the computing apparatus (Fig. 2A/2B, 205; Col. 4, lines 51-56; Col. 6, lines 9-10; Fig. 5, 500; Col. 13, lines 20-32) is configured to obtain an exponent result (Col. 6, line 11, exponents of input operands) after (Col. 6, lines 4-8) the floating-point number multiplication computation according to the computation mode, (Fig. 1B, Exponent; Col. 3, lines 45-47; Fig. 2A, exponents; Col. 5, lines 4-7; Fig. 2B, [9:0] inputs; Col. 6, lines 9-14); and
the computing apparatus (Fig. 2E, group of 230(0), 235 Unit (0), Fig. 3B, 320; Col. 8, lines 67, Col. 9, lines 1-8; Col. 9, lines 62-65; Fig. 5, 500; Col. 13, lines 20-32) configured to obtain a mantissa result (Col. 8, lines 25-29; Col. 9, lines 4-8) after the floating-point number multiplication computation according to the computation mode, and wherein the computation mode is used to indicate a data format (Col. 3, lines 43-45, 62-64; Col. 4, lines 8-11).
Tannenbaum in view of Wyland in view of Nair disclose the exponent of the first vector element, and the exponent of the corresponding second vector element, the mantissa of the first vector element, and the mantissa of the corresponding second vector element, and the first vector element and corresponding second vector element.
Further, Nair discloses the exponent of the first vector element, and the exponent of the corresponding second vector element, the mantissa of the first vector element, and the mantissa of the corresponding second vector element (co. 6 ln. 3-18 largest element size of the first input vector and second input vector alike may be 21-bit floating point number, of which is exemplified as “711 and 721” in Fig. 7, co. 14 ln. 13-29), and the first vector element (co. 6 ln. 5-18 ‘first element’), and corresponding second vector (co. 6 ln. 5-18 ‘second element’),
The motivation provided with respect to claim 1 equally applies to claim 8.
Regarding claim 9, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Tannenbaum teaches the apparatus wherein:
the computation mode is further used to indicate a data format after the floating-point number multiplication computation (see claim 8 mapping).
The motivation provided with respect to claim 1 equally applies to claim 9.
Regarding claim 10, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Tannenbaum teaches the apparatus wherein:
the data format comprises at least one of a half precision floating-point number, a single precision floating-point number, a brain floating-point number, a double precision floating-point number, or a self-definition floating-point number (Col. 2, lines 58-61; Col. 3, lines 48-51, Col. 4, lines 1-4, half – 16-bit; Col. 3, lines 37-39, single – 32-bit).
The motivation provided with respect to claim 1 equally applies to claim 10.
Regarding claim 11, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Tannenbaum teaches the apparatus wherein:
the floating-point multiplier further (see claim 1 mapping) includes:
a sign processing unit (Fig. 2E, 234; Col. 8, lines 43-45) configured to obtain a sign result (Col. 8, lines 47-53) after the floating-point number multiplication computation (Col. 8, lines 45-47).
Tannenbaum in view of Wyland in view of Nair disclose the sign of the first vector element and the sign of the corresponding second vector element.
Further, Nair discloses the sign of the first vector element and the sign of the corresponding second vector element (co. 6 ln. 3-18 largest element size of the first input vector and second input vector alike may be 21-bit floating point number, of which is exemplified as “711 and 721” in Fig. 7, co. 14 ln. 13-29).
The motivation provided with respect to claim 1 equally applies to claim 11.
Regarding claim 12, in addition to the teachings addressed in the claim 11 analysis, the rejection of claim 11 is incorporated and Tannenbaum teaches the apparatus wherein:
the sign processing unit (Fig. 2E, 234; Col. 8, lines 43-45) includes an exclusive OR logic circuit, wherein the exclusive OR logic circuit is configured to perform an exclusive OR computation, so as to obtain the sign result (Col. 8, lines 43-56) after the floating-point number multiplication computation (see claim 8 mapping).
Tannenbaum in view of Wyland in view of Nair disclose the sign of the first vector element and the sign of the corresponding second vector element. Further, Nair discloses the sign of the first vector element and the sign of the corresponding second vector element (co. 6 ln. 3-18 largest element size of the first input vector and second input vector alike may be 21-bit floating point number, of which is exemplified as “711 and 721” in Fig. 7, co. 14 ln. 13-29).
The motivation provided with respect to claim 1 equally applies to claim 12.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Tannenbaum in view of Wyland in view of Nair and in further view of US 20210303302 A1 Boswell et al. (hereinafter “Boswell”).
Regarding claim 4, in addition to the teachings addressed in the claim 1 analysis, the rejection of claim 1 is incorporated and Tannenbaum in view of Wyland teaches the apparatus wherein:
outputting the product result, the multiplication unit receives corresponding vector elements for a multiplication operation; and outputting the summation result, the addition unit receives from the multiplication unit for an addition operation (see claim 1 mapping).
Tannenbaum and the combination of Tannenbaum in view of Wyland are silent to disclosing after and next pair; after and next product result.
Tannenbaum in view of Wyland in view of Nair in view of Boswell disclose after and next pair; after and next product result.
Boswell teaches after and next pair ([0089-0090]); after and next product result ([0091], [0095]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Tannenbaum in view of Wyland in view of Nair’s vector inner product device with Boswell’s temporal limitations because they are in the claimed invention’s same field of endeavor of matrix multiply-accumulate operations [abstract]. It would have been obvious to one of ordinary skill in the art to implement the temporal limitations as by configuring the units to load the next data to be processed after the previous computation, it allows the system to support various pathways to efficiency. Making this modification would be beneficial, as operations can be accelerated by: reducing bandwidth between calling from memory to inputting ([0089]), executing the datapath in parallel ([0090]), and/or reducing operation size by splitting vectors ([0091]).
Claims 6, 7, 14, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tannenbaum in view of Wyland in view of Nair and in further view of US 20110270902 A1 Dimitrov et al. (hereinafter “Dimitrov”).
Regarding claim 6, in addition to the teachings addressed in the claim 5 analysis, the rejection of claim 5 is incorporated and Tannenbaum in view of Wyland teaches the apparatus further comprising:
the addition unit (see claim 1 mapping).
Tannenbaum and Tannenbaum in view of Wyland are silent to disclosing a multi-level adder group arranged in a multi-level tree structure, wherein each level of the adder group includes one or more first adders.
Tannenbaum in view of Wyland in view of Nair in view of Dimitrov disclose a multi-level adder group arranged in a multi-level tree structure, wherein each level of the adder group includes one or more first adders.
Dimitrov teaches a multi-level adder group arranged in a multi-level tree structure, wherein each level of the adder group includes one or more first adders (Fig. 2, 132, 5 Adders in a row as first level, 2 Adders in a row as next level, 1 Adder in last row; [0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Tannenbaum in view of Wyland in view of Nair’s vector inner product device with Dimitrov’s adder because they are in the claimed invention’s same field of endeavor of floating point arithmetic [0140]. It would have been obvious to one of ordinary skill in the art to implement the adder as it allows the system to perform calculations in parallel without added registers or feedback loops ([0072]). Making this modification would be beneficial, as operations can be accelerated by performing them in parallel while avoiding using unnecessary hardware components.
Regarding claim 7, in addition to the teachings addressed in the claim 6 analysis, the rejection of claim 6 is incorporated. Tannenbaum teaches the computing apparatus (see claim 1 mapping). Tannenbaum and Tannenbaum in view of Wyland are silent to disclosing configured to transform data output by one level of the adder group into another type of data for an addition operation of a next level of the adder group.
Tannenbaum in view of Wyland in view of Nair in view of Dimitrov disclose configured to transform data output by one level of the adder group into another type of data for an addition operation of a next level of the adder group.
Dimitrov teaches configured to transform data output by one level of the adder group into another type of data for an addition operation of a next level of the adder group (Fig. 2, 128, left shifts by 1, by 7, by 14 found between adder levels; [0073]).
The motivation to combine provided with respect to claim 6 equally applies to claim 7.
Regarding claim 14, in addition to the teachings addressed in the claim 7 analysis, the rejection of claim 7 is incorporated and Tannenbaum teaches the apparatus wherein:
the computing apparatus (Fig. 2E, group of 230(0), 235 Unit (0), Fig. 3B, 320; Col. 8, lines 67, Col. 9, lines 1-8; Col. 9, lines 62-65; Fig. 5, 500; Col. 13, lines 20-32) includes a partial product computation unit (Fig. 2E, group of 230(0) and 235; Col. 9, lines 1-8) and a partial product summation unit (Fig. 3B, 320 or 322(H) or 322(L); Col. 9, lines 60-65; Col. 10, lines 1-4), wherein the partial product computation unit is configured to obtain intermediate results (Fig. 3B, outputs from 250; Col. 9, lines 51-56) according (Col. 5, lines 18-21), and the partial product summation unit is configured to sum the intermediate results to obtain the summation result (Fig. 3B, output from 310 M[76:0], Col. 10, lines 8-17) and take the summation result as the mantissa result (Col. 8, lines 25-29; Col. 9, lines 4-8) after (Col. 6, lines 4-8) the floating-point number multiplication computation (Col. 9, lines 11-12).
Tannenbaum in view of Wyland in view of Nair disclose mantissas of the first vector element, and the mantissas of the corresponding second vector element.
Further, Nair discloses mantissas of the first vector element, and the mantissas of the corresponding second vector element (co. 6 ln. 3-18 largest element size of the first input vector and second input vector alike may be 21-bit floating point number, of which is exemplified as “711 and 721” in Fig. 7, co. 14 ln. 13-29).
The motivation provided with respect to claim 1 equally applies to claim 14.
Regarding claim 15, in addition to the teachings addressed in the claim 14 analysis, the rejection of claim 14 is incorporated and Tannenbaum teaches the apparatus wherein:
the partial product computation unit includes a Booth encoding circuit (Fig. 2E, 230(0) and 230(1)… 230(8); Col. 9, lines 1-4), wherein the Booth encoding circuit is configured to fill high and low bits with 0 and perform Booth encoding processing (Col. 6, lines 61-64; Col. 7, lines 53-57), so as to obtain the intermediate results (Fig. 3B, outputs from 250; Col. 9, lines 51-56).
Tannenbaum in view of Wyland in view of Nair disclose mantissas of the first vector element or the mantissas of the corresponding second vector element.
Further, Nair discloses mantissas of the first vector element or the mantissas of the corresponding second vector element (co. 6 ln. 3-18 largest element size of the first input vector and second input vector alike may be 21-bit floating point number, of which is exemplified as “711 and 721” in Fig. 7, co. 14 ln. 13-29).
The motivation provided with respect to claim 1 equally applies to claim 15.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Tannenbaum in view of Wyland in view of Nair and further in view of US 20200026494 A1 Langhammer et al. (hereinafter “Langhammer”).
Regarding claim 13, in addition to the teachings addressed in the claim 8 analysis, the rejection of claim 8 is incorporated and Tannenbaum teaches the apparatus wherein:
the computing apparatus (see claim 1 mapping); the computation mode (see claim 8 mapping).
Tannenbaum in view of Wyland in view of Nair disclose the first vector and the corresponding second vector element.
Further, Nair discloses the first vector (co. 5 ln. 62-65, co. 6 ln. 11-15 ‘first input vector’) and the corresponding second vector (co. 5 ln. 62-65, co. 6 ln. 11-15 ‘second input vector’).
The motivation provided with respect to claim 1 equally applies to claim 13.
Tannenbaum in view of Wyland in view of Nair in view of Langhammer disclose non-normalized and non-zero floating-point numbers; perform normalization processing; to obtain corresponding exponents and corresponding mantissas.
Langhammer discloses non-normalized and non-zero floating-point numbers ([0051-0052] mantissa product of Mx and My; [0056]), perform normalization processing ([0053]); to obtain corresponding exponents and corresponding mantissas ([0053], [0056] exponent; [0054] normalized mantissa).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Tannenbaum in view of Wyland in view of Nair’s vector inner product device with Langhammer’s normalization processing unit because they are in the claimed invention’s same field of endeavor of matrix floating point arithmetic [abstract]. It would have been obvious to one of ordinary skill in the art to implement the normalization processing unit as it allows the system to check for bit alignment and performs adjustments based on the condition ([0053]). Making this modification would be beneficial, as performing normalization ensures correctness of data processed and thus increases the accuracy of the system.
Claims 16, 17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tannenbaum in view of Wyland in view of Nair in view of Dimitrov and in further view of US 20160092167A1 Rarick (hereinafter “Rarick”).
Regarding claim 16, in addition to the teachings addressed in the claim 15 analysis, the rejection of claim 15 is incorporated and Tannenbaum teaches the apparatus wherein:
the partial product summation unit; the intermediate results to obtain the summation result (see claim 14 mapping).
Tannenbaum and Tannenbaum in view of Wyland are silent to disclosing a third adder, wherein the third adder is configured to sum.
Tannenbaum in view of Wyland in view of Nair in view of Dimitrov in view of Rarick disclose a third adder, wherein the third adder is configured to sum.
Rarick teaches a third adder, wherein the third adder is configured to sum (Fig. 3, 215 carry lookahead adder; [0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Tannenbaum in view of Wyland in view of Nair in view of Dimitrov’s vector inner product system with Rarick’s third adder because they are in the claimed invention’s same field of endeavor of floating point operations [abstract]. It would have been obvious to one of ordinary skill in the art to implement the adders as using a carry lookahead adder in this embodiment supports pipeline stages in which operations only take one clock cycle ([0042]). Making this modification would be beneficial, as performing operations that only take one clock cycle promote efficiency in the system and faster computations.
Regarding claim 17, in addition to the teachings addressed in the claim 15 analysis, the rejection of claim 15 is incorporated and Tannenbaum teaches the apparatus wherein:
the partial product summation unit (see claim 14 mapping) includes a Wallace tree (Fig. 3B, 320, 322(H), 322(L); Col. 10, lines 1-4, 33-42), wherein the Wallace tree is configured to sum the intermediate results (Fig. 3B, outputs from 250; Col. 9, lines 51-56) to obtain second intermediate results (Fig. 3B, outputs from 320 or 322(H) or 322(L); Col. 9, lines 39-44, 60-65, 51-56), and the second intermediate results to obtain the summation result (Fig. 3B, output from 310 M[76:0], Col. 10, lines 8-17).
Tannenbaum and Tannenbaum in view of Wyland are silent to disclosing a fourth adder is configured to sum.
Tannenbaum in view of Wyland in view of Nair in view of Dimitrov in view of Rarick disclose a fourth adder is configured to sum.
Rarick teaches a fourth adder is configured to sum (see claim 16 mapping).
Rarick discloses the claimed invention except for an additional adder as the “fourth” adder. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to separable into a plurality of adders, and thus an additional adder as a fourth adder, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179.
The motivation to combine provided with respect to claim 16 equally applies to claim 17.
Regarding claim 18, in addition to the teachings addressed in the claim 16 analysis, the rejection of claim 16 is incorporated. Tannenbaum and Tannenbaum in view of Wyland silent to disclosing the third adder comprises at least one of a full adder, a serial adder, or a carry-lookahead adder.
Tannenbaum in view of Wyland in view of Nair in view of Dimitrov in view of Rarick disclose the third adder includes at least one of a full adder, a serial adder, and a carry-lookahead adder.
Rarick teaches the third adder comprises at least one of a full adder, a serial adder, or a carry-lookahead adder (see claim 16 mapping).
The motivation to combine provided with respect to claim 16 equally applies to claim 18.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tannenbaum in view of Wyland in view of Nair in view of Dimitrov in view of Rarick in further view of Boswell.
Regarding claim 19, in addition to the teachings addressed in the claim 17 analysis, the rejection of claim 17 is incorporated and Tannenbaum teaches the apparatus wherein:
when the number of the intermediate results (Fig. 3B, 3 outputs from 250; Col. 9, lines 51-56) the intermediate results, wherein M is a preset positive integer (Fig. 3B, 320 has 3 inputs; 332(H) has 2 inputs; 332(L) has 2 inputs).
Tannenbaum and Tannenbaum in view of Wyland are silent to disclosing is less than M, a zero value is added as; to make the number equal to M.
Tannenbaum in view of Wyland in view of Nair in view of Dimitrov in view of Rarick in view of Boswell disclose is less than M, a zero value is added as; to make the number equal to M.
Boswell teaches is less than M, a zero value is added as; to make the number equal to M ([0091]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Tannenbaum in view of Wyland in view of Nair in view of Dimitrov in view of Rarick’s vector inner product device with Boswell’s sizing limitations because they are in the claimed invention’s same field of endeavor of matrix multiply-accumulate operations [abstract]. It would have been obvious to one of ordinary skill in the art to implement the sizing limitations as by configuring the data to be sized based off a set length and partitioned, allows the system to support efficiency in processing. Making this modification would be beneficial, as operations can be accelerated by reducing operation size by splitting vectors while maintaining correctness and accuracy with zero-padding ([0091]).
Regarding claim 20, in addition to the teachings addressed in the claim 19 analysis, the rejection of claim 19 is incorporated and Tannenbaum teaches the apparatus wherein:
each Wallace tree has M inputs (Fig. 3B, 320 has 3 inputs; 332(H) has 2 inputs; 332(L) has 2 inputs) and N outputs (Fig. 3B, 320, 332(H), 332(L) all have 1 output), and the number of Wallace trees (Fig. 3B, 3 Wallace Trees), wherein N is a preset positive integer that is less than M, and K is a positive integer that is not less than the biggest bit width of the intermediate results (Fig. 3B, outputs from 250, with 32 bits being the biggest; Col. 9, lines 51-56).
Tannenbaum and Tannenbaum in view of Wyland are silent to disclosing is not less than K.
Tannenbaum in view of Wyland in view of Nair in view of Dimitrov in view of Rarick in view of Boswell disclose is not less than K.
Boswell teaches is not less than K ([0113]).
The motivation to combine provided with respect to claim 19 equally applies to claim 20.
Response to Arguments
35 USC 103.
Applicant’s arguments, see Remarks p. 12, filed 01/06/2026, with respect to the rejection(s) of claim(s) 1, 4-20 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Nair, as necessitated by the amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151