DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on December 10th, 2025, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on December 10th, 2025 is acknowledged and isanswered as follows.
Applicant's remarks, see pg. 6, with respect to the objections of claims 11, 16-18 and 21 under informalities, have been fully considered and are persuasive. Therefore, the objections of these claim have been withdrawn.
Applicant's arguments, see pgs. 6, with respect to the rejections of claims 11-21 under 35 U.S.C 112 (b) have been considered and are persuasive. Therefore, the rejections of these claim have been withdrawn.
Applicant's arguments, see pg. 6, with respect to the rejections of claims under 35 U.S.C 102 (a)(1) have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11-13, 15-17 and 20-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 11 recites the limitation “a shielding region of the first conductivity type” in line 14 which is the same conductivity with “a drift region of a first conductivity type” in line 2. However, according to Applicant’s specification, shielding region 17 has a conductivity of p-doped that is different from the conductivity of drift region 15 of n-doped (see Applicant’s specification, pg. 6, lines 7-8 and pg. 7, lines 15-16). There is no evidence from Applicant’s specification suggesting that shielding region 17 being the first conductivity type (n-doped). Therefore, the new claim 11 contains new matter.
Claims 12-13, 15-17 and 20 are rejected for being depended on claim 11 and having the above issue incorporating into the claims.
Claim 21 recites the limitation “a shielding region of the first conductivity type” in line 17 which is the same conductivity with “a drift region of a first conductivity type” in line 3. However, according to Applicant’s specification, shielding region 17 has a conductivity of p-doped that is different from the conductivity of drift region 15 of n-doped (see Applicant’s specification, pg. 6, lines 7-8 and pg. 7, lines 15-16). There is no evidence from Applicant’s specification suggesting that shielding region 17 being the first conductivity type (n-doped). Therefore, the new claim 21 contains new matter.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 21 recites the limitations “the first lateral surface” and “the second lateral surface” in lines 27-28. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-13, 15-17 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saito et al. (Pub. No.: US 2004/0195618 A1), hereinafter as Saito.
PNG
media_image1.png
485
689
media_image1.png
Greyscale
Regarding claim 11, Saito discloses a semiconductor device in Figs. 10 and 12, comprising: a drift region of a first conductivity type (n type drift layer 11) (see Fig. 12 and [0063]); a channel region of a second conductivity type (p-type base layer 12) on the drift region, the second conductivity type being opposite of the first conductivity type (see Fig. 12 and [0063]); a source region of the first conductivity type (n type source layer 13) on or in channel region (see Fig. 12 and [0063]); a trench which forms an insulated gate (trench which formed gate electrode 24a and insulation film 23a) and extends through the source region and the channel region so that a bottom of the trench is situated in the drift region (see Fig. 12 and [0065]); at least one buried region of the second conductivity type (one of plurality of p-type layer 14B’), which extends within the drift region from an edge region of the drift region (defined by interface between layer 14B’ and drift layer 11) to the trench and is in direct contact with a first subarea of a surface of the trench (plurality of sections of the trench of gate electrode 24a on two lateral surfaces of the trench in which layer 14B’ direct contacts), a second subarea of the surface of the trench (plurality of sections of the trench of gate electrode 24a contacts drift layer 11) being in direct contact with the drift region, and at least one the buried region being connected to the source region in an electrically conducting manner (layer 14B’ electrically connects source 13 through layer 12) (see Fig. 12, [0068] and [0071]); and a shielding region (an upper region of layer 11a’ within opening 14B-----1 of layer 14B’) of the first conductivity type (n-type) directly abuts the bottom of the trench and is disposed beneath the trench (beneath insulation film 23a), wherein the shielding region being positioned such that it is surrounded laterally by the at least one buried region of the second conductivity type within the drift region (the upper region of layer 11a’ being surrounded laterally by layer 14B’), the shielding region being electrically connected to a source potential through the at least one the buried region (the upper region of layer 11a’ electrically connected to potential of source 13 through layer 14B’ and layer 12) (see annotated Fig. 12 above and [0068-0070]), wherein the surface of the trench includes a first lateral surface (one lateral sidewall of the trench of gate electrode 24a) and a second lateral surface (opposite lateral sidewall of the trench of gate electrode 24a) opposite the first lateral surface (see Figs. 10 and 12), wherein the trench extends laterally in a longitudinal direction (x direction) and a transverse direction (y direction) perpendicular to the longitudinal direction, the extension of the trench being longer in the longitudinal direction than in the transverse direction (see Fig. 10), and first subarea sections of the first subarea (plurality of sections of the trench of gate electrode 24a) of the surface of the trench being situated along the longitudinal direction on the first lateral surface (one lateral sidewall of the trench of gate electrode 24a) and on a second lateral surface (opposite lateral sidewall of the trench of gate electrode 24a) (plurality of sections of the trench of gate electrode 24a on two lateral surfaces of the trench in which layer 14B’ direct contacts) (see Figs. 10 and 12).
Regarding claim 12, Saito discloses the semiconductor device as recited in claim 11, wherein the at least one buried region (layer 14B’) extends beneath the trench (see Figs. 10 and 12).
Regarding claim 13, Saito discloses the semiconductor device as recited in claim 11, wherein the at least one buried region includes a multitude of buried regions (plurality of layers 14B’) (see Figs. 10, 12 and [0068-0070]), the first subarea of the surface of the trench including a multitude of the first subarea sections (plurality of sections of the trench of gate electrode 24a on two lateral surfaces of the trench in which layer 14B’ direct contacts) (see Figs. 10 and 12), and the second subarea being situated between the first subarea sections (see Figs. 10 and 12).
Regarding claim 15, Saito discloses the semiconductor device as recited in claim 11, wherein the first subarea sections along the longitudinal direction are alternately situated on the first lateral surface of the trench and on the second lateral surface of the trench (the plurality of sections of the trench of gate electrode 24a alternating on each of the two lateral surfaces of the trench in which layer 14B’ direct contacts) (see Figs. 10 and 12).
Regarding claim 16, Saito discloses the semiconductor device as recited in claim 13, wherein each buried region of the multitude of buried regions is formed in such a way that it encloses an angle with the longitudinal direction of the trench (each of layers 14B’ forming 90o angle with the sidewall of the trench of gate electrode 24a) (see Figs. 10 and 12).
Regarding claim 17, Saito discloses the semiconductor device as recited in claim 16, wherein each buried region of the multitude of buried regions which is in contact with the first subarea sections of the multitude of first subarea sections on the first lateral surface enclose a first angle ᶲ1 with the longitudinal direction of the trench (90o angle on one sidewall of the trench of gate electrode 24a), and each buried region of the multitude of buried regions which is in contact with each first subarea section of the multitude of subarea sections on the second lateral surface of the trench enclose a second angle ᶲ2 with the longitudinal direction of the trench (90o angle on opposing sidewall of the trench of gate electrode 24a) (see Figs. 10 and 12).
Regarding claim 21, Saito discloses a method for manufacturing a semiconductor device in Figs. 10 and 12, comprising the following step: forming a drift region of a first conductivity type (n type drift layer 11) (see Fig. 12 and [0063]); forming at least one buried region of the second conductivity type (one of the plurality of p-type layers 14B’) (see Figs. 10, 12 and [0068], [0071]); forming a channel region of a second conductivity type (p-type base layer 12) on the drift region, the second conductivity type being opposite of the first conductivity type (see Fig. 12 and [0063]); forming a source region of the first conductivity type (n type source layer 13) on or in channel region (see Fig. 12 and [0063]); forming a trench which forms an insulated gate (trench formed gate electrode 24a and insulation film 23a) and extends through the source region and the channel region so that a bottom of the trench is situated in the drift region (see Fig. 12 and [0065]); the at least one buried region of the second conductivity type (p-type layer 14B’) extending within the drift region from an edge region of the drift region (defined by interface between layer 14B’ and drift layer 11) to the trench and is in direct contact with a first subarea of a surface of the trench (plurality of sections of the trench of gate electrode 24a on two lateral surfaces of the trench in which layer 14B’ direct contacts), a second subarea of the surface of the trench (plurality of sections of the trench of gate electrode 24a contacts drift layer 11) being in direct contact with the drift region (see Figs. 10 and 12); connecting the buried region being connected to the source region in an electrically conducting manner (layer 14B’ electrically connects source 13 through layer 12) (see Fig. 12, [0068] and [0071]); and forming a shielding region (an upper region of layer 11a’ within opening 14B-----1 of layer 14B’) of the first conductivity type (n-type) directly abuts the bottom of the trench and is disposed beneath the trench (directly contacts and beneath insulation film 23a), wherein the shielding region being positioned such that it is surrounded laterally by the at least one buried region of the second conductivity type within the drift region (the upper region of layer 11a’ being surrounded laterally by layer 14B’), the shielding region being electrically connected to a source potential through the at least one the buried region (the upper region of layer 11a’ electrically connected to potential of source 13 through layer 14B’ and layer 12) (see annotated Fig. 12 above and [0068-0070]), wherein the trench extends laterally in a longitudinal direction (x direction) and a transverse direction (y direction) perpendicular to the longitudinal direct, the extension of the trench being longer in the longitudinal direction than in the transverse direction (see Fig. 10), and first subarea sections of the first subarea of the surface of the trench (plurality of sections of the trench of gate electrode 24a) being situated along the longitudinal direction on the first lateral surface of the trench (one lateral sidewall of the trench of gate electrode 24a) and on the second lateral surface of the trench (opposite lateral sidewall of the trench of gate electrode 24a) (plurality of sections of the trench of gate electrode 24a on two lateral surfaces of the trench in which layer 14B’ direct contacts) (see Figs. 10 and 12).
Allowable Subject Matter
Claims 18-19 would be allowed if rewritten to overcome the objections and the rejections under 35 U.S.C. 112, set forth in this office action.
The following is an examiner' s statement of reason for allowance: the prior art made of record does not teach or fairly suggest the following: wherein ᶲ1 =45o + α and ᶲ2 = 45o - α for 00< α < 45o as in claim 18. Claim 19 depends on claim 18, and therefore also include said claimed limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CUONG B NGUYEN/Primary Examiner, Art Unit 2818