DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 05/10/2023.
Currently claims 1-17 are pending in the application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/23/2021 and 05/12/2024 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2020/0091244 A1 (Chan) .
Regarding claim 1, Chan discloses, a selector material (38; lower chalcogenide element; Fig. 2D; [0038]), wherein the selector material (38) comprises at least one of Te, Se and S ([0051]).
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Note: Chan teaches para. [0051] that a lower chalcogenide material 38a forms a two terminal selector device comprising the selector node 38 connected to bottom and middle electrodes 40 and 36. Such a selector device is sometimes referred to as an Ovonic Threshold Switch (OTS). Chan teaches that materials suitable for forming an OTS (include Te—As—Ge—Si, Ge—Te—Pb, Ge—Se—Te, Al—As—Te, Se—As—Ge—Si, Se—As—Ge—C, Se—Te—Ge—Si, Ge—Sb—Te—Se, Ge—Bi—Te—Se, Ge—As—Sb—Se, Ge—As—Bi—Te, and Ge—As—Bi—Se, among others.
Regarding claim 6, Chan discloses, the selector material according to claim 1, wherein the selector material has nonlinear conductivity characteristics to be used in a neural network as a neural component; and/or, the selector material (38) has ovonic threshold switching type selection characteristics (Fig. 2D; [0051]).
Note: Chan teaches para. [0051] that a lower chalcogenide material 38a forms a two terminal selector device comprising the selector node 38 connected to bottom and middle electrodes 40 and 36. Such a selector device is sometimes referred to as an Ovonic Threshold Switch (OTS).
Allowable Subject Matter
Claims 2-5 and 7-17 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 2, the closest prior art, US 2020/0091244 A1 (Chan), in combination with, fails to disclose, “the selector material according to claim 1, wherein the chemical formula of the selector material is
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wherein M comprises doping materials, and 0 < x < 100, 0 < y < 100, 0 < z < 100, 0 < t < 0.5”, in combination with the additionally claimed features, as are claimed by the Applicant.
Claims 3-5 and 7-17 are also allowable due to their dependence on an allowable base claim.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2020/0075675 A1 (Wu) - A memory device is disclosed including first conductive lines extending in a first direction, second conductive lines extending in a second direction, and a plurality of memory cells each arranged between the first and second conductive lines and each including a variable resistance memory layer and a switch material pattern. The switch material pattern includes an element injection area arranged in an outer area of the switch material pattern, and an internal area covered by the element injection area. The internal area contains a first content of at least one element from arsenic (As), sulfur (S), selenium (Se), and tellurium (Te), the element injection area contains a second content of the at least one element from As, S, Se, and Te, and the second content has a profile in which a content of the at least one element decreases away from the at least one surface of the switch material pattern.
US 2019/0355789 A1 (Donghi) - A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction
US 2019/0252609 A1 (Sei) - A switch device is disclosed including: a first electrode; a second electrode opposed to the first electrode; and a switch layer provided between the first electrode and the second electrode, and the switch layer includes one or more kinds of chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S) and one or more kinds of first elements selected from phosphorus (P) and arsenic (As), and further includes one or both of one or more kinds of second elements selected from boron (B) and carbon (C) and one or more kinds of third elements selected from aluminum (Al), gallium (Ga), and indium (In).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
12/18/2025