The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-11 and 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (CH 111584562, see US 2022/0140046)).Regarding claim 7, Zhou et al. teach in figure 2 and related text a display panel, comprising:
a first substrate 10 on which a plurality of pixel units (inherently therein) are disposed, each of the pixel units comprising a light-emitting area AA and a vacant area NA,
wherein a light-emitting diode (LED) chip (located in the TFT array substrate 21) and a pixel driving circuit (not shown connected to external terminals 112) for driving the LED chip to emit light are disposed in the light-emitting area AA, the vacant area NA is an area where the pixel driving circuit and the LED chip are not provided, and
at least a conductive hole 21a is located in the vacant area NA of at least some of the pixel units; and
a second substrate (the rest of the structure, away from the first substrate 10) disposed on a side of the first substrate facing away from the pixel units,
the second substrate comprises a second base 122, a second buffer layer 221, and a bonding conductive layer 112, the bonding conductive layer 112 is disposed on the second base 122 at a side close to the first substrate, the bonding conductive layer 112 is in contact with and covered by the second buffer layer 221, and
the pixel driving circuit is electrically connected to the bonding conductive layer through the conductive hole 21a.
Zhou et al. do not explicitly state using a plurality of pixel units.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a plurality of pixel units in Zhou et al.’s device, in order to be able to use the device in practical application.
Regarding the claimed limitations of forming a first substrate and a second substrate, these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
The formation of a first substrate and a second substrate does not produce a structure which is different from a structure which is formed using only one substrate.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Regarding claims 1,16 and 17, Zhou et al. teach in figure 2 and related text substantially the entire claimed structure, as applied to claim 7 above, including having the conductive hole being filled with a conductive material, and wherein an orthographic projection of the second substrate on the first substrate is located in the first substrate.
Zhou et al. do not explicitly state that the conductive hole is filled with a conductive adhesive.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a conductive adhesive in Zhou et al.’s device in order to improve the structural integrity of the device.
Regarding claims 2 and 8, Zhou et al. teach in figure 2 and related text that the first substrate further comprises a plurality of contact terminals 112 disposed corresponding to a plurality of conductive holes, and one end of each of the contact terminals is electrically connected to the pixel driving circuit; and the bonding conductive layer 112 comprises a plurality of bonding terminals 112 and a plurality of bonding traces 111, one end of each of the bonding traces is electrically connected to a corresponding one of the bonding terminals, and another end of the bonding trace is electrically connected to another end of the contact terminal 112 through a corresponding one of the conductive holes 21a.
Regarding claims 3 and 9, Zhou et al. teach in figure 2 and related text that the bonding traces comprise a plurality of fan-out traces 111, the pixel driving circuit comprises a source and drain metal layer, and the source and drain metal layer 211 comprises a plurality of data lines, wherein each of the data lines is electrically connected to a corresponding one of the fan-out traces 111 through a corresponding one of the conductive holes 21a.
Regarding claims 4 and 10, Zhou et al. teach in figure 2 and related text a gate driving circuit (not shown), but does not each that the bonding traces comprise a plurality of clock signal lines, and the gate driving circuit is electrically connected to the clock signal lines through the conductive holes. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a plurality of clock signal lines, and the gate driving circuit is electrically connected to the clock signal lines through the conductive holes in Zhou et al.’s device in order to be able to operate the device in its intended use.
Regarding claims 5 and 11, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the gate driving circuit comprises a plurality of cascaded circuit units, in Zhou et al.’s device in order to use the device in an application which requires specific characteristics. In the combined device, each of the circuit units is located in the vacant area.
Regarding claim 13, Zhou et al. teach in figure 2 and related text that the first substrate comprises a first side and a second side disposed opposite to each other, some of the conductive holes are located close to the first side, and some of the conductive holes are located close to the second side.
Regarding claim 14, Zhou et al. teach in figure 2 and related text that the second substrate comprises a first fan-out area and a second fan-out area (by arbitrarily dividing the fan-out area into two sections), an orthographic projection of the first fan-out area on the first substrate is close to the first side, and an orthographic projection of the second fan-out area on the first substrate is close to the second side; and a driving chip (not shown) is further provided on the second substrate, electrically connected to the bonding terminals. Zhou et al. do not teach that the driving chip is disposed between the first fan-out area and the second fan-out area. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to dispose the driving chip between the first fan-out area and the second fan-out area in Zhou et al.’s device in order to arrange the elements in the device by doing experimentation and optimization.
Regarding claim 15, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the number of the conductive holes greater than or equal to number of the bonding traces, in Zhou et al.’s device in order to provide adequate number of the conductive holes to the number of the bonding traces.
Regarding claim 18, Zhou et al. teach in figure 2 and related text that the first substrate further comprises a first base (the bottom substrate) and a first buffer layer 222, the first buffer layer is disposed on a side of the first base away from the second substrate, and the pixel driving circuit 21 is arranged on a side of the first buffer layer away from the second substrate; wherein the pixel driving circuit comprises: a semiconductor layer 212 disposed on the side of the first buffer layer away from the second substrate; a first gate insulating layer 213 covering the semiconductor layer and the first buffer layer; a first gate layer 214 disposed on the first gate insulating layer; a second gate insulating layer 215 covering the first gate layer and the first gate insulating layer; a second gate layer 216 disposed on the second gate insulating layer; an interlayer dielectric layer 217 covering the second gate layer and the second gate insulating layer; and a source and drain metal layer 211 arranged on the interlayer dielectric layer; wherein the conductive hole 21a penetrates the interlayer dielectric layer, the first gate insulating layer, the second gate insulating layer, and the first buffer layer.
Regarding claim 19, Zhou et al. teach in figure 2 and related text that the second buffer layer further covers the second base and the conductive hole 21a extends from the first substrate to the second substrate and penetrates the second buffer layer. 224
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection based on the new numerals in the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
1/5/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800