Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9, 13, 15-16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Miyamoto et al. (CN-101238561-A referred as Miyamoto).
Regarding claim 1. Miyamoto discloses a semiconductor device, comprising: a first nitride-based semiconductor layer disposed above a substrate ([page 41, lines 24-27], figure 3, a first nitride-based semiconductor layer #132 containing GaN is disposed above a substrate #110);
a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer ([page 41, lines 24-27], figure 3, a second nitride-based semiconductor layer #133 containing AlGaN is disposed on the first nitride-based semiconductor layer #132. Please note that #133 containing AlGaN (4.0 eV) has a greater bandgap than the #132 containing GaN (3.2 eV) as known in the art);
a first electrode and a second electrode disposed above the second nitride-based semiconductor layer ([page 42, lines 1-3], figure 3, a first electrode #114 and a second electrode #112 is seen disposed above the second nitride-based semiconductor layer #133);
a first gate electrode disposed above the second nitride-based semiconductor layer and between the first and second electrodes ([page 41, lines 24-27], figure 3, a first gate electrode #113 is disposed above the second nitride-based semiconductor layer #133 and between the first electrode #114 and the second electrode #112);
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a first field plate disposed over the second nitride-based semiconductor layer and extending from a region between the first electrode and the first gate electrode to a region directly over the first gate electrode ([page 42, lines 7-11], figure 3 annotated above, a first field plate #116 is seen disposed over the second nitride-based semiconductor layer #133 and extending from a region between the first electrode #114 and first gate electrode #113 (specifically seen in the perspective #Ref1) to a region directly above the first gate electrode #113); and
a second field plate disposed over the second nitride-based semiconductor layer and extending from a region between the first electrode and the first field plate to a region directly over the first field plate, wherein the second field plate is horizontally spaced away from the first gate electrode ([page 42, lines 7-11], figure 3, a second field plate #118 is seen disposed over the second nitride-based semiconductor layer #133 and extending from a region between the first electrode #114 and the first field plate #116 to a region directly over the first field plate #116. It is also seen that the second field plate #118 is horizontally spaced away from the first gate electrode #113, more emphasized with the spacer #117 in between).
Regarding claim 9. Miyamoto discloses a dielectric layer between the first and second field plates to vertically isolate the first and second field plates ([page 44, lines 1-6], figure 3, a dielectric layer #117 is in between the first field plate #116 and the second field plate #118 to vertically isolate both field plates).
Regarding claim 13. Miyamoto discloses wherein the first field plate has a thickness different than a thickness of the second field plate ([page 42, lines 7-11], figure 3, the first field plate #116 has a different thickness than the second field plate #118 as illustrated).
Regarding claim 15. Miyamoto discloses wherein the second field plate has a width greater than an overlapping width between the first and second field plates ([page 42, lines 7-11], figure 3, the second field plate #118 has a width greater than the overlapping width between the first #116 and second field plates #118).
Regarding claim 16. Miyamoto discloses a method for manufacturing a semiconductor device, comprising:
forming a first nitride-based semiconductor layer over a substrate ([page 41, lines 24-27], figure 3, a first nitride-based semiconductor layer #132 containing GaN is disposed above a substrate #110);
forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer ([page 41, lines 24-27], figure 3, a second nitride-based semiconductor layer #133 containing AlGaN is disposed on the first nitride-based semiconductor layer #132);
forming a gate electrode over the second nitride-based semiconductor layer ([page 41, lines 24-27], figure 3, a gate electrode #113 is disposed above the second nitride-based semiconductor layer #133);
forming a first field plate over the second nitride-based semiconductor layer and extending to a region directly over the gate electrode ([page 42, lines 7-11], figure 3, a first field plate #116 is seen disposed over the second nitride-based semiconductor layer #133 and extending to a region directly over the gate electrode #113); and
forming a second field plate over the second nitride-based semiconductor layer and extending to a region directly over the first field plate such that the first field plate is located between the gate electrode and the second field plate ([page 42, lines 7-11], figure 3, a second field plate #118 is seen disposed over the second nitride-based semiconductor layer #133 and extending to a region directly over the first field plate #116. It is also seen that the first field plate #116 is in between the gate electrode #113 and the second field plate #118).
Regarding claim 20. Miyamoto discloses forming a first electrode and a second electrode over the second nitride-based semiconductor layer ([page 42, lines 1-3], figure 3, the first electrode #114 and the second electrode #112 are formed over the second-nitride based semiconductor layer #133), wherein the gate electrode is located between the first and second electrodes, and the first electrode is closer to the gate electrode than the second electrode ([page 42, lines 1-3], figure 3, the gate electrode #113 sits in between and is closer to the first electrode #114 than the second electrode #112).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. (CN-101238561-A referred as Miyamoto) in view of Ohno et al. (US-20220093747-A1 referred as Ohno).
Regarding claim 2. Miyamoto lacks wherein an entirety of the second field plate is located between the first electrode and the first field plate.
Ohno discloses wherein an entirety of the second field plate is located between the first electrode and the first field plate ([0035], figure 1, the entirety of the second field plate #9 is located in between the first electrode #7 and the first field plate #10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Miyamoto to include the entirety of the second field plate is located between the first electrode and the first field plate as taught by Ohno in order to distribute the weight of the device, allow for additional elements therein between for added functionality, and to increase the devices versatility.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. CN-101238561-A referred as Miyamoto) in view of Then et al. (US-20230090106-A1 referred as Then).
Regarding claim 3. Miyamoto discloses wherein the first field plate comprises: a second portion at the region directly over the first gate electrode and in a position higher than the first gate electrode ([page 42, lines 7-11], figure 3, a second portion at a region directly over the first gate electrode #113 and in a position higher than the first gate electrode #113).
Miyamoto lacks wherein the first field plate comprises: a first portion at the region between the first electrode and the first gate electrode and in a position lower than the first gate electrode.
Then discloses wherein the first field plate comprises: a first portion at the region between the first electrode and the first gate electrode and in a position lower than the first gate electrode ([0097], figure 4, a first portion of the first field plate #416 is in between the first electrode #422 and the gate electrode #414B and also in a position lower than the first gate electrode #414B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Miyamoto to include the first field plate comprising a first portion at the region between the first electrode and the first gate electrode as taught by Then in order to reduce signal interference, allow for additional electrical insulation, and to distribute the weight of the device.
Regarding claim 4. Miyamoto as modified discloses wherein the second field plate vertically overlaps with the second portion of the first field plate ([page 42, lines 7-11], figure 3, the second field plate #118 vertically overlaps the second portion of the first field plate #116. Emphasized with a spacer #117 therein between).
Regarding claim 5. Miyamoto as modified discloses wherein the second field plate is horizontally spaced away from the second portion of the first field plate ([page 42, lines 7-11], figure 3, the second field plate #118 is horizontally spaced away from the second portion of the first field plate #116. Emphasized with a spacer #117 therein between).
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. CN-101238561-A referred as Miyamoto) and Then et al. (US-20230090106-A1 referred as Then) as applied to claim 3, in further view of Isobe et al. (US-20220293745-A1 referred as Isobe).
Regarding claim 6. Miyamoto as modified lacks wherein the first portion has a first height with respect to the second nitride-based semiconductor layer, wherein the second portion has a second height with respect to the second nitride-based semiconductor layer, wherein the second field plate has a third height with respect to the second nitride-based semiconductor layer, and the third height is greater than the first height and less than the second height.
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Isobe discloses wherein the first portion has a first height with respect to the second nitride-based semiconductor layer ([0040], figure 1 annotated above, the first field plate #50 contains a first portion at label #51 with a first height #H1 with respect to the second nitride-based semiconductor layer #8), wherein the second portion has a second height with respect to the second nitride-based semiconductor layer ([0040], figure 1 annotated above, the first field plate #50 contains a second portion at label #52 with a second height #H2 with respect to the second nitride-based semiconductor layer #8), wherein the second field plate has a third height with respect to the second nitride-based semiconductor layer, and the third height is greater than the first height and less than the second height ([0038], figure 1 annotated above, the second field plate #40 has a third height #H3 with respect to the second nitride-based semiconductor layer #8. It is illustrated that the third height #H3 is greater than the first height #H1 but less than second height #H2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Miyamoto as modified to include further modify the heights of the first field plate and the second field plate as taught by Isobe in order to increase the devices versatility, reduce device failure, and to enhance the devices integrity.
Regarding claim 7. Miyamoto as modified lacks wherein the first field plate further comprises: a third portion connecting the first portion to the second portion and extending upward to get higher than the first gate electrode.
Isobe discloses wherein the first field plate further comprises: a third portion connecting the first portion to the second portion and extending upward to get higher than the first gate electrode ([0040], figure 1 annotated above, the first field plate #50 comprises a third portion #3P connecting the first portion #51 and the second portion #52 therein between and also extending upwards to get higher than the first gate electrode #20 (further described in [0037])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Miyamoto as modified to further include a third portion to the first field plate as taught by Isobe in order to increase the devices versatility, enhance the devices usability, and to simplify the device design.
Regarding claim 8. Miyamoto as modified lacks wherein the second field plate is horizontally spaced away from the third portion of the first field plate.
Isobe discloses wherein the second field plate is horizontally spaced away from the third portion of the first field plate ([0040], figure 1, the second field plate #40 is horizontally spaced away from the third portion #3P of the first field plate #50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Miyamoto as modified to further include the second field plate spaced away from the third portion of the field plate as taught by Isobe in order to reduce signal interference, allow for additional electrical safety, and to spread out the thermal heat.
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. CN-101238561-A referred as Miyamoto) in view of Byun et al. (US-20230115802-A1 referred as Byun).
Regarding claim 10. Miyamoto lacks a third electrode disposed above the second nitride-based semiconductor layer, wherein the second electrode is located between the first and third electrodes; and a second gate electrode disposed above the second nitride-based semiconductor layer and located between the second and third electrodes.
Byun discloses a third electrode disposed above the second nitride-based semiconductor layer, wherein the second electrode is located between the first and third electrodes ([0084], figure 6, a third electrode #SE3 is disposed above the second nitride-based semiconductor layer #BUF. The second electrode #SE2 is located in between the first electrode #SE1 and the third electrode #SE3); and a second gate electrode disposed above the second nitride-based semiconductor layer and located between the second and third electrodes ([0084], figure 6, a second gate electrode #GAT2 is disposed above the second nitride-based semiconductor layer #BUF and located in between the second electrode #SE2 and the third electrode #SE3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Miyamoto to further include a third electrode and a second gate electrode as taught by Byun in order to improve device performance, reduce stress points in one gate electrode, and to distribute the workload across the device.
Regarding claim 12. Miyamoto as modified discloses wherein the second electrode is closer to the first gate electrode than the first electrode ([page 42, lines 1-3], figure 3, the second electrode #112 is closer to the first gate electrode #113 than the first electrode #114).
Miyamoto as modified lacks wherein the second electrode is closer to the second gate electrode than the third electrode.
Byun discloses wherein the second electrode is closer to the second gate electrode than the third electrode ([0084], figure 6, the second electrode #SE2 is closer to the second gate electrode #GAT2 than the third electrode #SE3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Miyamoto as modified to further include the second electrode is closer to the second gate electrode than the third electrode as taught by Byun in order to reduce signal interference, allow for additional insulation, and to reduce device failure.
Claims 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. CN-101238561-A referred as Miyamoto) in view of Bothe et al. (US-20220130965-A1 referred as Bothe).
Regarding claims 14 and 19. Miyamoto lacks
[claim 14] wherein the first and second field plate are electrically connected to the same conductive layer.
[claim 19] electrically connecting the first and second field plates to the same conductive pad.
Bothe discloses
[claim 14] wherein the first and second field plate are electrically connected to the same conductive layer ([0071], figure 5B, the first field plate #240-1 and the second field plate #240-2 are electrically connected to the same conductive layer #235 as described).
[claim 19] electrically connecting the first and second field plates to the same conductive pad ([0071], figure 5B, the first field plate #240-1 and the second field plate #240-2 are electrically connected to the same conductive pad #235 as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Miyamoto to further include the first and second field plate are electrically connected to the same conductive layer as taught by Byun in order to allow connection through an insulating layer, enhanced versatility, and increased device safety.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. (CN-101238561-A referred as Miyamoto) in view of Du et al. (US-20220293779-A1 referred as Du).
Regarding claims 17 and 18. Miyamoto lacks
[claim 17] wherein forming the second field plate comprises: patterning a conductive layer to form the second field plate horizontally spaced away from the gate electrode.
[claim 18] wherein forming the second field plate comprises: patterning a conductive layer to form the second field plate in a position lower than a top surface of the first field plate.
Du discloses
[claim 17] wherein forming the second field plate comprises: patterning a conductive layer to form the second field plate horizontally spaced away from the gate electrode ([0048], figure 7-8, patterning the conductive layer #122 to form a second field plate #150 horizontally (x-axis) spaced away from the gate electrode #120).
[claim 18] wherein forming the second field plate comprises: patterning a conductive layer to form the second field plate in a position lower than a top surface of the first field plate ([0048], figure 7-8, patterning the conductive layer #122 to form a second field plate #150 to be in a position lower than a top surface of the first field plate #133 seen in figure 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Miyamoto to further include patterning a conductive layer to form the second field plate under positioning constraints as taught by Du in order to reduce the total device weight, enhance the manufacturing speed, and to allow for additional electrical insulation therein between.
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes Remaud et al. (US-20230124686-A1) and Zhao et al. (US-20230095367-A1) for the nitride-based layers, gate electrodes, and field plates.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818