Prosecution Insights
Prosecution Insights
Tech Center 2800 • Art Units: 2818
This examiner grants 100% of resolved cases
Jacob Raul Marin has resolved 23 cases in Art Unit 2818 of Tech Center 2800. His allowance rate is 100.0 percent. This 100.0 percent rate is a metric for practitioners to consider when evaluating the examiner's history. The data also shows an interview lift of 0.0 percent. This lift indicates the change in allowance probability associated with an interview in this art unit.
The median days to allowance is 1196. This 1196-day figure represents the duration of the prosecution process for cases that reach a grant. Practitioners should consider the 23 resolved cases as the current record of the examiner's work. The 100.0 percent allowance rate and 0.0 percent interview lift are components of the examination profile. The median pendency is a factor for managing client expectations.
Direct communication is a documented tactic, as shown by the lift. Applicants should review the allowance rate as they prepare their prosecution strategy. The cases provide a data set for understanding the examiner's approach in Tech Center 2800. The timeline is a measure of the time required to navigate Art Unit 2818 to a successful conclusion.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18634325 | SEMICONDUCTOR DEVICE | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18386654 | SEMICONDUCTOR DEVICE | Final Rejection | Samsung Electronics Co., Ltd. |
| 18371258 | SEMICONDUCTOR PACKAGE | Non-Final OA | SAMSUNG ELECTRONICS CO, LTD. |
| 18668809 | CHIP PACKAGE STRUCTURE WITH ADHESIVE WALL STRUCTURE AND METHOD FOR FORMING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18639105 | SEMICONDUCTOR STRUCTURE WITH REDUCED CURRENT LEAKAGE AND METHOD FOR MANUFACTURING THE SAME | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18489365 | MULTI-PORT SRAM CELL WITH DUAL SIDE POWER RAILS | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18177909 | SEMICONDUCTOR STRUCTURE WITH DIELECTRIC SPACER AND METHOD FOR MANUFACTURING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 17833440 | BOTTOM DIELECTRIC ISOLATION AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS | Final Rejection | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18680053 | SEMICONDUCTOR PACKAGE STRUCTURE WITH INTERPOSER DIES | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
| 18500605 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF | Non-Final OA | NANYA TECHNOLOGY CORPORATION |
| 18286691 | SILICON WAFER MANUFACTURING METHOD | Final Rejection | SHIN-ETSU HANDOTAI CO., LTD. |
| 18377399 | COMPONENT PACKAGE SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF | Final Rejection | Zhuhai ACCESS Semiconductor Co., Ltd |
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