DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Cross-Reference to Related Applications
2. This application is a 371 of PCT/CN2021/140729 12/23/2021.
Oath/Declaration
3. The oath/declaration filed on 09/14/2022 is acceptable.
Priority
4. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
5. The office acknowledges receipt of the following items from the applicant:
Information Disclosure Statement (IDS) filed on 11/30/2022 and 04/29/2024.
Specification
6. The specification is objected to for the following reason: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP 606.01).
Claim Objections
7. Claims 1, 9 and 17 are objected to because of the following reasons:
In claim 1, line 13, in claim 9, line 14 and in claim 17, line 16, a term of “the first via” should replace by – the first via hole --.
Claim Rejections-35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
8. Claims 8 and 16 are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 8 and claim 16 recite the limitation "the signal input pad" in line 2. There is insufficient antecedent basis for this limitation in the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless --
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. Claims 1, 7 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIN G (CN-113097412-A).
Regarding claim 1, LIN G discloses an organic light-emitting diode display panel, comprising:
a substrate (210);
a thin film transistor device disposed on the substrate, wherein the thin film transistor device comprises an active layer (including a plurality of first semiconductor units 241), a gate layer (260), a source (280), and a drain )280);
an auxiliary electrode (300) arranged in a same layer as the source (280) and the drain (280);
a passivation layer (410) disposed on the source (280), the drain (280), and the auxiliary electrode (300);
a planarization layer (420) disposed on the passivation layer (410); and
a light-emitting device layer (510/520/530) disposed on the planarization layer (420), wherein the light- emitting device layer (510/520/530) comprises an anode layer (510), a light-emitting functional layer (corresponding to 520, see XU C (CN-119947438-A)), and a cathode layer (530);
wherein a first via hole (710) penetrating the planarization layer (420) and the passivation layer (410) is defined above the auxiliary electrode (300), and a notch (722) between the auxiliary electrode (300) and the planarization layer (420) is defined at a bottom of an inner sidewall of the first via hole (710); and
wherein the cathode layer (530) extends through the first via hole (710) to the notch (722) to connect with the auxiliary electrode (530) (Fig. 3 and English Text).
Regarding claim 7, LIN G discloses wherein a thickness of the planarization layer (420) ranges from 1 micrometer to 4 micrometers (Fig. 3 and English Text).
Regarding claim 9, LIN G discloses a organic light-emitting diode display panel, comprising:
a substrate (210);
a thin film transistor device disposed on the substrate, (210) wherein the thin film transistor device comprises an active layer (including a plurality of first semiconductor units 241), a gate layer (260), a source (280), and a drain (280);
an auxiliary electrode (300) arranged in a same layer as the source (280) and the drain (280);
a passivation layer (410) disposed on the source (280), the drain (280), and the auxiliary electrode (300);
a planarization layer (420) disposed on the passivation layer (410), wherein a thickness of the planarization layer (420) ranges from 1 micrometer to 4 micrometers; and
a light-emitting device layer disposed on the planarization layer (420), wherein the light- emitting device layer comprises an anode layer (510), a light-emitting functional layer (corresponding to 520, see XU C (CN-119947438-A)), and a cathode layer (530);
wherein a first via hole (710) penetrating the planarization layer (420) and the passivation layer (410) is defined above the auxiliary electrode (300), and a notch (722) between the auxiliary electrode (300) and the planarization layer (420) is defined at a bottom of an inner sidewall of the first via hole (710);
wherein the cathode layer (530) extends through the first via hole (710) to the notch (722) to connect with the auxiliary electrode (300); and
wherein the light-emitting functional layer (520) covers a partial area of the auxiliary electrode (300) corresponding to the first via hole (710), and the cathode layer (530) covers another partial area of the auxiliary electrode (300) in the notch (722) (Fig. 3 and English Text).
Regarding claim 10, LIN G discloses further comprising: a buffer layer (230) disposed between the substrate (210) and the thin film transistor device; and an interlayer dielectric layer (270) disposed on the buffer layer (230) (Fig. 3 and English Text).
10. Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE J (CN-108155299-A).
Regarding claim 17, LEE J discloses a manufacturing method of an organic light-emitting diode display panel, comprising:
providing a substrate (10);
forming a thin film transistor device (T) and an auxiliary electrode (31) on the substrate (10);
sequentially forming a passivation layer (14) and a planarization layer (15) on the thin film transistor device (T) and the auxiliary electrode (31);
defining a first via hole (37) penetrating the planarization layer (15) above the auxiliary electrode (31), and defining a second via hole (H3) penetrating the planarization layer (15) and the passivation layer (14) above a source (24, changing location between source (23) and drain (24)) of the thin film transistor device (T);
forming an anode layer (40) on the planarization layer (15), and connecting the anode layer (40) to the source (24) through the second via hole (H3);
performing a wet etching process on the passivation layer (14) in the first via hole (37) to form a notch between the auxiliary electrode (31) and the planarization layer (15);
forming a pixel definition layer (43) on the planarization layer (15) to define a light-emitting area and a notch forming area;
forming a light-emitting functional layer ((corresponding to 41, see XU C (CN-119947438-A)) on the substrate (10) to cover a part of an area of the auxiliary electrode (31) corresponding to the first via hole (37) in the first via hole (37); and
forming a cathode layer (42) on the light-emitting functional layer (41) and extending the cathode layer (42) to cover another part of the area of the auxiliary electrode (31) in the notch (Fig. 1 and English Text).
Allowable Subject Matter
11. The following is a statement of reason for the indication of allowable subject matter:
Claims 2-6, 11-15 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHUC T DANG/Primary Examiner, Art Unit 2897