DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-9, 12, 13, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Pub. 2010/0176383) in view of Cai (CN106205495A) and/or Gupta et al. (US Pub. 2018/0033805) and Shin et al. (US Pub. 2015/0102332).
Regarding independent claim 1, Park teaches as display panel (Figs. 1-3; para. 0026+), comprising:
a first thin-film transistor (110) comprising a first source (113), a first drain (the other 113), a first active layer (112b), and a first gate (111); and
a second thin-film transistor (120) comprising a second source (123), a second drain (the other 123), a second active layer (122), and a second gate (121);
wherein the first thin-film transistor further comprises a third active layer (112a), the third active layer and the first active layer are laminated, and non-channel regions on two ends of the third active layer are respectfully electrically connected to non-channel regions on two ends of the first active layer (Fig. 2), wherein a material of the first active layer of the first thin-film transistor is same as a material of the second active layer of the second thin-film transistor (para. 0035); and
wherein an average electron mobility of the first active layer and the third active layer of the first thin-film transistor is greater than the electron mobility of the second active layer of the second thin-film transistor (para. 0038).
While Park is not explicitly clear how the scan/data driving transistor (claimed “first thin-film transistor” 110) and the LED driving transistor (claimed “second thin-film transistor” 120) are connected, a traditional 2T1C pixel drive circuit is known in the art as shown in Fig. 1 of Cai and Fig. 2 of Gupta. It would have been obvious to one of ordinary skill in the art at the time of filing to look to Cai and/or Gupta to provide that which was missing from Park; that is, for the purpose of providing a clear connection configuration of the transistor(s)/pixels such that wherein the first drain of the first thin-film transistor is electrically connected to the second gate of the second thin-film transistor as claimed.
Park in view of Cai and/or Gupta are silent with respect to “threshold voltage offset”.
Shin teaches that threshold voltage offset is generally undesirable and ideally minimized or non- existent in order to avoid stain or deviation of luminance that may be visible on the screen (para. 0007- 0008). Furthermore, given that “threshold voltage offset” is being interpreted as “a difference between a desired/designed threshold voltage and the actual/real-life threshold voltage” -- common sense would provide that it would be desirable to have this value be as small as possible or non-existent because of course one would not want an actual/real-life value to be different from a desired/designed for value.
It would have been obvious to one of ordinary skill in the art at the time of filing to optimize the threshold voltage offsets such that they were as small as possible or even zero such that the limitations of the threshold voltage offset of the second active layer of the second thin-film transistor is less than or equal (that is, having both being zero/non-existent) to an average threshold voltage offset of the first active layer and the third active layer of the first thin-film transistor are met for the purpose of providing a reliable device that operates as designed without stain or deviation of luminance that can occur if the threshold voltage offset was too high.
Re claim 4, the combination of Park and Shin makes obvious wherein the threshold voltage offset of the second active layer of the second thin-film transistor is as small as possible or non-existent such that it was “less than or equal to 1 V” as claimed for the purpose of providing a reliable device that operates as designed without stain or deviation of luminance that may occur if the threshold voltage offset was too high (Shin para. 0007-0008).
Re claim 5, Park teaches wherein a material of the first active layer of the first thin-film transistor comprises one or more of indium oxide, gallium oxide, zinc oxide, and combinations thereof (para. 0034).
Re claim 6, Park teaches wherein a material of the second active layer of the second thin-film transistor comprises metal oxide doped with rare-earth metal element (para. 0035; for example, zinc oxide doped with gadolinium (Gd)).
Re claim 7, the combination of Park in view of Cai and/or Gupta teaches further comprising: a data line electrically connected to the first source of the first thin-film transistor; a scan line electrically connected to the first gate of the first thin-film transistor; and a light-emitting unit comprising a first electrode and a second electrode opposite to the first electrode, wherein the first electrode is electrically connected to the second source of the second thin-film transistor (Park Fig. 2, para. 0028-0029; Cai Fig. 1; and Gupta Fig. 2).
Re claim 8, the combination of Park in view of Cai and/or Gupta teaches further comprising: a capacitor comprising a first plate and a second plate opposite to the first plate, wherein the first plate is electrically connected to the drain of the first thin-film transistor and the gate of second thin-film transistor, and the second plate is electrically connected to the second source of the second thin-film transistor and the light-emitting unit (Park Fig. 2, para. 0028-0029; Cai Fig. 1; and Gupta Fig. 2).
Re claim 9, Park is silent with respect to a light-shielding layer disposed under the second thin-film transistor.
Gupta teaches a light shielding layer for the purpose of blocking stray light from disrupting operation of the device (para. 0078).
It would have been obvious to one of ordinary skill in the art at the time of filing to include a light shielding layer as taught by Gupta within the device of Park such that the light shielding layer was disposed under the second thin-film transistor for the purpose of blocking stray light from disrupting the operation of the pixel.
Re claim 12, Park teaches wherein the average electron mobility of the first active layer and the third active layer of the first thin-film transistor is 1.5 times or more of the electron mobility of the second active layer of the second thin-film transistor (para. 0038).
Re claim 13, Park teaches wherein the average electron mobility of the first active layer and the third active layer of the first thin-film transistor is greater than or equal to 20 cm2/(V-s) (para. 0038).
Re claim 15, Park teaches wherein the first active layer of the first thin-film transistor and the second active layer of the second thin- film transistor are provided through a same manufacturing process (Fig. 4B; para. 0044).
Re claim 16, Park teaches wherein a material of the third active layer of the first thin-film transistor comprises one or more of indium oxide, gallium oxide, zinc oxide, tin oxide, and combinations thereof (para. 0034).
Re claim 17, Park teaches wherein a material of the first active layer of the first thin-film transistor is different from the material of the third active layer of the first thin-film transistor (para. 0034).
Response to Arguments
Applicant's arguments filed 12/09/2025 have been fully considered but they are not persuasive.
Specifically, Applicant’s arguments are based on a misinterpretation of the rejection. Applicant states that Park’s 112b layer is equivalent to the “third active layer” of the claims; however, the rejection is based on Park’s 112b layer being the “first active layer”, while Park’s 112a was interpreted as being the “third active layer”. The claims to not specify a specific order of the “first active layer” and the “third active layer”; only that they are “laminated”.
Because, as pointed out by Applicant, Park’s active layer 122 (the claimed “second active layer”) uses the same layer as Park’s 112b layer, the claimed limitation of “wherein a material of the first active layer [112b] of the first thin film transistor [110] is same as a material of the second active layer [122] of the second thin film transistor [120]” is met by the disclosure of Park.
Applicant further argues that although Shin has disclosed threshold voltage offset, it has not disclosed an average threshold voltage offset of two active layers of the thin-film transistors, nor has it disclosed that the average threshold voltage offset is greater than or equal to the threshold voltage offset of the second thin-film transistor. Applicant argues that the Examiner has not made a prima facie case of obviousness to combine the threshold voltage offset in Shin with the threshold voltage offset of the second thin-film transistor being less than or equal to the average threshold voltage offset of the first thin-film transistor, because there is no teaching, suggestion, or motivation to combine the feature that the threshold voltage offset of the second thin-film transistor is less than or equal to the average threshold voltage offset of the first thin-film transistor with the threshold voltage offset in Shin, thereby the first thin-film transistor can serve as the switching thin-film transistor with the short response time, and the second thin-film transistor can serve as the driving transistor with the high stability.
The Examiner disagrees. The Examiner cited Shin to teach that threshold voltage offset is generally undesirable and ideally minimized or non- existent in order to avoid stain or deviation of luminance that may be visible on the screen (Shin para. 0007-0008). Therefore, one of ordinary skill in the art at the time of filing would have been motivated to minimize the threshold voltage offsets of the transistors of Park for the same advantage of avoiding stain or deviation of luminance. It would naturally follow that the optimum or workable ranges be discovered and this is not considered inventive (MPEP 2144.05, II, A). In this case, when optimizing, it would naturally follow that the optimum or workable ranges of “the threshold voltage offset of the second active layer of the second thin- film transistor is less than or equal to an average threshold voltage offset of the first active layer and the third active layer of the first thin-film transistor” be discovered. Particularly, in the case where the threshold voltage offsets are optimized such that they are eliminated, then the threshold voltage offsets would be equal (they would both be zero) and; therefore, the claimed limitations would be met.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (571)272-4237. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOLLY K REIDA/Examiner, Art Unit 2899