Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
Applicant’s arguments, filed 04/13/2026, with respect to pending claims 1, 2, 5-9, 11, 12, and 14-15 have been fully considered and are directed to claims as amended. The arguments addressed to the 101 rejection are not persuasive.
Arguments
The Applicant argues (Pages 7 and 8):
1. The Amended Claims Provide a Concrete Technical Purpose Beyond Data Manipulation
“Independent claims 1 and 6 are amended to explicitly recite "ending the process" following the steps of outputting the notifications. Specifically, the claims now require ending the process when notifying the user to check whether the first step list has been implemented correctly based on the test results, and ending the process after notifying the user that the difference in the characteristic value will be small based on the regression analysis.
The addition of "ending the process" gives the claims a concrete technical effect. Rather than merely presenting data to a user, the claimed system and method actively terminate a semiconductor prototyping run when the data indicates that a lot was incorrectly implemented or that further processing would not yield a measurable improvement in device characteristics (See, Paragraphs [0061]-[0062], Original Specification). As detailed in the specification, this termination step physically reduces the number of prototype cycles required, thereby lowering development costs and shortening the time-to-market (See, Paragraphs [0094]-[0095], Original Specification). This is an objective technical improvement specific to semiconductor manufacturing and prototyping, not a generic business or administrative decision.
2. The Claims Recite an Improvement to Semiconductor Manufacturing (Step 2A, Prong 2 / Step 2B)
The claimed invention is expressly directed to improving the evaluation and characteristic values of semiconductor elements, overcoming the difficulties of verifying step dependencies in complex manufacturing processes involving wide-ranging steps and conditions (See, Paragraphs [0001]-[0005], Original Specification). By automatically halting a prototyping lot when the regression analysis predicts only a negligible change in the target characteristic value, the system prevents the wasteful processing of substrates that would not yield a measurable benefit. This represents a specific technical solution to a technical problem in the field of semiconductor process engineering.”
The Examiner respectfully disagrees with the assertions above. The additional step of "ending the process" as recited in the claims (see the 112(b) discussion below) just amounts to an insignificant additional step. The Examiner suggests indicating a specific process which is being ended or at least adding more detail on what process is being run and ended, so that it becomes clear that the claim is reciting the more specific kinds of improvement that are discussed on pages 7 and 8 of the arguments, which might then be enough to overcome the 101 rejection. Please see the claim analysis below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 5-9, 11, 12, 14 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 6 recite the limitation of “the process”, which is recited several times in the claims. There is insufficient antecedent basis for this limitation in the claim.
It is important to note that it is unclear what “the process” refers to in the claim, so merely changing it to “a process” the first time it occurs would not fix the issue. The scope of the claim is unclear because it is not clear whether the “process” refers to some subset of the recited steps in the claim or whether the “process” refers to some semiconductor manufacturing process which is going on in the background of the claim, involving more components and actions than are actually recited explicitly. Please clarify the claim to make clear whether there is some semiconductor manufacturing process going on, for which data is being collected and analyzed, and which is then ended if the claim gets a certain result? Or is the recited “test” itself the process that gets ended? Or is it the method of the claim that gets ended, and any further steps in the claim don’t get carried out? Since no specific “process” has been recited, the Examiner tentatively interprets the claim to mean that the steps of the claim are ended at the instruction of “ending the process” (and no further limitations are carried out), rather than that some specific external process involved in the semiconductor manufacturing environment is being terminated.
The Examiner notes that the resolution of this issue has an impact on the 101 analysis below, since “ending the process” can be understood in different ways, some of which may involve additional elements/steps that could integrate the claims into a practical application, along the lines suggested by the applicant’s arguments on pages 7 and 8. Clarification by the applicant is respectfully requested.
Claims 2, 5, 7-9, 11, 12, 14 and 15 are rejected under 35 U.S.C. 112 because they incorporate the lack of clarity present in parent claims 1 and 6.
Claim Rejections - 35 USC §101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 2, 5-9, 11, 12, 14, and 15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more as addressed below.
The new 2019 Revised Patent Subject Matter Eligibility Guidance published in the Federal Register (Vol. 84 No. 4, Jan 7, 2019 pp 50-57) has been applied and the claims are deemed as being patent ineligible.
The current 35 USC 101 analysis is based on the current guidance (Federal Register vol. 79, No. 241. pp. 74618-74633). The analysis follows several steps. Step 1 determines whether the claim belongs to a valid statutory class. Step 2A prong 1 identifies whether an abstract idea is claimed. Step 2A prong 2 determines whether any abstract idea is integrated into a practical application. If the abstract idea is integrated into a practical application the claim is patent eligible under 35 USC 101. Last, step 2B determines whether the claims contain something significantly more than the abstract idea. In most cases the existence of a practical application predicates the existence of an additional element that is significantly more.
Under Step 2A Prong 1, the independent claim 1 all include abstract ideas as highlighted (using a bold font) shown below.
“1. A storage having instructions stored therein which, when processed by arithmetic device, cause the arithmetic device to perform operations for semiconductor element characteristic value estimation system comprising:
inputting a first step list, a second step list, and a characteristic value of a semiconductor element,
storing a group of step lists and a group of characteristic values of semiconductor elements,
performing comparison between two step lists selected from the first step list and the group of step lists and obtaining a result of the comparison,
collecting step lists whose degree of similarity to the first step list is higher than or equal to a certain level from a group of step lists and a collected group of characteristic values,
performing a test using two or more characteristic values of semiconductor elements selected from the characteristic value of the semiconductor element and the collected group of characteristic values of the semiconductor elements and obtaining a result of the test;
performing regression analysis of parameters for a step and two or more characteristic values of semiconductor elements selected from the characteristic value of the semiconductor element and the group of characteristic values of the semiconductor elements and obtaining a result of the regression analysis;
estimating a characteristic value of a semiconductor element from the second step list on the basis of the result of the regression analysis;
outputting, in accordance with the result of the test, notifying to check whether the first list has been implemented correctly to a display device and ending the process,
outputting, in accordance with the result of the comparison, notifying an information that a difference in the characteristic value will be small based on the result of the regression analysis and ending the process, and
outputting, in accordance with the result of the test, the characteristic value of the semiconductor element and the result of the comparison to a display device.
“6. (Currently Amended) A semiconductor element characteristic value estimation method comprising:
a first step of inputting a first step list included in a first lot and a characteristic value of a first semiconductor element manufactured in accordance with the first step list;
a second step of collecting a second step list whose degree of similarity to the first step list is higher than or equal to a certain level from a group of step lists;
a third step of performing a test using the characteristic value of the first semiconductor element and a characteristic value of a second semiconductor element manufactured in accordance with the second step list and, after displaying notifying to check whether the first step list has been implemented correctly based on the result of the test to a display device, ending the process;
a fourth step of performing, among a first plurality of semiconductor elements manufactured in accordance with a first plurality of step lists included in the first lot, analysis of variance on characteristic values of the first plurality of semiconductor elements and comparison of the first plurality of step lists and recording whether a step which is different among the first plurality of step lists influences the characteristic values of the first plurality of semiconductor elements;
a fifth step of collecting a third step list whose degree of similarity to each of the first plurality of step lists is higher than or equal to a certain level from the group of step lists;
a sixth step of performing regression analysis of parameters for a step influencing the characteristic values of the first plurality of semiconductor elements and a characteristic value of a third semiconductor element manufactured in accordance with the third step list, and obtaining a result of the regression analysis;
a seventh step of estimating, from a second plurality of step lists included in a second lot, characteristic values of a second plurality of semiconductor elements manufactured in accordance with the second plurality of step lists on the basis of the result of the regression analysis before the second plurality of semiconductor elements are manufactured; and
an eighth step of outputting the characteristic values and the result of the comparison and after notifying an information that a difference in the characteristic value will be small based on the result of the regression analysis, ending the process,
wherein the semiconductor element characteristic value estimation method is stored in a storage and is executed by an arithmetic device.”
The highlighted steps are considered to be equivalent to mathematical calculations and mathematical steps.
Under Step 2A Prong 2, claims 1 and 6 just comprise a field of use (semiconductor manufacturing) and claims are not directed to any particular practical application.
All of claim 1 comprises an abstract idea, except the steps/elements of “arithmetic device” and “display device” which are merely a generic pieces of a computer. The general-purpose computer does not make the claims significantly more than the abstract idea. All of these additional elements are generic computer and generic components of the computer, which are in light of Alice, are not considered as being significantly more than the abstract idea. There is no indication that the combination of elements/units improves the functioning of a computer or improves any other technology or technical field.
The step of “collecting step lists whose degree of similarity to the first step list is higher than or equal to a certain level from a group of step lists and a collected group of characteristic values,” could be characterized as mathematical calculations or mental steps performed in the human mind (including observation, evaluation and opinion).
The step of “outputting, in accordance with the result of the test, notifying to check whether the first list has been implemented correctly to a display device,” in claim 1 and step of “displaying notifying to check whether the first list has been implemented correctly based on the result of the test to a display device” and “outputting the characteristic values and the result of the comparison…” in claim 6 are considered extra solution activity and not significantly more than the judicial exception. As recited in MPEP section 2106.05(g), displaying analysis/results is considered extra solution activity in light of Electric Pawer Group, LLO y. Alstom 3.A, 830 F.3d 1350, 1354-55, 119 USPOQed 1739, 1742 (Fed. Cir. 2076). The same applies to the other “outputting” steps in the claims.
The additional steps of "ending the process" is understood as including merely the ending of the claimed steps at the point in the claim where the “ending the process” claim is recited, so this considered to be either part of the abstract idea or an insignificant additional element which does not integrate the claim into a particular practical application.
Claim 1 comprises other additional steps such as the “storing a group of step lists and a group characteristic value” and “stored in a storage and is executed by an arithmetic device” which is not significantly more since it is claimed at a high level of generality as a generic computer processing step. Storing and retrieving information in memory is not significantly more as found in VersataDev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
In claim 6 regarding the step of “a first step of inputting a first step list included in a first lot and a characteristic value of a first semiconductor element manufactured in accordance with the first step list”, the receiving/inputting a list of data is merely insignificant extra solution activity to obtain data.
Under step 2B, the claims are not significantly more than the abstract idea for analogous reasons to those discussed above with respect to Prong 2. Claims 1 and 6 are therefore rejected as ineligible.
Dependent claims 2 and 5 merely extend the details of the abstract idea of mathematical concepts.
Claim 7 is directed to the data output, which is an insignificant additional step.
Claims 8 and 9 further recite the display being in the form of a table, which is insignificant additional steps.
Claim 10 and 13 comprise “notifying information…regression analysis” which is just extra solution data activity.
Claims 11, 12, 14 and 15 additionally describes the data information.
Therefore claims 2, 5, 7-9, 11, 12, 14, and 15 are similarly rejected under 35 U.S.C. 101.
Examiner note regarding the prior art of the record:
Regarding Claims 1 and 6:
Kotani (JP2012212919A), hereinafter Kotani describes a device for managing substrate processing, wherein the device associates recipe data and processing results data and accumulates the associated data in a file, and from a plurality of processing results data, subjects the relationship between recipe data and processing results data to regression analysis.
Yamada (JP2012004181), hereinafter Yamada describes a characteristic prediction device that learns a prediction model by calibrating state variables in the prediction model, the state variables expressing a relationship between operating data and characteristic values, on the basis of characteristic values of a product manufactured by a processing device and error information pertaining to the characteristic values.
Mitsushita et al., (US Pub.20070225853A1), hereinafter Mitsushita describes a semiconductor manufacturing device that stores, in a database, a QC value data group and an EES parameter group for a plurality of lots processed by the semiconductor manufacturing device in the past, and creates an equation for predicting QC value data using PLS regression on the basis of the EES parameter group and the QC value data group.
However, regarding claims 1 and 6, the closest prior arts either singularly or in combination, fail to anticipate or render obvious in particular, “performing comparison two step lists (second step of collecting a second process list for which the similarity level is a certain level or higher)”, “performing a test using two or more characteristic values of semiconductor elements (third step of conducting an examination in which characteristic values are used) and obtaining a result of the test”, and “performing regression analysis … with the group of characteristic values of the semiconductor elements (sixth step of implementing regression analysis)”. Claims 1 and 6 are therefore distinguished from the prior art.
Claims 2, 5, 7-9, 11, 12, 14, and 15 are distinguished from the prior art due to their dependency on claims 1 and 6 correspondently.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KALERIA KNOX/
Examiner, Art Unit 2857
/ANDREW SCHECHTER/Supervisory Patent Examiner, Art Unit 2857
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