DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 5, 2026, has been entered.
Claim Objections
Claim 1 is objected to because of the following informalities:
It is noted that since the claim amendments dated May 19, 2025, were submitted after the final Office Action of March 5, 2025, and were not entered, the aspect of claim 1 which relates to “and the arsenic flux concentration from the source is a mixture of As4 and As2” is a limitation which has been newly added to claim 1 and should have been underlined.
Appropriate correction is required.
Claim Interpretation
Claim 1 includes the wherein clause(s) which recite the following:
“wherein some or all of the deposited material is non-intentionally doped with a resulting p-type doping concentration in an interval of 2×1014cm-3 to 3.6×1016cm-3, and with a mobility greater than or equal to 1.6×103 cm2/Vs at room temperature, wherein the resulting material exhibits a p-type concentration between 2×1014cm-3 to 3.6×1016cm-3 as measured by Hall-effect at room temperature, thereby allowing subsequent compensation by an n-dopant agent, or the compensating n-dopant agent is deposited simultaneously with the group III-V material(s) in the first step resulting in a n-doped material, wherein the n-dopant agent concentration is at least 1.00×1016 cm-3” (emphasis added).
The inclusion of the word “or” in the above wherein clause is interpreted as meaning the deposited material is either non-intentionally doped with a resulting p-type doping concentration or is intentionally doped with an n-dopant agent to produce an n-type doping concentration. Thus, the claim may be met by prior art which satisfies at least one of these two alternatives.
In the context of claim 12, growth stops which are at “randomized irregular intervals” are interpreted as occurring at time periods which are not equal or do not have a periodic repeating pattern.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 17 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 17 recites an on-cut crystal in which “steps are not provided on the (111)Si substrate surface.” The specification as originally filed does not appear to teach or suggest that an on-cut crystal is a crystal in which no steps are provided on the Si(111) substrate surface.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-5, 7-8, 11, 13, 15, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over a publication to Kawai, et al. entitled “Initial growth mechanism of AlAs on Si(111) by molecular beam epitaxy,” Appl. Phys. Lett., Vol. 59, pp. 2983-85 (1991) (hereinafter “Kawai”) in view of U.S. Patent Appl. Publ. No. 2008/0076235 to Hudait, et al. (“Hudait”) and further in view of a publication to Chai, et al. entitled “The effect of growth conditions on Si incorporation in molecular beam epitaxial GaAs,” Appl. Phys. Lett., Vol. 39, pp. 800-03 (1981) (“Chai”) and still further in view of U.S. Patent No. 4,833,101 to Toshio Fujii (“Fujii”) and even further in view of a publication to Kunzel, et al. entitled “The effect of arsenic vapour species on electrical and optical properties of GaAs grown by molecular beam epitaxy,” Appl. Phys. A, Vol. 28, pp. 167-73 (1982) (“Kunzel”).
Regarding claim 1, Kawai teaches a method of controlling n-doping in a molecular beam epitaxy (MBE) growth process that includes growing group III-V materials on a (111)Si substrate (see, e.g., the Abstract, Figs. 1-3, and entire reference which teach the growth of AlAs on Si(111) by MBE), comprising the steps of:
growing the nucleation layer (see, e.g., the third paragraph on p. 2983 which teaches forming a nucleation layer in the form of an As prelayer by irradiating the Si(111) substrate with As4), thereafter
directing a continually flowing arsenic flux towards a growth interface of the (111)Si substrate after growing the nucleation layer (see, e.g., the third and fourth paragraphs on p. 2983 which teach that an AlAs layer is then grown on the Si(111) substrate by initially directing a continually flowing As4 flux towards the substrate after forming the As prelayer),
depositing group III-V material(s) in steps comprising periods wherein in a first step the deposition of the group III-V material is carried out, followed by a second step wherein the deposition of the group III-V material is stopped, continuing depositing the group III-V material by performing the first step and the second step while the arsenic flux is continually flowing until achieving a final material growth composition (see, e.g., pp. 2983-84 and Figs. 1-3 which teach that an AlAs layer is deposited in steps comprised of periods in which the Al flux is supplied for 1.3 s and then stopped for 2.0 s under a constant As4 flux),
keeping the temperature of the epitaxial growth process in an interval between 300 °C to 580 °C (see, e.g., the third and fourth paragraphs on p. 2983 which teach that the growth temperature is maintained at 400 and 540 °C).
Kawai does not explicitly teach that the nucleation layer comprises group III-Sb material(s). However, in Figs. 1-5 and ¶¶[0016]-[0034] as well as elsewhere throughout the entire reference Hudait teaches an analogous method of depositing Group III-V compound semiconductors onto a Si substrate as part of a process of forming electronic devices thereupon. In ¶¶[0020]-[0022] Hudait specifically teaches the growth of a buffer layer which is comprised of a nucleation layer (106) and an overlying buffer layer (108) which, in one embodiment, is comprised of AlSb in order to provide an improved interface between the device layer and substrate as well as to provide excellent device isolation. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Hudait and would be motivated to utilize a Group III-Sb material such as AlSb as the nucleation layer in the method of Kawai in order to provide an improved interface between the device layer and substrate as well as to provide excellent device isolation.
Kawai and Hudait do not explicitly teach that some or all of the deposited material is non-intentionally doped with a resulting p-type doping concentration in an interval of 2×1014cm-3 to 3.6×1016cm-3, and with a mobility greater than or equal to 1.6×103 cm2/Vs at room temperature, wherein the resulting material exhibits a p-type concentration between 2×1014cm-3 to 3.6×1016cm-3 as measured by Hall-effect at room temperature, thereby allowing subsequent compensation by an n-dopant agent, or the compensating n-dopant agent is deposited simultaneously with the group III-V material(s) in the first step resulting in a n-doped material, wherein the n-dopant agent concentration is at least 1.00×1016 cm-3. However, in Figs. 1-3 and pp. 800-03 Chai teaches that Si may be used as an n-type dopant in Group III-V semiconductor materials such as GaAs. In Fig. 1 and p. 801 Chai specifically teaches that a Si doping concentration of approximately 1015 to 6×1018 cm-3 may be obtained by increasing the temperature of the Si effusion cell while the substrate temperature is in the 530 to 620 °C range. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Chai and would be motivated to utilize Si as an n-type dopant with a concentration of at least 1016 cm-3 in the method of Kawai and Hudait in order to form an n-type AlAs or AlInAs layer as part of a process of forming electronic and/or optoelectronic devices having the desired properties on Si substrates.
Kawai and Chai do not explicitly teach that the Group III-V material(s) comprises at least Ga and In or Al and In. However, in Fig. 4 and ¶¶[0025]-[0026] Hudait further teaches that a barrier layer (112) comprised of InAlSb is formed on the buffer layer (108) by opening sources of Al, In, and Sb in the reactor. Then in Fig. 2, col. 1, ll. 11-57, and col. 3, l. 6 to col. 4, l. 12 Fujii teaches that ternary and quaternary alloys such as InGaAs or InGaAlAs are commonly utilized to produce a semiconductor having a particular bandgap such as between about 0.7 and 1.5 eV. The composition of individual components such as In is adjusted from 0 to 100% along curve A in Fig. 2, for example, in order to produce an InGaAs alloy having the desired bandgap as well as to lattice match the film to the substrate. Accordingly, the teachings of Hudait and Fujii show that the use of Al, In, and Ga as Group III materials for the formation of a Group III-V alloy is known in the art and is utilized as part of the formation of Group III-V layers having a predetermined lattice parameter and bandgap in optoelectronic devices. Consequently, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Hudait and Fujii and would be motivate to incorporate In into the AlAs layer produced in the method of Kawai in order to, for example, produce a Group III-V layer having the bandgap and lattice parameter necessary for the formation of the desired optoelectronic device(s). In this regard, the use of In and Al as Group III materials in a III-V device would involve nothing more than the use of a known material suitable for its intended use. Use of a known material based on its suitability for its intended use has been held to support a prima facie determination of obviousness. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1947). See also MPEP 2144.07.
Kawai, Hudait, Chai, and Fujii do not explicitly teach that the arsenic flux concentration from the source is a mixture of As4 and As2. However, in Fig. 1 and the Experimental section on pp. 168-69 Kunzel teaches that the supply of As during the growth of a Group III-V compound semiconductor is accomplished using an effusion cell comprised of a solid As source with a temperature-controlled cracker which is operated at temperatures as high as 850 °C. Below 500 °C a pure As2 flux is produced whereas operation at 850 °C produces a beam consisting of at least 90 % As2 and 10 % As4. In Fig. 2 and Section 2.1 Kunzel teaches that a cracker temperature of 850 °C causes defect-induced bound lines to disappear from the photoluminescence spectra while Figs. 4-5 and Section 2.3 teach that Ge behaves as an n-type dopant through the use of primarily As2 instead of As4 species (i.e., a cracker temperature of 850 °C). Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Kunzel and would be motivated to utilize a solid As source with a temperature-controlled cracker operating at a temperature of 850 °C in order to produce an As flux comprised of 90% As2 and 10% As4 such that a higher quality Group III-V compound semiconductor which is doped n-type when using Si as a dopant may be produced.
Regarding claim 3, Kawai, Hudait, and Fujii do not teach that the n-doping concentration is in an interval from 1×1016 cm-3 to 3.5×1018 cm-3. However, as noted supra with respect to the rejection of claim 1, in Fig. 1 and p. 801 Chai specifically teaches that a Si doping concentration of approximately 1015 to 6×1018 cm-3 may be obtained by increasing the temperature of the Si effusion cell while the substrate temperature is in the 530 to 620 °C range. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Chai and would be motivated to utilize Si as a compensating n-type dopant with an overlapping concentration of 1015 to 6×1018 cm-3 in the method of Kawai and Hudait in order to form an n-type AlAs layer as part of a method of forming electronic devices on Si substrates.
Regarding claim 4, Kawai, Hudait, and Fujii do not teach that the n-dopant agent is from a group comprising silicon, sulfur, tellurium, tin, germanium, and selenium. However, as noted supra with respect to the rejection of claim 1, in Figs. 1-3 and pp. 800-03 Chai teaches that Si may be used as an n-type dopant in Group III-V semiconductor materials such as GaAs. Accordingly, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to utilize Si as an n-type dopant in the method of Kawai and Hudait in order to form an n-type Group III-V semiconductor layer.
Regarding claim 5, Kawai, Hudait, Chai, and Fujii do not explicitly teach that the arsenic flux source is provided by a solid As source with a temperature-controlled cracker in a range from 600°C to 900°C. However, as noted supra with respect to the rejection of claim 1, in Fig. 1 and the Experimental section on pp. 168-69 Kunzel teaches that the supply of As during the growth of a Group III-V compound semiconductor is accomplished using an effusion cell comprised of a solid As source with a temperature-controlled cracker which is operated at temperatures as high as 850 °C. Below 500 °C a pure As2 flux is produced whereas operation at 850 °C produces a beam consisting of at least 90 % As2 and 10 % As4. In Fig. 2 and Section 2.1 Kunzel teaches that a cracker temperature of 850 °C causes defect-induced bound lines to disappear from the photoluminescence spectra while Figs. 4-5 and Section 2.3 teach that Ge behaves as an n-type dopant through the use of primarily As2 instead of As4 species (i.e., a cracker temperature of 850 °C). Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Kunzel and would be motivated to utilize a solid As source with a temperature-controlled cracker operating at a temperature of 850 °C in order to produce an As flux comprised of 90% As2 and 10% As4 such that a higher quality Group III-V compound semiconductor which is doped n-type when using Si as a dopant may be produced.
Regarding claim 7, Kawai, Hudait, Chai, and Fujii do not explicitly teach that the concentration of As4 is larger than the concentration of As2 at a cracker temperature approaching 600°C, while the concentration of As4 is less than the concentration of As2 at a cracker temperature approaching 900°C. However, as noted supra with respect to the rejection of claim 5, in Fig. 1 and the Experimental section on pp. 168-69 Kunzel teaches that the supply of As during the growth of a Group III-V compound semiconductor is accomplished using an effusion cell comprised of a solid As source with a temperature-controlled cracker which is operated at temperatures as high as 850 °C. Below 500 °C a pure As2 flux is produced whereas operation at 850 °C produces a beam consisting of at least 90 % As2 and 10 % As4. Thus, the teachings of Kunzel show that operating a cracked As source over the recited temperature ranges would produce the As4 and As2 concentrations as claimed.
Regarding claim 8, Kawai teaches that the arsenic flux concentration in non- nucleation layers, measured using beam equivalent pressure (BEP) is at least 1.33322×10-5 mbar (see, e.g., the third paragraph on p. 2983 which teaches the use of an As4 beam flux of 10-5 Torr).
Regarding claim 11, Kawai teaches that continuing the depositing of the group III-V material(s) according to the first step and the second step is done periodically (see, e.g., pp. 2983-84 and Figs. 1-3 which teach that an AlAs layer is deposited in steps comprised of regular periods in which the Al flux is supplied for 1.3 s and then stopped for 2.0 s under a constant As4 flux).
Regarding claim 13, Kawai teaches that increasing the arsenic flux concentration in non-nucleation layers, measured using beam equivalent pressure (BEP) to at least 1.33322×10-5 mbar reduces growth stops duration (see, e.g., pp. 2983-84 and Figs. 1-3 which teach that an AlAs layer is deposited in steps comprised of regular periods in which the Al flux is supplied for 1.3 s and then stopped for 2.0 s under a constant As4 flux at a pressure of 10-5 Torr; accordingly, the higher As flux permits a shorter growth stop of 2 seconds).
Regarding claim 15, Kawai, Chai, and Fujii do not teach that the nucleation layer comprises As in an amount less than 20 at%. However, as noted supra with respect to the rejection of claim 1, in ¶¶[0020]-[0022] Hudait specifically teaches the growth of a buffer layer which is comprised of a nucleation layer (106) and an overlying buffer layer (108) which, in one embodiment, is comprised of AlSb in order to provide an improved interface between the device layer and substrate as well as to provide excellent device isolation. In this regard the nucleation layer has no As and, hence, is comprised of < 20 at% As.
Regarding claim 19, Kawai teaches that the arsenic flux concentration in non-nucleation layers, measured using beam equivalent pressure (BEP), is within a range of 1.33322×10-5 mbar to 3.99967×10-5 mbar (see, e.g., the third paragraph on p. 2983 which teaches the use of an As4 beam flux of 10-5 Torr).
Claims 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawai in view of Hudait and further in view of Chai and still further in view of Fujii and Kunzel and even further in view of U.S. Patent No. 5,077,875 to Hoke, et al. (“Hoke”).
Regarding claim 9, Kawai, Hudait, Chai, and Kunzel do not teach that indium is one of the group III-V materials, and the indium is deposited in an amount from 1.1at% to 21.4at%. However, in Fig. 2, col. 1, ll. 11-57, and col. 3, l. 6 to col. 4, l. 12 Fujii teaches that ternary and quaternary alloys such as InGaAs or InGaAlAs are commonly utilized to produce a semiconductor having a particular bandgap such as between about 0.7 and 1.5 eV. The composition of individual components such as In is adjusted from 0 to 100% along curve A in Fig. 2, for example, in order to produce an InGaAs alloy having the desired bandgap as well as to lattice match the film to the substrate. Then in Fig. 1 and col. 4, l. 21 to col. 5, l. Hoke teaches a specific embodiment in which a GaInAs channel layer (67) is utilized with an In concentration of 15 at. % In (i.e., Ga0.85In0.15As) which falls within the claimed range. It therefore would have been within the capabilities of an ordinary artisan prior to the effective filing date of the invention to utilize In as a Group III element in a Group III-V compound semiconductor alloy in the method of Kawai, Hudait, Chai, and Kunzel and to adjust the In composition to within the claimed range of 1.1 to 21.4 at. % to obtain a Group III-V compound semiconductor having the bandgap and lattice parameter necessary for a particular application.
Regarding claim 10, Kawai, Hudait, Chai, and Kunzel do not teach that indium is one of the group III-V materials, and the indium is deposited in an amount according to one of the following amounts 1.1 at%, 1.2 at%, 1.4 at%, 2.2 at% , 2.4 at% , 2.6 at% , 2.9 at%, 3.3 at%, 3.9 at%, 4.2 at%, 4.6 at%, 5.6 at%, 7.1 at%, 8.3 at%, 10.0 at%, 14.3 at%, 16.7 at% or 21.4 at%. However, in Fig. 2, col. 1, ll. 11-57, and col. 3, l. 6 to col. 4, l. 12 Fujii teaches that ternary and quaternary alloys such as InGaAs or InGaAlAs are commonly utilized to produce a semiconductor having a particular bandgap such as between about 0.7 and 1.5 eV. The composition of individual components such as In is adjusted from 0 to 100% along curve A in Fig. 2, for example, in order to produce an InGaAs alloy having the desired bandgap as well as to lattice match the film to the substrate. Then in Fig. 1 and col. 4, l. 21 to col. 5, l. Hoke teaches a specific embodiment in which a GaInAs channel layer (67) is utilized with an In concentration of 15 at. % In (i.e., Ga0.85In0.15As). It therefore would have been within the capabilities of an ordinary artisan prior to the effective filing date of the invention to utilize In as a Group III element in a Group III-V compound semiconductor alloy in the method of Kawai, Hudait, Chai, and Kunzel and to adjust the In composition to within the claimed values of 1.1 up to 21.4 at. % to obtain a Group III-V compound semiconductor having the bandgap and lattice parameter necessary for a particular application.
Claims 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawai in view of Hudait and further in view of Chai and still further in view of Fujii and Kunzel and even further in view of a publication to Sakaki, et al. entitled “One atomic layer heterointerface fluctuations in GaAs-AlAs quantum well structures and their suppression by insertion of smoothing period in molecular beam epitaxy,” Japanese Journal of Applied Physics, Vol. 24, pp. L417-20 (1985) (“Sakaki”).
Regarding claim 12, Kawai, Hudait, Chai, Fujii, and Kunzel do not teach that the periods of growth stops appear at randomized irregular intervals. However, in Figs. 1(a)-(b) and pp. L417-18 Sakaki teaches an analogous growth interruption method in which a growth stop period of 10-60 s and up to 90 s is utilized in order to control the flatness of the growth interface. As shown specifically in Fig. 1(b), the Al shutter is opened and then closed at different times and for different durations in order to facilitate recovery of the specular intensity of the RHEED beam when needed by permitting surface atoms sufficient time to migrate to equilibrium sites on the surface. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Sakaki and would be motivated to utilize RHEED to monitor the growth of AlAs in the method of Kawai, Hudait, Chai, Fujii, and Kunzel and would close the Al shutter at random intervals and for different durations as determined by the specular intensity of the RHEED spot such that surface adatoms have sufficient time to migrate to equilibrium sites and the quality of the deposited AlAs thin film may be maintained.
Regarding claim 14, Kawai, Hudait, Chai, Fujii, and Kunzel do not explicitly teach that periods of growth stops are between 20 to 500 seconds long. However, Kawai refers to the use of the growth interruption method of Sakaki in the third paragraph on p. 2983. Then in Figs. 1(a)-(b) and pp. L417-18 Sakaki teaches an analogous growth interruption method in which a growth stop period of 10-60 s and up to 90 s is utilized in order to control the flatness of the growth interface. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Sakaki and would recognize that a growth stop of up to 90 seconds may be utilized in order to, for example, obtain greater control over the flatness of the growth interface during AlAs growth in the method of Kawai.
Claims 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawai in view of Hudait and further in view of Chai and still further in view of Fujii and Kunzel and and even further in view of a publication to Yamamoto, et al. entitled “Misorientation dependence of crystal structures and electrical properties of Si-doped AlAs grown on (111)A GaAs by molecular beam epitaxy,” Japanese Journal of Applied Physics, Vol. 32, pp. 3346-53 (1993) (“Yamamoto”).
Regarding claim 16, Kawai, Hudait, Chai, Fujii, and Kunzel do not explicitly teach that the (111)Si substrate has a miscut angle such that steps are provided on the (111)Si substrate surface, wherein heights of the respective steps are not more than one monolayer of molecules. However, in the Abstract, Figs. 1-9, Experimental Section 2, and the Results in Section 3 Yamamoto teaches that the growth of Si-doped AlAs on (111) substrates which are miscut by 3° or 5° yields epitaxial layers which have, inter alia, a cubic crystal structure, possess a lower electrical resistivity (see Fig. 8), and are n-type. Moreover, a substrate miscut of 3 or 5° will necessarily produce monolayer-height atomic steps which facilitate step-flow growth as arriving adatoms preferentially attach at step edges. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Yamamoto and would be motivated to utilize a miscut Si(111) substrate which has monolayer height atomic steps for the growth of the Si-doped AlAs epitaxial layer of Kawai, Hudait, Chai, Fujii, and Kunzel in order to promote step-flow growth and produce a Group III-V compound semiconductor which is n-type, has a reduced surface roughness, and has the resistivity and crystal structure necessary for a particular application.
Regarding claim 17, Kawai teaches that the (111)Si substrate is an on-cut crystal such that steps are not provided on the (111)Si substrate surface (see, e.g., the third paragraph on p. 2983 which teaches that the Si(111) substrate has a minor off-angle of 0.5° and, hence, may be considered as an on-cut crystal). Even if it is assumed arguendo that Kawai does not teach that the Si(111) substrate is an on-cut crystal, as noted supra with respect to the rejection of claim 16, in the Abstract, Figs. 1-9, Experimental Section 2, and the Results in Section 3 Yamamoto teaches that the growth of Si-doped AlAs on (111) substrates which are exactly (111) oriented yields epitaxial layers which have, inter alia, a hexagonal crystal structure and a higher electrical resistivity. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Yamamoto and would be motivated to utilize an on-cut Si(111) substrate for the growth of the Si-doped AlAs epitaxial layer of Kawai, Hudait, and Chai in order to produce a Group III-V compound semiconductor which has the resistivity and crystal structure necessary for a particular application.
Claim 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawai in view of Hudait and further in view of Chai and still further in view of Fujii and Kunzel and even further in view of a publication to Kaspi, et al. entitled “Digital alloy growth in mixed As/Sb heterostructures,” Journal of Crystal Growth, Vol. 251, pp. 515-20 (2003) (“Kaspi”).
Regarding claim 18, Kawai, Hudait, Chai, Fujii, and Kunzel do not explicitly teach that the epitaxial growth process can be of a digital alloy growth type. However, in the Abstract and Sections 2-5 at pp. 516-20 Kaspi teaches that Group III-V compound semiconductor superlattices may be grown by a digital alloying technique in order to provide protection against compositional drift in the growth direction due to reduced sensitivity to variations in arsenic-flux and substrate temperature. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to ensure the epitaxial growth process of Kawai, Hudait, and Chai can be a digital alloy growth type for these reasons.
Claim 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawai in view of Hudait and further in view of Chai and still further in view of Fujii and Kunzel and even further in view of U.S. Patent No. 5,476,811 to Toshio Fujii, et al. (“Toshio”).
Regarding claim 20, Kawai does not teach that the arsenic flux concentration in non-nucleation layers, measured using beam equivalent pressure (BEP), is above 3.99967×10-5 mbar. However, in Figs. 8-9 and col. 11, ll. 1-64 as well as elsewhere throughout the entire reference Toshio teaches an analogous method of depositing a Group III-V semiconductor such as GaAs and AlAs in which the As vapor pressure utilized for growth may be used to control the conduction type of the deposited semiconductor layer. At an As pressure of approximately 3×10-5 Torr a transition from p-type to n-type occurs on all crystalline growth surfaces, including the (100), (110), (111), and (311) planes. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Toshio and would be motivated to utilize an As BEP of above 3.99967×10-5 mbar in the method of Kawai, Hudait, and Chai in order to deposit an n-type layer as part of a process for forming one or more electronic devices thereupon.
Response to Arguments
Applicants’ arguments filed February 5, 2026, have been fully considered, but they are not persuasive and are moot in view of the new grounds of rejection set forth in this Office Action.
Applicants initially argue that in the method of Kawai the As flux is pulsed to reconstruct the surface between depositions and does not teach an uninterrupted As flux as claimed. See applicants’ 2/5/2026 reply, p. 7. This argument is found unpersuasive as the third full paragraph on p. 2983 of Kawai clearly teaches that there is a “constant As4 flux in every cycle” which indicates that the As flus is not pulsed.
Applicants then repeat their argument that since Hudait’s heteroepitaxy involves a (001) substrate and a high-temperature GaAs/AlAs nucleation system there is no motivation for forming a Group III-Sb nucleation layer on the Si(111) surface. Id. at p. 8. This argument is not found persuasive as the purpose of the buffer layer in Hudait is to, for example, provide high resistivity for excellent device isolation and low capacitance. This benefit is not dependent on and may be attained regardless of which crystallographic plane is used as the growth surface.
Applicants then contend that Chai and Fuji simply discuss generic Si doping and As overpressure in GaAs and do not teach or imply maintaining a continuous As flux. Id. Applicants’ argument is noted, but is unpersuasive as appears to be based on arguing against the references individually. In this case it is Kawai rather than Chai and Fuji that is relied upon to teach the aspect relating to maintaining a continuous As flux.
Applicants argue that the Examples proffered in the specification demonstrate that only the claimed combination yields stable (111)III-V growth with low background p-type levels and high Hall mobility. Id. Applicants’ argument is noted, but it is pointed out that it is based upon features which are not explicitly claimed. As explained supra with respect to the rejection and interpretation of claim 1, the claim language includes the use of the word “or” in the wherein clause which is interpreted as meaning that the deposited material is either non-intentionally doped with a p-type doping concentration or is intentionally doped with an n-dopant agent. The rejection of claim 1 relies on Chai to teach that intentionally doping GaAs with Si as an n-type dopant is known in the art. In order to have the p-type doping concentration explicitly required by the claim it would be necessary to remove the aspect of the claim which relates to intentionally producing an n-doped material.
Applicants then argue against the reliance on Kunzel to reject claims 5-7 by contending that Kunzel does not teach the continuous flux growth/pause regime or the Si(111) substrate and no explicit motivation has been provided. Id. This argument is not found persuasive as it is Kawai rather than Kunzel that is relied upon to teach the use of Si(111) substrate and a continuous As flux. Moreover, the specific motivation for relying on the teachings of Kunzel is, as noted supra with respect to the rejection of claims 5-7, to produce a higher quality Group III-V semiconductor which is doped n-type when using Si as a dopant.
Applicants argue against the reliance on Hoke to teach the inclusion of In by contending that Hoke does not teach indium incorporation on Si(111) under continuous As flux and the In ranges were selected specifically to mitigate (111) faceting and are not a result of routine optimization. Id. at p. 9. This argument is not found persuasive as it is Kawai rather than Kunzel that is relied upon to teach the use of Si(111) substrate and a continuous As flux. Moreover, applicants’ argument regarding mitigating (111) faceting is based on arguments of counsel rather than factually supported objective evidence. In any case, Hoke is relied on to teach that In may be incorporated in the recited composition to produce a Group III-V compound semiconductor with the desired bandgap and lattice parameter for a particular application.
Applicants argue against the rejection of claims 12 and 14 by contending that Sakaki’s GaAs/AlA superlattice work involves (001) GaAs substrates and As-off interruptions to control interface roughness which is contradictory to the claimed process which maintains As flux on during interruptions. Id. This argument also is found unpersuasive as the teachings of Sakaki only involve stopping the Ga and/or Al flux rather than the As flux. Moreover, claim 12 specifically recites that “periods of growth stops appear at randomized irregular intervals.” In providing the claim with its broadest reasonable interpretation a “growth stop” may be interpreted as stopping the precursor flux from all sources. The claim does not specifically require that the As flux be continued during the “growth stop.” The teachings of Sakaki show that stopping the Ga or Al flux at random intervals facilitates recovery of the specular intensity of the RHEED beam and, hence, the growth of a higher quality Group III-V layer.
Applicants then argue against the rejection of claim 16-17 by contending that Yamamoto describes Si-doped GaAs(111)A layers with 3° miscut for specific electrical properties, not the on-cut or one-monolayer step limits required by the claims and the Examiner’s motivation is lacking. Id. This argument is not found persuasive as the teachings of Yamamoto clearly show that the use of Si(111) substrates with a miscut angle of 0, 3, or 5° facilitates control of the growth mode, the resulting crystal structure, as well as the type and amount of doping. Thus, a person of ordinary skill in the art would be motivated to utilize the substrate miscut, including the formation of monolayer-high atomic steps as a result of the 3 or 5° miscut angle in order to control the aforementioned materials properties in the desired manner for a particular application. Moreover, since the Si(111) substrate of Kawai has a very minor off-angle of 0.5° it may be broadly considered as an “on-cut” crystal. Upon further review it has been determined that the specification actually does not teach or suggest an on-cut crystal in which “steps are not provided on the (111)Si substrate surface.” The Examiner notes that it is essentially impossible to form practical wafer sizes such as 4-, 8-, or 12-inch Si wafers where the entire surface is comprised of a single atomic plane and the miscut is perfectly 0°. This is necessarily the case due to slight deviations or alignment errors in the wafer cutting and polishing process which leaves behind a very small miscut angle that necessarily produces atomic steps.
Applicants then argue against the rejection of claim 18 by contending that the InAsSb digital alloys on GaSb substrates as taught by Kaspi are chemically and structurally unrelated to the recited Si(111) platform and, consequently, there is no teaching or motivation that links Kaspi to continuous As flux or Sb nucleation on Si. Id. This argument also is found unpersuasive as the teachings of Kaspi relate to the growth of Group III-V semiconductors by thin film growth from the vapor phase and, hence, Kaspi is considered analogous art. As explained supra with respect to the rejection of claim 18, Kaspi teaches that growth by the digital alloying technique provides protection against composition drift in the growth direction due to reduced sensitivity to variations in arsenic flux and the substrate temperature and, consequently, an ordinary artisan would be motivated to utilize a digital alloy growth type for these reasons. Moreover, it is Kawai rather than Kaspi that is relied upon to teach the use of a Si(111) substrate and a continuous As flux.
Finally applicants argue that there is no teaching or suggestion in Toshio that a BEP within the claimed range would be advantageous for Si(111) or that it would be compatible with Sb-based nucleation layers. Id. at pp. 9-10. This argument is not found persuasive as col. 11, ll. 14-32 of Toshio specifically teaches that an As pressure of greater than 3×10-5 Torr results in a transition from p- to n-type on all crystalline growth surfaces, including the (111) surface. Thus, a person of ordinary skill in the art would be motivated to utilize a BEP of greater than approximately 4×10-5 Torr in order to deposit an n-type layer. Moreover, since the Sb-based nucleation layer is comprised of an analogous Group III-V semiconductor which is itself deposited on a Si(111) surface in the method of Kawai and Hudait, there is no reason why this transition from p- to n-type would not occur with the use of the claimed nucleation layer. Stated in other words, this argument is also found unpersuasive because it is based on arguments of counsel rather than factually supported objective evidence.
Conclusion
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/KENNETH A BRATLAND JR/Primary Examiner, Art Unit 1714