DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed April 10, 2026. Claims 1, 12-13, 15, and 20 have been amended. No claims have been added. No claims have been canceled. Currently, claims 1-9, and 11-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 1, 15, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Iwai et al. (US 20100301442 A1) herein after “Iwai” in view of Park et al. (US 20190148423 A1) herein after “Park” and Sasago et al. (US 20200273895 A1) herein after “Sasago”.
Regarding claim 1, Fig. 1 of Iwai discloses an avalanche photodiode (Fig. 1, optical semiconductor device 100, ¶ [0067]), comprising:
a substrate (Fig. 1, substrate 101, ¶ [0067]) including a first side with a first surface (top surface in Fig. 1) and a second side with a second surface (bottom surface in Fig. 1) that is opposite the first surface;
an anode region (Fig. 1, anode contact region 106, ¶ [0067]) disposed in the substrate (101) at the first side of the substrate (101);
an anode electrode (Fig. 1, anode electrode 111, ¶ [0067]) coupled to the anode region (106);
a cathode region (Fig. 1, cathode contact region 107, ¶ [0067]) disposed in the substrate (101) at the first side of the substrate (101);
a cathode electrode (Fig. 1, cathode electrode 110, ¶ [0067]) coupled to the cathode region (107); and
an insulating layer (Fig. 1, isolation region 108, ¶ [0067]) disposed in the substrate (101) at the first side of the substrate (101), wherein the anode electrode (111) or the cathode electrode (110) passes through the insulating layer (108).
Iwai fails to disclose the second surface being a light-incident surface of the substrate;
an insulating layer disposed in the substrate at the first side of the substrate and including a first surface and a second surface opposite the first surface, wherein the anode electrode or the cathode electrode passes through the first and second surfaces of the insulating layer, and wherein the insulating layer is buried in the substrate such that the first surface of the insulating layer is coplanar with the first surface of the substrate; and
a doped region disposed in the substrate and extending between two parts of the insulating layer which contact the cathode region, the doped region contacting the two parts of the insulating layer and having a conductivity type that is opposite a conductivity type of the cathode region.
In the similar field of image sensing devices, Fig. 7 of Park discloses the second surface (Fig. 7, second surface 5b, ¶ [0062]) being a light-incident surface (Fig. 7, “microlenses 94 may redirect a path of light incident”, ¶ [0093]) of the substrate (Fig. 7, semiconductor substrate 5, ¶ [0062]);
an insulating layer (Fig. 7, shallow trench isolation region 10, ¶ [0066]) disposed in the substrate at the first side of the substrate (Fig. 7, “A shallow trench isolation region 10 may be disposed on the first surface 5a of the semiconductor substrate 5”, ¶ [0066]) and including a first surface and a second surface opposite the first surface, wherein the anode electrode or the cathode electrode (Fig. 7, electrode structures 46, ¶ [0068]) passes through the first and second surfaces of the insulating layer (Fig. 7, “the electrode structures 46… may pass through the shallow trench isolation region 10”, ¶ [0071]), and wherein the insulating layer is buried in the substrate such that the first surface of the insulating layer is coplanar with the first surface of the substrate (shown in Fig. 7).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai with the structure as disclosed by Park, to simplify production and improve performance (see Park, ¶ [0135]).
Park fails to disclose a doped region disposed in the substrate and extending between two parts of the insulating layer which contact the cathode region, the doped region contacting the two parts of the insulating layer and having a conductivity type that is opposite a conductivity type of the cathode region.
In the similar field of endeavor of photoelectric conversion apparatuses, Fig. 6B of Sasago discloses a doped region (Fig. 6B, well region 114, ¶ [0059]) disposed in the substrate and extending between two sides of the insulating layer (Fig. 6B, element isolation region 113, ¶ [0065]) which contact the cathode region (Fig. 6B, N-type semiconductor region 111, ¶ [0060]) (indirect contact through the semiconducting layers), the doped region (114) contacting the two parts of the insulating layer (113) and having a conductivity type that is opposite a conductivity type of the cathode region (111) (“The well region 114 is, for example, a P-type semiconductor region”, “N-type semiconductor region 111”, ¶ [0059-0060]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai with the doped region as disclosed by Sasago, to improve device integration (see Sasago, ¶ [0062]).
Regarding claim 2, Iwai, Park and Sasago together disclose the avalanche photodiode of claim 1 as applied above, and Fig. 2 of Iwai further discloses wherein, in a plan view (Fig. 2, “a top view of the optical semiconductor device 100”, ¶ [0068]), the cathode electrode (110) is disposed closer to a center of the avalanche photodiode (100) than the anode electrode (111).
Regarding claim 3, Iwai, Park and Sasago together disclose the avalanche photodiode of claim 2 as applied above, and Fig. 2 of Iwai further discloses wherein, in the plan view (Fig. 2, “a top view of the optical semiconductor device 100”, ¶ [0068]), the cathode electrode (110) surrounds (Fig. 2, “so as to surround the light receiving surface 112”, ¶ [0068]) the center of the avalanche photodiode (100).
Regarding claim 4, Iwai, Park and Sasago together disclose the avalanche photodiode of claim 3 as applied above, and Fig. 2 of Iwai further discloses wherein, in the plan view, the cathode electrode (110) is spaced apart from and surrounds (Fig. 2, “the cathode electrode 110 is positioned on the cathode contact region 107 around a perimeter of the light receiving surface 112”, ¶ [0068]) the center of the avalanche photodiode (100).
Regarding claim 5, Iwai, Park and Sasago together disclose the avalanche photodiode of claim 4 as applied above, and Fig. 2 of Iwai further discloses wherein, in the plan view, the cathode electrode (110) is contiguous (shown in Fig. 2).
Regarding claim 6, Iwai, Park and Sasago together disclose the avalanche photodiode of claim 5 as applied above, and Fig. 2 of Iwai further discloses wherein all sides of the cathode electrode (110) are spaced apart from the center of the avalanche photodiode (100) at a same distance (shown in Fig. 2).
Regarding claim 7, Iwai, Park and Sasago together disclose the avalanche photodiode of claim 3 as applied above, and Fig. 2 of Iwai further discloses wherein, in the plan view, the cathode electrode (110) is surrounded by the insulating layer (108), but Iwai and Park fail to disclose the cathode electrode includes a plurality of cathode portions.
In the similar field of endeavor of photoelectric conversion apparatuses, Fig. 8A of Sasago discloses wherein, in the plan view, the cathode electrode (Fig. 8A, plug 301, ¶ [0068) includes a plurality of cathode portions spaced apart from one another by the insulating layer (113).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai with the cathode region as disclosed by Sasago, to increase pixel integration (see Sasago, ¶ [0089]).
Regarding claim 8, Iwai, Park and Sasago together disclose the avalanche photodiode of claim 7 as applied above, but Iwai and Park fail to disclose wherein each cathode portion is spaced apart from the center of the avalanche photodiode at a same distance.
In the similar field of endeavor of photoelectric conversion apparatuses, Fig. 8A of Sasago discloses wherein each cathode portion (301) is spaced apart from the center of the avalanche photodiode (22) at a same distance.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai with the cathode region as disclosed by Sasago, to increase pixel integration (see Sasago, ¶ [0089]).
Regarding claim 9, Iwai, Park and Sasago together disclose the avalanche photodiode of claim 3 as applied above, but Iwai and Park fail to disclose wherein, in the plan view, the insulating layer extends between two sides of the cathode electrode.
In the similar field of endeavor of photoelectric conversion apparatuses, Fig. 8A of Sasago discloses Iwai, Park and Sasago together
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai with the arrangement as disclosed by Sasago, to increase pixel integration (see Sasago, ¶ [0089]).
Regarding claim 11, Iwai, Park and Sasago together disclose the avalanche photodiode of claim 1 as applied above, but Iwai and Park fail to disclose wherein the insulating layer extends deeper into the substrate than the anode region.
In the similar field of endeavor of photoelectric conversion apparatuses, Fig. 6B of Sasago discloses wherein the insulating layer (113) extends deeper into the substrate (101) than the anode region (see Annotation 1, Fig. 6B of Sasago, AR).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai with the arrangement as disclosed by Sasago, to separate the device regions (see Sasago, ¶ [0065]).
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Annotation 1, Fig. 6B of Sasago
Regarding claim 12, Iwai, Park and Sasago together disclose the avalanche photodiode of claim 3 as applied above, but Iwai and Park fail to disclose wherein:
the doped regio is spaced apart from the cathode region by part of the substrate.
In the similar field of endeavor of photoelectric conversion apparatuses, Fig. 6B of Sasago discloses wherein:
the doped region (114) is spaced apart from the cathode region (111) by a part of the substrate (101).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai with the doped region as disclosed by Sasago, to improve device integration (see Sasago, ¶ [0062]).
Regarding claim 13, Iwai, Park and Sasago together disclose the avalanche photodiode of claim 1 as applied above, but Iwai and Park fail to disclose comprising:
a contact electrode coupled to the doped region and to a node that receives a potential.
In the similar field of endeavor of photoelectric conversion apparatuses, Fig. 6B of Sasago discloses comprising:
a contact electrode (303) coupled to the doped region (114) and to a node that receives a potential (“A well contact portion 303 is provided in the well region 114. The power source line 2000 is electrically connected to the well region 114 via the wiring of each wiring layer. The voltage VDD1 is supplied to the well region 114.”, ¶ [0083]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Iwai (US 20100301442 A1), Park (US 20190148423 A1) and Sasago (US 20200273895 A1) in further view of Lee (Bandwidth Improvement of CMOS-APD With Carrier-Acceleration Technique).
Regarding claim 14, Iwai, Park and Sasago disclose the avalanche photodiode of claim 13 as applied above, but Iwai, Park and Sasago fail to disclose wherein the potential is a ground potential.
In the similar field of endeavor of avalanche photodiodes, Fig. 1 of Lee discloses wherein the potential is a ground potential (Fig. 1, “connecting P-substrate to the ground”, page 2, col. 1, line 3).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai to include the ground potential as disclosed by Lee, to generate a reverse bias at the junctions (see Lee, page 2, col. 1, lines 1-2).
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (JP 2018088488 A) herein after “Tanaka” in view of Park (US 20190148423 A1) and Sasago (US 20200273895 A1).
Regarding claim 15, Fig. 4 of Tanaka discloses a light detecting device (Fig. 4, sensor chip 11A, ¶ [0055]), comprising:
a first substrate (Fig. 4, sensor substrate 41A, ¶ [0057]) including a first side with a first surface and a second side with a second surface that is opposite the first surface, the second surface being a light-incident surface of the first substrate (41A) (Fig. 4, “the surface of the sensor substrate 41 facing downward in FIG. 4 is a light receiving surface that receives light”, ¶ [0026]);
an avalanche photodiode (Fig. 4, SPAD pixels 21A, ¶ [0055]) including:
an anode region (Fig. 4, P-type diffusion layer 56, ¶ [0028]) disposed in the first substrate (41A) at the first side of the first substrate (41A);
an anode electrode (Fig. 4, contact electrode 72, ¶ [0034]) coupled to the anode region (56);
a cathode region (Fig. 4, N-type diffusion layer 53, ¶ [0028]) disposed in the first substrate (41A) at the first side of the first substrate (41A);
a cathode electrode (Fig. 4, contact electrodes 71A, ¶ [0058]) coupled to the cathode region (53); and
a first wiring layer (Fig. 4, sensor side wiring layer 42, ¶ [0025]) on the first surface of the first substrate (41A) and including:
an anode wiring (Fig. 4, contact electrode 78, ¶ [0042]) coupled to the anode electrode (72);
a cathode wiring (Fig. 4, contact electrode 77, ¶ [0042]) coupled to the cathode electrode (71A); and
a plurality of first bonding pads (Fig. 4, metal pad 80, metal pad 81, ¶ [0042]); and
a second substrate (Fig. 4, sensor side wiring layer 42, logic side wiring layer 43, ¶ [0025]) including a second wiring layer (Fig. 4, sensor side wiring layer 42, ¶ [0025]) and circuitry (Fig. 4, logic side wiring layer 43, ¶ [0025]) to process signals output from the avalanche photodiode (21A), the second wiring layer including a plurality of second bonding pads (Fig. 4, metal pad 101, metal pad 102, ¶ [0046]) bonded to the plurality of first bonding pads (80, 81) (Fig. 4, “The metal pads 80 to 82 are used to electrically and mechanically join to the metal pads 101 to 103”, ¶ [0043]).
Tanaka fails to disclose an insulating layer disposed in the first substrate at the first side of the first substrate and including a first surface and a second surface opposite the first surface;
wherein the cathode electrode or the anode electrode passes through the first and second surfaces of the insulating layer, and wherein the insulating layer is buried in the first substrate such that the first surface of the insulating layer is coplanar with the first surface of the first substrate;
a doped region disposed in the first substrate and extending between two parts of the insulating layer which contact the cathode region, the doped region having a conductivity type that is opposite a conductivity type of the cathode region.
In the similar field of image sensing devices, Fig. 7 of Park discloses an insulating layer (Fig. 7, shallow trench isolation region 10, ¶ [0066]) disposed in the first substrate at the first side of the first substrate (Fig. 7, “A shallow trench isolation region 10 may be disposed on the first surface 5a of the semiconductor substrate 5”, ¶ [0066]) and including a first surface and a second surface opposite the first surface,
wherein the cathode electrode or the anode electrode (46) passes through the first and second surfaces of the insulating layer (Fig. 7, “the electrode structures 46… may pass through the shallow trench isolation region 10”, ¶ [0071]), and wherein the insulating layer is buried in the substrate such that the first surface of the insulating layer is coplanar with the first surface of the substrate (shown in Fig. 7).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai with the structure as disclosed by Park, to simplify production and improve performance (see Park, ¶ [0135]).
Park fails to disclose a doped region disposed in the first substrate and extending between two parts of the insulating layer which contact the cathode region, the doped region having a conductivity type that is opposite a conductivity type of the cathode region.
In the similar field of endeavor of photoelectric conversion apparatuses, Fig. 6B of Sasago discloses a doped region (114) disposed in the first substrate and extending between two sides of the insulating layer (113) which contact the cathode region (111) (indirect contact through the semiconducting layers), the doped region (114) having a conductivity type that is opposite a conductivity type of the cathode region (111) (“The well region 114 is, for example, a P-type semiconductor region”, “N-type semiconductor region 111”, ¶ [0059-0060]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai with the doped region as disclosed by Sasago, to improve device integration (see Sasago, ¶ [0062]).
Regarding claim 16, Tanaka and Park together disclose the light detecting device of claim 15 as applied above, and Fig. 4 of Tanaka further discloses wherein the plurality of first bonding pads (80, 81) and the plurality of second bonding pads each include a bonding pad (101, 102) electrically connected to the anode wiring (78) and a bonding pad electrically connected to the cathode wiring (77) (Fig. 4, “The contact electrode 77 connects the metal wiring 74 to a metal pad 80 , the contact electrode 78 connects the metal wiring 75 to a metal pad 81”, “The metal pads 80 to 82 are used to electrically and mechanically join to the metal pads 101 to 103”, ¶ [0042-0043]).
Regarding claim 17, Tanaka and Park together disclose the light detecting device of claim 16 as applied above, and Fig. 5 of Tanaka further discloses wherein, in a plan view, the cathode electrode (71A) is disposed closer to a center of the avalanche photodiode (21A) than the anode electrode (72).
Regarding claim 18, Tanaka and Park together disclose the light detecting device of claim 17 as applied above, and Fig. 5 of Tanaka further discloses wherein, in the plan view, the cathode electrode (71A) surrounds (Fig. 5, “four contact electrodes 71A are arranged at the four corners”, ¶ [0058]) the center of the avalanche photodiode (21A).
Regarding claim 19, Tanaka and Park together disclose the light detecting device of claim 17 as applied above, and Fig. 5 of Tanaka further discloses wherein, in the plan view, the cathode electrode (71A) is spaced apart from and surrounds (Fig. 5, “four contact electrodes 71A are arranged at the four corners”, ¶ [0058]) the center of the avalanche photodiode (21A).
Regarding claim 20, Fig. 14 of Tanaka disclose an electronic apparatus, comprising:
a light source (Fig. 14, light source device 211, ¶ [0103]) that emits modulated light toward and object (Fig. 14, “the subject by receiving light (modulated light or pulsed light) projected from the light source device 211”, ¶ [0103]); and
an avalanche photodiode (Fig. 14, “The sensor chip 11 according to each of the above-described embodiments is applied as the sensor chip 203”, ¶ [0105]) that senses the modulated light reflected from the object (Fig. 14, “The optical system 202 is configured to have one or more lenses, and guides image light (incident light) from a subject to the sensor chip 203”, ¶ [0104]), the avalanche photodiode (21A) including:
a substrate (41A) including a first side with a first surface and a second side with a second surface that is opposite the first surface, the second surface being a light-incident surface of the substrate (41A);
an anode region (56) disposed in the substrate (41A) at the first side of the substrate (41A);
an anode electrode (72) coupled to the anode region (56);
a cathode region (53) disposed in the substrate (41A) at the first side of the substrate (41A); and
a cathode electrode (71A) coupled to the cathode region (53).
Tanaka fails to disclose an insulating layer disposed in the substrate at the first side of the substrate and including a first surface and a second surface opposite the first surface;
wherein the cathode electrode or the anode electrode passes through the first and second surfaces of the insulating layer, and wherein the insulating layer is buried in the substrate such that the first surface of the insulating layer is coplanar with the first surface of the substrate; and
a doped region disposed in the first substrate and extending between two parts of the insulating layer which contact the cathode region, the doped region having a conductivity type that is opposite a conductivity type of the cathode region.
In the similar field of image sensing devices, Fig. 7 of Park discloses an insulating layer (Fig. 7, shallow trench isolation region 10, ¶ [0066]) disposed in the substrate (5) at the first side of the substrate (Fig. 7, “A shallow trench isolation region 10 may be disposed on the first surface 5a of the semiconductor substrate 5”, ¶ [0066]) and including a first surface and a second surface opposite the first surface,
wherein the cathode electrode or the anode electrode (46) passes through the first and second surfaces of the insulating layer (Fig. 7, “the electrode structures 46… may pass through the shallow trench isolation region 10”, ¶ [0071]), and wherein the insulating layer is buried in the substrate such that the first surface of the insulating layer is coplanar with the first surface of the substrate (shown in Fig. 7).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai with the structure as disclosed by Park, to simplify production and improve performance (see Park, ¶ [0135]).
Park fails to disclose a doped region disposed in the first substrate and extending between two parts of the insulating layer which contact the cathode region, the doped region having a conductivity type that is opposite a conductivity type of the cathode region.
In the similar field of endeavor of photoelectric conversion apparatuses, Fig. 6B of Sasago discloses a doped region (114) disposed in the first substrate and extending between two sides of the insulating layer (113) which contact the cathode region (111) (indirect contact through the semiconducting layers), the doped region (114) having a conductivity type that is opposite a conductivity type of the cathode region (111) (“The well region 114 is, for example, a P-type semiconductor region”, “N-type semiconductor region 111”, ¶ [0059-0060]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the photodiode disclosed by Iwai with the doped region as disclosed by Sasago, to improve device integration (see Sasago, ¶ [0062]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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